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J-M Sainson INTEGRITY ANALYSIS AT CERN J. Evans CERN IT/CE-AE

[email protected] (Intranet) http://cern.ch/support-specctraquest

HIGH-SPEED DIGITAL DESIGN ANALYSIS UNDER CADENCE

Pre-Layout Analysis SPECCTRAQuestTM Design Flow Post-Layout Analysis

Design Choices and Layout Guidelines Layout Checks Layout Enhancements

Concept (Before Manufacturing) (On Existing Board) CADENCE's Simulation SPECCTRAQuestTM SI expert (Schematic) Ÿarchitectures evaluation ŸPCBs stackup specification Allegro to Front End (Signal Integrity Analysis Package) (Backannotati Ÿpre layout vs. post layout Ÿanalyze signal integrity (bus, clock tree,..) Ÿlines cross-section Design Choices simulations correlation phenomena on unreliable Ÿtopologies exploration specification (microstrip, Signal Explorer printed circuit boards ) (Topology Explorer) Ÿpossible Ÿstandard ICs technologies on) Layout changes Ÿidentify tracks having: comparison Ÿlines impedance (Zo) and Guidelines (Front End to Allegro) - excessive reflections/ Ÿlast modifications on the Ÿterminations type and tolerance specification IBIS Models SPECCTRAQuest Import Database Allegro crosstalk (Behavioral) (Floor Planner) (Board Layout) "virtual board" at value characterization Ÿterminations location - too fast technology Layout Checks minimum cost before and/or ŸASIC's I/O cells Ÿtracks spacing Enhancements manufacturing ŸSPECCTRAQuest "what characterization SigNoise if" capability can help to Ÿmax/min tracks length (Behavioral Ÿreduce hardware Simulator) CADENCE's find optimum solution Ÿpackages type selection Ÿbussed tracks skew PCB System Design prototype Ÿworst case simulations Ÿ...

MAIN SIGNAL INTEGRITY (SI) EXPRESSIONS

A Track must be considered as Equivalent Bandwidth of a Digital Effective Loaded Backplane a Transmission Line when: Signal with Switching Time (tr): (Zeff): Ex: Zeff = 43 Ohm for 18 stubs 30 cm long backplane, Ex: critical length = 1.7" (4cm) for Ex: F = 640 MHz for with Zo = 75 Ohm ,C = 45 pF (1.5pF/cm), Cload = 5 pF x18 = 90pF 10KE ALTERA/FLEX FPGA 10KE ALTERA / FLEX (tr = 0.5ns) on microstrip line FPGA (tr = 0.5ns) Zo = Unloaded transmission line characteristic impedance (tpd = 150 ps/inch) C = Total unloaded backplane transmission line capacitance Cload = Total load capacitance along the backplane line (connector, stub, IC package)

TYPICAL PRE-LAYOUT BUS DESIGN ANALYSIS

Typical Backplane & On Board BUS Systems Equivalent Backplane Schematic Under SigXplorer Backplane Simulation Example

Connectors Effect: With XILINX/Virtex GTL I/O Terminations Connectors Plugged Board Impedance Equivalent R, L, C circuit Effect Effect & Tolerance Effects under SigXplorer. (NNR Effect)

VIH GTL = 0.850V

ICs Packages Effect VIL GTL = 0.750V

Silicon Speed Effect

Backplane Partially Impedance & Loaded Tolerance Effect Backplane Effect Stubs Effect

Minimum margin (50mV) on NNR location (purple wave)

Terminations Effect - IBIS model: I/O Virtex XILINX/GTL Connectors Board Impedance Effect - Termination type: Shunt 40 Ohm & Tolerance Effects - Zo: 50 Ohm Stubs Effect - Transmission line: Microstrip ICs Packages Effect Terminations Effect: Silicon Speed Effect: Stubs Effect: Backplane Impedance & "What if" analyses for Driver switching time (tr, tf) is Equivalent transmission Tolerance Effects: - Line length: 40 cm termination type and value a key parameter modeled by line under SigXplorer. Equivalent stripline or Silicon Speed Effect under SigXplorer. the IBIS model. microstrip line with sweep - Frequency 40 MHz Nearest Neighbor capability under SigXplorer. - Stub number: 20 Receiver Effect (NNR) ICs Packages Effect: All package and silicon - Driver: central location of the BUS parasitics are defined in the IBIS model.

IBIS SIGNAL INTEGRITY MODELING STANDARD

ASICs I/O Cells Model Generation Why use the "IBIS" Modeling Standard Input Model Power clamp I-V (SPICE Netlist to IBIS Format Translation) for Signal Integrity Simulations? Vcc IBIS I/O Cells Silicon Behaviour Package Parasitic IBIS ASCII File IBIS Behavioural Model & Power_Clamp Circuit Standard Die Parasitic [Model] Signal Integrity Standard R_pkg L_pkg SPICE Transistor Model SPICE I/O Cells Entry [Voltage Range] (ANSI/EIA-656-A) SPICE Netlists [Pulldown] C_pkg Gnd_Clamp C_comp Formats: Ÿbest for circuit designer Ÿideal for system level ŸHSPICE SPICE to IBIS Software: R ŸCadence's SPITRAN Pullup] GND ŸSPECTRE interconnect design GND Die ŸEIA spice2ibis Ÿsimulates very slowly, because GND clamp GND capacitor ŸPSpice R I-V [GND Clamp] voltage/current relationship are Ÿsimulates faster because Ÿetc.. calculated from lower level data voltage/current/time [POWER Clamp] relationships given only for the Ÿeach device in the buffer is [Ramp] (dV/dt_r and dV/dt_f ratios) Ramp up Power external nodes of the entire SPICE or Pull-up clamp modeled/simulated individually Output Model Transistor Level Model buffer V-t I-V I-V Ÿreveals process and intellectual Vcc Vcc nt A]

Ÿno circuit detail involved [

property Silicon Behaviour Package Parasitic Curre Voltage [V] Ÿhides both process and circuit Pull- Power & Ÿtoo slow for system level up Clamp Die Parasitic IBIS R_pkg L_pkg Behavioral Model interconnect design intellectual property Ÿlimited use for circuit designers Pulldown Ground C_comp C_pkg Clamp

GND GND GND GND

IBIS (I/O Buffer Information Specification) ANSI/EIA- 656-A Ramp Pulldown GND HSPICE/PSpice to IBIS application notes available on down I-V clamp or I-V http://cern.ch/support-specctraquest (How to) menu www.eigroup.org/ibis/ V-t