Signal integrity and simultaneous switching noise of CMOS devices and systems
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Authors Senthinathan, Ramesh, 1961-
Publisher The University of Arizona.
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Link to Item http://hdl.handle.net/10150/565539 SIGNAL INTEGRITY AND SIMULTANEOUS SWITCHING NOISE OF CMOS DEVICES AND SYSTEMS
by Ramesh Senthinathan
A Dissertation Submitted to the Faculty of the
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
In Partial Fulfillment of the Requirements For the Degree of DOCTOR OF PHILOSOPHY WITH A MAJOR IN ELECTRICAL ENGINEERING
In the Graduate College THE UNIVERSITY OF ARIZONA
19 9 2 2 THE UNIVERSITY OF ARIZONA GRADUATE COLLEGE
As members of the Final Examination Committee, we certify that we have read the dissertation prepared by ^ames^L Senthinathan______entitled "Signal Integrity and Simultaneous Switching Noise of CMOS
Devices and Systems"
and recommend that it be accepted as fulfilling the dissertation requirement for the Degree of Doctor of Philosophy______
7/6/1992 17 Date 7/6/1992 Date 7/6/1992
Date 7/6/1992 Date 7/6/1992 Date Dr. Stephan W. Koch
Final approval and acceptance of this dissertation is contingent upon the candidate's submission of the final copy of the dissertation to the -c Graduate College.
I hereby certify that I have read this dissertation prepared under my ;~ direction and recommend that it be accepted as fulfilling the dissertation requirement. "
7/6/1992 Dissertation DirectorDr. John L. Prince Date 3
STATEMENT BY AUTHOR
This dissertation has been submitted in partial fulfillment of requirements for an advanced degree at The University of Arizona and is deposited in the Uni versity Library to be made available to borrowers under rules of the library. Brief quotations from this dissertation are allowable without special per mission, provided that accurate acknowledgement of source is made. Requests for permission for extended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the major department or the Dean of the Graduate College when in his or her judgment the proposed use of the material is in the interests of scholarship. In all other instances, however, permission must be obtained from the author.
SIGNED: 4
ACKNOWLEDGEMENTS
My most sincere gratitude is for my advisor Prof. John L. Prince. During the entire period of my graduate studies at the University of Arizona (including my M.S. degree), he has not only helped me with technical matters but also given me lots of encouragement and support. Prof. Prince has provided me with financial support as a research assistant for my entire six years of study at the University of Arizona. My sincere thanks to Prof. Andreas C. Cangellaris for his valuable advise, comments and suggestions through out my Ph.D work. My special thanks to him for helping me understand many doubts in the microwave area. I thank many electrical engineering, physics, and mathematics department professors who have helped me understand with greater depth and overcome many doubts. My special thanks to Professors Ronald D. Schrimpf, Oliged A. Palusinski, Michael Scheinfein, and Douglas Hamilton. Thanks to Honeywell, GTE, Hestia and IBM corporations for valuable sum mer intern experience. My special thanks to Intel corporation, Arizona, for a very valuable two and a half years circuit/ system design experience, and for sponsoring my permanent resident visa status. I thank my co-workers and friends, B. Al-Masri, M. Gribbons, P. Hsu, A. Mehra, S. Nimmagadda, S. Sudharshanan and S. Voranantakul for many fruitful technical and philosophical discussions. A very special thanks to my parents for constant encouragement, and sup port from pre-school to Ph.D degree. I thank my wife Logini for her patience, support and encouragement. To my father Ramalingam Senthinathan and in memory of my mother Maheswary Senthinathan^ 6
TABLE OF CONTENTS
Page
LIST OF ILLUSTRATIONS...... 10 LIST OF T A B L E S...... 15 ABSTRACT...... 16 CHAPTER 1 - INTRODUCTION...... 18 1.1 Background ...... 18 1.2 Introduction...... 20 CHAPTER 2 - PERFORMANCE OF SCALED AND PACKAGED CMOS DEVICES/SYSTEMS ...... 25 2.1 Introduction...... 25 2.2 Interconnect Scaling ...... 26 2.3 Behavior of Delays with Driver/Interconnect Scaling...... 30 2.4 S u m m a r y ...... 36 CHAPTER 3 - METHODS OF CALCULATING SIMULTANEOUS SWITCHING NOISE (S S N )...... 37
3.1 Introduction ...... 37 3.2 Theory and M o d elin g ...... 38
3.3 Ground Noise and Vss Pad-Pin Connection C alculation...... 46 3.4 Results ...... 47 3.5 Behavior of Simultaneous Switching Noise with Scaling ...... 51 3.6 Summary ...... 53 7
TABLE OF CONTENTS - Continued
Page CHAPTER 4 - THE MODELING OF POWER/GROUND PLANE PARASITICS AND THEIR CONTRIBUTION TO THE “EFFECTIVE” INDUCTANCE OF VDD/Vss PACKAGE INTERFACE ...... 54 4.1 Introduction...... 54 4.2 Mathematical Formulation of U A L G R L ...... 57 4.3 Effective Inductance “Lyss” Modeling ...... 59 4.4 Reference Plane Inductance Network Calculation ...... 66 4.5 Results ...... 69 4.6 Summary ...... • ...... 77 CHAPTER 5 - CHARACTERISTICS OF SIGNAL PROPAGATION OVER PERFORATED REFERENCE PLANES ..... 78 5.1 Introduction...... 78 5.2 Impact of Reference Plane Openings for Stripline Geometries . . . 85 5.3 Connector Characterization Using S-Parameter Measurement Techniques...... 87 5.4 Modeling Using Two Dimensional (TEM) Approximation .... 92 5.5 Three-Dimensional Modeling Technique ...... 97 5.6 Comparison Between Measurement and Sim ulations...... 104 5.7 Full-Wave Analysis of a Periodically Perforated Structure .... 109 5.8 Summary ...... 117 8
TABLE OF CONTENTS — Continued
Page CHAPTER 6 - NOISE IMMUNITY CHARACTERISTICS OF CMOS RECEIVERS AND EFFECTS OF SKEWING/DAMPING CMOS DRIVER SWITCHING WAVEFORM ON THE “SIMULTANEOUS” SWITCHING N O IS E ...... 119 6.1 Introduction...... 119 6.2 Driver Switching Noise and Receiver Noise Immunity ...... 122 6.3 Effects of Skewing Output Drivers ...... 126 6.4 Trade-offs in Using Damping Resistors ...... 131 6.5 Summary ...... 134 CHAPTER 7 - APPLICATION SPECIFIC OUTPUT DRIVER CIRCUIT TECHNIQUES TO REDUCE SIMULTANEOUS SWITCHING NOISE ...... 136 7.1 Introduction...... 136 7.2 CMOS Output Driver Switching Current Com ponents...... 137 7.3 Current Controlled Output D r iv e r s ...... 140 7.4 Controlled Slew Rate Output Drivers ...... 142 7.5 Summary ...... 155 CHAPTER 8 - SIMULTANEOUS SWITCHING NOISE SIMULATOR (SSNS) ARCHITECTURE ...... 157 8.1 Introduction ...... 157 8.2 SSNS Architecture ...... 158
8.3 “Lvss” Modeling for MCM Vss Connections ...... 161 8.4 Simultaneous Switching Noise Calculation for CMOS MCMs . . . 164
8.5 Summary ...... 170 9
. TABLE OF CONTENTS - Continued
Page CHAPTER 9 - CONCLUSIONS ...... 171 CHAPTER 10 - DISSCUSSION AND FUTURE WORK ...... 174 10.1 BiCMOS Outputs Simultaneous Switching Noise ...... 174 10.2 Use of Substrate-Taps to Reduce Simultaneous Switching Noise . 176 10.3 SSNS Architecture Improvement ...... 178 REFERENCES ...... 181 10
LIST OF ILLUSTRATIONS
Figure Page 2.1 Typical on-chip (Si — SiOz) interconnect structure ...... 27 2.2 A CMOS Inverter with device/ interconnect parasitics ...... 31 2.3 Delays with [CV] scaling using exact, approximate, and no interconnect parasitics va lu es...... 32 2.4 Normalized capacitance and resistance with [CV] scaling ...... 34 3.1 Typical multilayer chip-package interface parasitics ...... 39 3.2 CMOS output driver with lumped package parasitics ...... 40 3.3 Typical CMOS output driver switching characteristics ...... 41
3.4 On-chip Vdd/Vss bus, and noise feed through mechanisms ..... 42 3.5 Ground noise vs. # of simultaneous switching output drivers .... 48 3.6 Ground noise vs. # of ground pad-pin connections ...... 50 3.7 Simultaneous switching noise as a function of [CV] s c a lin g ...... 52
4.1 Typical “direct-connection” package Vss connections ...... 56 4.2a Perforated Vss plane with multiple sink/source points [4.5] .... 60
4.2b Contour “c” used in equation ( 4 . 7 ) ...... 60 4.3a Single chip-package interface m o d e l...... 61 4.3b Equivalent inductance network ...... 61 4.4a Current distribution on a Vss plane without perforations ...... 64
4.4b Current distribution on a Vss plane with perforations...... 64
4.5 Perforated copper Vss plane with two arbitrary rectangular cuts . . 65
4.6a A Vss plane with three Vss p i n s ...... 67 11
LIST OF ILLUSTRATIONS - Continued
Figure Page
4.6b Equivalent inductance network of Figure 4.7 Vss p la n e ...... 67
4.7 A non-perforated Vss plane with eight sink points ...... 70 4.8 A perforated Vss plane with eight sink points ...... 71 4.9 Comparison of perforated and non-perforated Vss plane inductance vs. # of sink points ...... 73 4.10 3 mA drivers, 16 outputs simultaneous switching noise ...... 75 4.11 12 mA drivers, 32 outputs simultaneous switching n o i s e ...... 76 5.1 Equivalent circuit model of a perforated reference plane stripline interconnect stru ctu re...... 79 5.2 Scaled-up, perforated reference plane stripline model ...... 81 5.3 Scaled-up model crossection ...... 82 5.4 Periodically perforated card structure ...... 83 5.5 Card structure interconnect crossection ...... 84 5.6 Stripline, buried microstripline impedance vs. conductor height . . . 86 5.7 Reflection coefficient (p), AZ vs. conductor height ...... 88 5.8 Two-port network equivalent transmission line model ...... 90 5.9 TDR measurement setup and connections ...... 93
5.10 Two-dimensional (PUL) capacitance/ inductance modeling ..... 95 5.11 Total, scale model measured and calculated capacitance values . . . 96 5.12 Three-dimensional inductance modeling ...... 98
5.13 X-Y bar formations for 3-D inductance modeling ...... 99 12
LIST OF ILLUSTRATIONS - Continued
Figure Page 5.14 Total, and AL inductance values vs. conductor/ plane thickness . . . 100 5.15 Comparison between 2-D and 3-D inductance values ...... 102 5.16 Total inductance with and without perforation vs. conductor height . 103 5.17 Inductance modeling for “gap” type perforation discontinuity . . . 105 5.18a Comparison between measurements and simulations for stripline . . 106 5.18b Measurements and simulations for 5x1 cm perforation size .... 106 5.19a Measurements and simulations for 5x4 cm perforation size .... 107 5.19b Measurements and simulations for 5x8 cm perforation size .... 107 5.20a Measurements and simulations for 10x1 cm perforation size .... 108 5.20b Measurements and simulations for 10x4 cm perforation size .... 108 5.21a Measurements and simulations for 10x8 cm perforation size.... 110 5.21b Measurements and simulations for 20.4x20.4 cm perforation size . . 110 5.22a Signal disturbance (AV) vs. perforation length for 5 cm
perforation window width ...... Ill
5.22b AV vs. perforation length for 10 cm perforation window width . . Ill
5.23 A y vs. perforation area (different widths) ...... 112 5.24 Card structure, unit cell discontinuity inductance modeling .... 114 5.25 Return current path on the top perforated reference p la n e ...... 115
5.26 Measurement and simulation comparison for eleven perforated model 116 6.1 Typical input receiver noise immunity characteristics ...... 121 6.2 Ground noise vs. # of simultaneously switching outputs ...... 124 13
LIST OF ILLUSTRATIONS - Continued
Figure Page 6.3 TTL level compatible CMOS receiver noise immunity behavior . . . 125 6.4 Effects of ground noise feed through from D.C. “ON” drivers . . . 127 6.5 Effects of skewing CMOS output drivers ...... 128 6.6 Performance vs. switching noise limitations on output drivers . . . 130
6.7 Underdamped oscillatory ground noise behavior ...... 132 6.8 Effects of damping resistor on the switching noise ...... 133 7.1a CMOS output driver switching characteristics...... 138 7.1b Voltage switching characteristics ...... 138 7.1c Current switching characteristics ...... 138 7.2 Current controlled CMOS output driver ...... 141 7.3 Switching current controlled/ unregulated CMOS output driver . . . 143 7.4 A typical tri-statable (enable high) CMOS output driver ..... 144
7.5 High-speed, tri-statable (enable low) CMOS output driver . . . . . 146 7.6 Tri-State output driver switching characteristics ...... 148 7.7 Driver delay-switching noise limitations ...... 149 7.8 Tri-statable, Controlled Slew Rate (CSR) output driver ...... 150 7.9 CSR output driver voltage switching characteristics ...... 153
7.10 CSR output driver current switching characteristics ...... 154 8.1 Simultaneous switching noise simulator (SSNS) trial architecture . . 159 8.2 Multi-chip module chip-package Vss connections ...... 162 8.3 Multi-chip module “Lyss” inductance network model ...... 163 14
LIST OF ILLUSTRATIONS - Continued
Figure Page
8.4 SSN vs. MCM integration level (10-5 % Vss connections) ..... 168 8.5 SSN vs. MCM integration level (20-10 % Fss connections) .... 169
10.1 A typical BiCMOS output driver circuit , ...... 175 10.2 Substrate-Taps current spreading ...... 177 10.3 Chip-Package interface paxasitics with substrate-taps...... 179 15
LIST OF TABLES
Table Page 2.1 Scaling rules used for this analysis ...... 26 2.2 First order device performance with scaling...... 26 2.3 Driver-interconnect performance with scaling (approximate calculation of parasitics)...... 33 2.4 Six-cell chain delays, A = 1 ...... 35 3.1 Ground noise with and without negative feedback influence ..... 49 4.1 Effect of perforations on Lpiane and RpUne v a lu e s...... 66 4.2 Inductance [Lij] calculations ...... 68 5.1 Touchstone-calculated lumped-element values and optimization
error (e) ...... 91 5.2 Comparison of calculated lumped-element v a l u e s ...... 101 5.3 Comparison of calculated lumped-element v a l u e s ...... 117 7.1 Tri-statable(enable high) CMOS output d r iv e r ...... 145 7.2 High-speed, tri-statable (enable low) CMOS output d r iv e r .....145 7.3 Performance-simultaneous switching noise comparison for
CSR with conventional output d riv ers...... 155 8.1 MCM CMOS chip integration parameters ...... 167 8.2 MCM integration: Driver and package parameters ...... 167 16
ABSTRACT
A method of calculating Simultaneous Switching Noise (SSN) for Comple mentary Metal Oxide Semiconductor (CMOS) based systems has been developed and investigated in detail. This model includes output driver negative feedback effects, where as previous models do not include these effects. Several closed-form equations were derived to incorporate negative feedback effects in SSN calculations. Results were compared with the well referenced circuit simulator SPICE, and with
measured values. A method of modeling effective inductance of the Vd d /Vss chip- package interface has been developed. This model includes the effects of package
pin placement, and perforations (if any) in Vd d /Vss planes. These models have been implemented in a SSNS (Simultaneous Switching Noise Simulator) architec ture. This architecture can be used for calculating SSN for CMOS single packaged chip, or multi-chip assemblies (i.e. MCM, COB, and etc). Device and package interconnect scaling rules were employed to verify performance degradation and limits due to chip-package parasitics. Results were compared using approximate and detailed University of Arizona (UA) simulation tools, and future trends are predicted.
Also, detailed investigations were performed to characterize signal prop
agation over perforated reference (Vdd/Vss) planes. A scaled-up model, and a periodically perforated FR-4 card structure were fabricated, and modeled using 2- D, 3-D and S-parameter extraction tools. Simulation results were compared with TDR measured values.
Mechanisms which cause false switching due to the chip-package and 17 package-system. interface-generated noise were analyzed. Impact of coupled and SSN on digital systems was investigated using noise immunity characteristics of CMOS input receivers. Output driver design techniques, such as damping and/or skewing output switching waveform to reduce SSN, were analyzed and design guidelines/ rules-of-thumb have been developed. Application specific circuit design techniques to reduce SSN are explained. 18
C H A P T E R 1
INTRODUCTION
1.1 Background
Simultaneous Switching Noise (SSN) (also known as delta-I noise or ground bounce) is a voltage glitch induced at the chip-package power distribution connec tions, due to an inductively induced voltage drop, when internal gates and/or out put drivers switch simultaneously. In reality, output driver current drive capability (measure of delay to drive a specific capacitive load) is much greater than the in ternal gates. This is because output drivers have to drive output loading as well as package and board parasitics. This results in the rate of change in output drivers switching current being much greater than the rate of change in switching current in internal gates, (outputs) » £(i)— ] (internal gates') ( 1.1) Here within the time interval T0 — St to T0 + St (where St is very small time) there are n number of output drivers and m number of internal gates switching from logic “1” to logic “0” or vice versa. Because of the condition described by equation (1.1),
SSN is often associated solely with the output drivers switching simultaneously. There are several inductances that are inherent in the power distribution network from the external power sources to the on-chip power connections. In order to calculate the SSN at the chip-package interface, it is essential to calculate the associated inductances. Note that, the definition of inductance is not a very pre cise concept unless one introduce a complicated topological description. However, 19 a simple definition of inductance rests on the concept of flux linkage [1.1]. Self in ductance L of a current carrying circuit can be defined as the flux linkage per unit current [1.1],
L = ^ (1.2) where d From equations (1.2) and (1.3), V (1.4) This voltage drop appears in series with the ground and in series with power connec tions to the voltage source outside the package. Thus the on-chip supply voltage is decreased, and the on-chip ground voltage is increased (the ground voltage “bounces up”) by this mechanism. A detailed discussion of the origin and of the circuit effects of SSN (for CMOS circuits) is contained in Chapter 3. Note that, the inherent chip-package inductances and the rate of change in the total switching current contributes to the switching noise. Due to the complex chip-package power distribution connections in present state of the art packaged systems, it is necessary to model these inductances that are inherent in the power distribution connections using rigorous modeling tools. This is because the accu racy of calculated SSN values very much depend on the accuracy of the calculated inductance values. Since multiple current paths exists from ideal power sources to the chip power rails (or buses), an inductance network is in order to study the impact of each path on the effective inductance. 20 Initial work on modeling , and calculating SSN for digital systems were given by G. A. Katopis [1.3], A. J. Rainal [1.4], and E. E. Davidson [1.5]. However, in the past it was assumed that SSN is directly proportional to the number of outputs switching simultaneously. For example, when n number of outputs switch simultaneously, each with identical di/dt, the SSN was wrongly taken to be di Yn — n Leff — . (1-5) Here Le/ / is the effective lumped inductance obtained from the inductance network. In this work, a detailed method of calculating SSN for CMOS based systems is given. This methodology includes the negative feedback effects which are very important in calculating SSN. Previous models do not include these effects, and in their methodology SSN is calculated using equation (1.5). This work will present an important, accurate equation to replace equation (1.5). To study the performance and SSN for future CMOS based systems, a detailed analysis of device and interconnect scaling was performed using rigorous parasitic extraction software tools. A systematic approach to modeling the induc tance network associated with the power distribution, and a method of reducing this inductance network to an equivalent effective inductance is explained. Some techniques to reduce SSN are explored in this work. A detailed methodology and a Simultaneous Switching Noise Simulator (SSNS) based on a trial architecture were developed to calculate, and to minimize SSN for CMOS based systems. In the next Section, each of the Chapters are introduced, and their contents are summarized. 1.2 Introduction In order to obtain high speed and high density, MOS devices are scaled down. Scaling schemes such as constant field [CE], constant voltage [CV], and 21 quasi-constant voltage [QCV] have been analyzed. To achieve high interconnect density, interconnects are also constantly scaled down with device scaling. Due to increase in system speed and density, designers are confronted with several practical problems imposed by interconnect structures and electrical connections at the chip- package interface. In addition to the maximum operating frequency degradation due to the interconnect parasitics, when the output drivers switch they generate noise at the chip-package interface as well as at the on-chip Vd d /Vss buses. As the devices are scaled down in CMOS device packaged systems, out put driver delay to drive off-chip interconnects decreases. However the decrease in delays does not decrease linearly with device scaling. When we scale down the channel lengths (£ e//) into sub-micron regions (Leff < l/xm), the dominant part of the overall delays in a system are due to off-chip interconnects. It is important to calculate interconnect parasitics with high accuracy in order to calculate the maximum system operating frequency accurately. In Chapter 2 the performance of scaled CMOS drivers together with off-chip interconnect is calculated using the con stant voltage device scaling scheme. Results were compared using both approximate closed-form equations, and more detailed UA software tools. In present high-speed chips, the output driver is a major contributor to the pin-to-pin delays because of capacitive output loading as well as package and board parasitics. To obtain high speed from these output drivers, often the drive current capabilities are increased by increasing the output driver circuit channel width. The increase in current drive capability may induce large power/ ground noise caused by “through-current” transients [1.6], due to many outputs switching simultaneously. Since the input circuits are connected to the same power/ ground bus, power/ ground noise must be controlled to avoid any false switching. Often, internal power/ground buses are separated from the external (I/O driver circuit) 22 power/ ground buses. However, these internal and external buses are connected to Vdd/Vss planes in multilayer packages. Thus electrical decoupling is not assured. Detailed methods of calculating simultaneous switching noise (SSN), including the negative feedback influence is explained in Chapter 3. For a given design, knowing the maximum tolerable noise levels, an algorithm is described which calculates the minimum number of Vdd/Vss bond-pad and package-pin connections required to avoid any false switching due to SSN. Often Vd d /Vss connections from a chip boundary are multiple connec tions (wire bonding, tape-automated-bonding, controlled collapse connection (C4)) to Vdd/Vss planes. Package pins are connected to Vd d /Vss planes, and exact placements of these pins depend on the package type. For example, Pin-Grid-Array (PGA) packages have pins placed in an array configuration, quad-flat-packs (QFP) have pins in all four perimeters, and dual-in-line packages (DIP) have pins on two opposite long perimeters. Due to these complicated connections, defining a single lumped resistance, inductance, and capacitance from an on-chip Vd d /Vss bus to the tip of a Vdd/Vss package pin is difficult. Especially, defining an equivalent effective inductance requires a very good understanding of the current path in the plane. If any perforations are present in Vdd/Vss planes, the current path will gen erally be affected and this gives rise to increases in the effective inductance of these Vd d /Vss planes. In Chapter 4 a method of modeling effective inductance including the effects of current distribution on Vdd/Vss planes is analyzed. The UA software tool called UALGRL [1.7] was used to calculate the plane effective inductance. An inductance network is developed using superposition theory to ascertain the impact of each of the package pin locations on the total effective inductance. Guidelines on Vd d /Vss package-pin placements are given to minimize SSN, and to decouple output driver SSN from input and internal circuits. The methodology explained in 23 Chapter 4 is also applicable to perforated Vdd/Vss (reference) planes. Discontinuities to an ideal transmission line can degrade the signal integrity of an output driver transmitted signal. When the supply voltages are scaled down from 5 volts to 3.3 volts, as is currently happening, the noise margin of CMOS cir cuits decrease. In Chapter 5 signal propagation over perforated reference planes is investigated. The perforations cause impedance discontinuities which degrades sig nal quality. To avoid false switching, it is essential to understand and estimate this \ noise within engineering accuracy. A scaled-up model and a periodically perforated FR-4 card structure were fabricated for this study. Both 2-D, 3-D, and S-parameter modeling tools were used to extract additional parasitics associated with perfora tions. These parasitics (AT, AC) are used in conjunction with transmission line models to compensate for additional delays caused by return current discontinuity on the reference plane due to perforations. Simulations were performed using a circuit simulator called ASTAP [1.8]. The simulation results were compared with TDR (Time Domain Reflectometry) measured values. Due to size and/or cost requirements, a single chip or a multi-chip assembly system can be I/O pad-pin limited, i.e. the number of bond-pads and package-pins may beat the maximum permitted. For such an I/O pad-pin limited system, the designer may be confronted with the problem of minimizing the effective SSN by design methods other than simply decreasing inductance by manipulating pads and pins. To use some other design techniques, one needs to understand the noise im munity characteristics of the circuits that are connected to noisy Vd d /Vss on-chip buses or noisy Vd d /Vss package planes. Noise feed through mechanisms at the chip-package interface are explained in Chapter 6. The characteristics of CMOS in put receiver circuit noise immunity in a system are analyzed. Techniques of damping and skewing CMOS output switching waveforms, to reduce SSN are explained and 24 demonstrated. Trade-offs and guidelines to use such design techniques to reduce effective SSN are explained in Chapter 6. In Chapter 7, application specific circuit design techniques to reduce SSN are explained. As explained earlier, two methods of reducing SSN are used in practice. One method is to use circuit design techniques, and the other method is to reduce the effective inductance (Te// ) seen by the output driver on Vd d /Vss paths. A trial architecture for a system called UASSNS (University of Arizona Simultane ous Switching Noise Simulator) was developed to model and verify SSN using both methods. This tool is developed to guide a system designer in calculating SSN at pre-design stages, and to cross-check for possible false switching errors. This tool is also intended for a use by packaging engineer to minimize Leff using op timal package-pin placement. The UASSNS architecture is open, to allow adding any future modules (methods) to reduce SSN. Simultaneous switching noise simu lator architecture is explained in Chapter 8. Conclusions and future work on noise modeling are discussed in Chapters 9 and 10. 25 C H A P T E R 2 PERFORMANCE OF SCALED AND PACKAGED CMOS DEVICES/SYSTEMS 2.1 Introduction In order to obtain high speed and high density, MOS devices are scaled down. Scaling schemes such as constant field [CE], constant voltage [CV], and quasi-constant voltage [QCV] have been analyzed [2.1],[2.2]. These schemes are shown in Table 2.1. Note that dimensions refer to all physical dimensions (except junction depths X, and oxide thicknesses toz), doping refers to the channel doping and voltage refers to the voltage applied to the device. All the voltages are with reference to substrate which is grounded. The following mechanisms are usually identified as the controlling performance and reliability factors in scaled circuits [2.3]: 1) velocity saturation, 2) source/drain parasitic resistance, 3) finite thickness of the inversion layer, and 4) Hot electron limitations. In this work, the effect of source/drain resistance, contact resistance and global interconnects (cell to cell on- chip interconnects) on CMOS device performance under constant-voltage scaling is analyzed. In practice, MOS devices do not perform in the simple manner as predicted by first-order scaling theory (see first order scaling theory [2.4],[2.5]) which neglects parasitics associated with the interconnects and package interface. These differences from first order scaling behavior increase as the channel lengths are reduced (scaled system performance is mainly dominated by the interconnects and package parasitics). In Table 2.2, the behavior of first order device performance 2© parameters with scaling, but without the effects of parasitics, are shown. Table 2.1 Scaling rules used for the analysis Scaling Rule JCEl ICY! [QCV] Dimensions l/a 1/a 1/a Gate Oxide 1/a 1/y/Z 1/a Doping a a2 a2 Voltage 1/a 1 1/%/a Table 2.2. First order device performance with scaling Device Parameters [CEl ICYl IQCVl Current a -1 y/Z 1 Current Density a a 3/2 a2 Power Dissipation a~2 Va a - 1/2 Power Dissipation Density 1 a 5/2 a 3/2 Delay [minimum] a -1 a~2 a"3/2 Power-Delay Product a -3 a"3/2 a -2 Frequency Dependent Power a -1 a 5/2 a 3/2 2.2 Interconnect Sealine In Figure 2.1, the typical on-chip interconnect structure is shown. In this work, it is assumed that the operating frequency and the substrate conductivity are such that the Si-SiOa interface behaves as a perfect ground plane [2.6]. 27 LOAD Figure 2.1 Typical on-chip (Si — Sz'02) interconnect structure. 28 All the interconnect geometries are scaled by a. (a > 1). Oxide thickness (tox) is scaled by 1 /y/oi for constant-voltage scaling. The relative dielectric constant 3.5 is used for SiOg. Actual on-chip interconnect structures may have other dielectrics (e.g., polymide) covering metal-2, metal-1 and poly interconnects. In this work, a simple microstrip-like interconnect structure is chosen to demonstrate the trends. Recently, software tools have been developed which are very useful in extracting the parasitics for multi-dielectric, multi-conductor interconnect structures including three dimensional geometries [2.7],[2.8]. As the geometries are scaled down, accurate parasitic extraction tools are required to give meaningful system timing estimations. Detailed analysis of coupled microstrip-like structures with multi-dielectric media are given in [2.9]. Historical and future predicted behavior of scaling for integrated circuits shows that as minimum dimensions are scaled down, the maximum chip size is scaled up. For example, for DRAMs (Dynamic Random Access Memory) each generation increases memory size by x 4, and takes three years. In this time period a=1.43, and chip area increases by A=1.6 [2.9]. When the minimum device size decreases and the die area of the chip increases, the maximum cell to cell interconnect length generally increases. To first order, using statistics from the past chips, a simple empirical relationship is found between the chip area and the maximum interconnect length [2.5]: y/chip area (2.1) Thus as the devices are scaled down by a, the maximum global interconnect length is scaled up independently by A, where A is greater than unity for leading edge chips. Even though there may be a direct relationship between a and A, different technolo gies may have different dependency. In this work, all the interconnect lengths are 29 assumed to be scaled separately from the device scaling. For approximate parasitic calculations, the following equations are used: ~ €r2 W Lmax Cl = (2.2) LOX €r2 t Lmax (2.3) Cc = LS ’ ry P Lmax (2.4) R l = W t ' where Cl is the line capacitance to substrate, Cc is the interline (coupling) ca pacitance and Rl is the line resistance. For exact values of Cx, Cc, and R l, we have used a software tool based on the Method of Moments [2.7] technique. Results from this parasitic extraction tool have been compared with measurements and the results agree very well. The following closed-form equation is used to calculate the diffusion+contact resistance J2C [2.11], \ / R s p c Rc coth L (2.5) W Here Ra is the diffusion sheet resistance, pc is the specific contact resistivity, and W and L are the contact rectangular dimensions. Using the residue expansion theorem for coth(Z), 1 1 1 coth(z) ------z — n7r 1----- n7r , \ / R s Pc 1 fp7 1 R c ~ + oc (2.6) W L y r s Experiments have demonstrated [2.12] that diffusion+contact resistance ex hibits an exponential behavior with o: for small contact windows (< 1 pm) instead of an inverse square behavior with a (> 1 pm). In Table 2.3, the behavior of first order device performance parameters with scaling, including the approximate effects 30 of parasitics, are shown. From [2.11], the parameter a in Table 2.3 is 0.3 for -AT^/Al and P +/A1 contacts, and is used in the diffusion+contact resistance calculation for smaller geometries (Xeff < 1/nn). 2.3 Behavior of Delays with Driver/Interconnect Sealine To demonstrate the variation of performance with scaling, a simple inverter (for two micron Zreff; Wp = 28, Wjv = 15) as shown in Figure 2.2 was used. The inverter is simulated (using SPICE) for one and two micron existing technology parameters with 1 ns inverter rise/fall times. SPICE parameters typical of 1/zm and 2fim Leff devices in the industry were used. Typical one fanout interconnect and load capacitances were selected (Cz,=0.41 fF//mi and Cload—^-Q fF for 2/ma technology). Constant-voltage scaling scheme and the following equations are used to calculate the average (tpih+tPhl)/2 delays for scaled geometries: tpih = (Rsp + Rpchannei + R dp + Rl) (Cl + Cc + Cload) , and (2.7) tphl = (RsN + R n channel + R dN + R l) (Cl + Cc + ClOAd ) • (2.8) The average delays are plotted in Figure 2.3 for the following cases: 1) without interconnect parasitics (device with load only), 2) using approximate interconnect parasitics and 3) using the exact interconnect parasitics. To show the performance dependency with interconnect parasitics, the maximum global interconnect length is fixed (A = 1). As the devices are scaled down, the interconnect parasitics dominate in the delay calculations. Note that in Figure 2.3, the differences are only for a single inverter and these errors accumulate for pin-to-pin timings in a system. 31 //////////////////////////////////// Figure 2.2 A CMOS Inverter with device/ interconnect parasitics. Figure 2.3 Delays with [CV] scaling using exact, approximate, and no inter no and approximate, exact, [CV] using scaling with Delays 2.3 Figure cln atr t 2 tScalingFactor, a LH + HL L«ff 0 0 ft) I 5 .7 0125 0.17 25 0 5 0 I 2 (fttn) ------onc prstc values. parasitics connect 1 --- L — Exact Line Porosities Line Exact — Porosities Line Without — • prxmt ie Porosities Line • Approximate — 32 33 To show the effect of estimating parasitics, the approximate interconnect capacitance normalized by the exact capacitance is plotted in Figure 2.4. Also the diffusion+contact resistance normalized by the channel resistance is plotted in Figure 2.4. It is clear from Figure 2.4 that for large a accurate parasitic extraction tools are essential to predict delays. X Table 2.3. Driver-interconnect performance with scaling (Using approximate calculation of parasitics) Driver-Interconnect Parameters m i is j a fQCVl Line Resistance \ a 2 Aa2 Xa2 Line Capacitance A Ac*- 1 / 2 A Interline Capacitance A A A Time Constant A2 a 2 \ 2a z!2 X2a 2 Line Voltage Drop Xa Aa3/ 2 Xa2 Channel Resistance 1 a~x/2 or1/2 Contact 4 -Diffusion Resistance Leff > 1 a 2 a 2 a 2 Leff < 1 fim eaa eaa eaa To study the chip level performance, a six-cell chain structure was chosen. The reason for selecting a six-cell chain is because the input ramp stabilizes after two to three stages, and using more than six cells is computationally expensive. Four different gates were selected: 1) nominal drive inverter, 2) nominal drive 2 input NAND, 3) nominal drive 2 input NOR, and 4) high drive inverter. In general, these gates form the basis for large cells. 34 Exact (CL + Cc) DIF ♦CONTACT CHANNEL Scaling Factor, a I 2 4 6 8 io 12 14 16 Leff(^m) 2 I 05 0 25 0.17 012 Figure 2.4 Normalized capacitance and resistance with [CV] scaling. 35 Typically, nominal gates drive one or two fanouts while high drive gates drive more than three fanouts. These gates were simulated (using SPICE) for one and two mi cron CMOS technologies using both approximate and exact interconnect parasitics. The average (tpih+tphi)/2 delays are shown in Table 2.4, using global interconnect length scaling A=l. Table 2.4. Six-cell chain delays, A=l. Cell Name 2 /im delays (ns) 1 yum delays (ns) C t (of) Approx. Exact Approx. Exact INV [nominal] 11.2 11.8 7.5 8.9 Cload=0.34: pf NOR 2 -input 15.8 16.5 12.7 14.5 C'load= 0.34 pf NAND 2-input 15.2 16.0 12.6 14.6 Cz,oa£>=0.34 pf INV [high-drive] 10.8 11.9 6.8 9.2 CLOAD= 2Si pf As expected, the error in delay caused by using the approximate intercon nect effects increases as we move from two micron to one micron technology. Note that high drive circuits have significant differences over nominal drive circuits. This is because high drive circuits have large current drive capability with low channel resistance, but the contact4-diffusion resistance becomes relatively more important. Lesser differences were found for NAND and NOR circuits, because these gates are highly resistive. This demonstrates that for highly loaded interconnects driven by high drive circuits (e.g., clock drivers), delays will be dominated very much by the 36 parasitics, compared to the nominal and low drive circuits in scaled devices. Often at VLSI level, average pin-to-pin number of gates are in the order of 102 — 103. If approximate interconnect parasitics were used, timing errors would accumulate resulting in false chip timing for scaled device-interconnects. Note that A > 1 will cause even larger effects in predicted delays 2.4 Summary An investigation into the behavior of delays and noise of CMOS devices with constant-voltage scaling was presented. It appears that interconnects play a major role in the delay calculations for small geometry devices. As a result, accurate modeling of interconnect parasitics is essential for future VLSI chips. Thus detailed modeling of device and also package interconnect parasitics are required to predict the performance of the packaged small geometry CMOS devices/ systems. 37 C H A P T E R 3 METHODS OF CALCULATING SIMULTANEOUS SWITCHING NOISE (SSN) 3.1 Introduction In present high-speed chips, the output driver is a major contributor to the pin-to-pin delays because of output loading as well as package and board parasitics. To get a good speed on these output drivers, often the drive current capabilities are increased by increasing the channel width of the output driver circuits. The increase in current drive capability induces large power/ ground noise due to outputs switching simultaneously. Since the inputs and/or internal logic (if not separated by internal Vd d /V s s buses) are connected to the same Vd d /V s s bus, power/ground noise must be controlled to avoid any false switching. Initial work on estimating Simultaneous Switching Noise (SSN) was done by A. J. Rainal [3.1], G. A. Katopis [3.2], and E. E. Davidson [3.3]. However in the past it was assumed that SSN was directly proportional to the number of out puts switching simultaneously. Recent studies indicate that CMOS circuits exhibit sub-linear behavior (due to negative feedback influence) of power/ ground noise as a function of the number of outputs switching simultaneously [3.4],[3.5]. In this chap ter detailed electrical model of a typical chip-package interface is explained. Several closed-form equations including the negative feedback influence are derived to cal culate SSN as well as the minimum number of bond-pad/package-pin connections needed for a given design [3.6]. Often in the literature SSN is also referenced to “ground bounce”. The 38 reason ground noise is more crucial compared to the power noise is that TTL- compatible input circuits have their switching point around 1.2 to 1.6 volts. Because of this, for a 5-V supply, more switching noise can be tolerated on the power rails. In this work, ground noise and ground pad-pin calculations are explained. Note that power noise and power pad-pin calculations are similar. . A typical multilayer package parasitics with internal/external Vss bus con nection to the package ground pin is shown in Figure 3.1. Note that similar con nections exist from Vdd bus to the package power pin. A lumped package parasitic electrical model of a CMOS output driver is shown in Figure 3 .2 . The following lumped package parasitics values (-Ryss—1 mfl, L v s s —5 nH, C vss= 3 pF) were selected from commonly used 160 to 256 I/O pin ceramic pin-grid-array (PGA) packages for this work [3.7]. Note that C v ss= 3 pF also includes Vss bond-pad area capacitance. In this work, it is assumed that internal switching current is small compared to the output driver switching current. However, as the drivers are scaled down and the number of gates on a chip increases, the internal switching cur rent becomes comparable to the output driver switching current and can no longer be ignored in the noise calculations. A typical CMOS output driver switching char acteristics are shown in Figure 3.3. Input receiver/ output driver circuits , and/or internal logic false switching due to Vd d /Vss on-chip bus fluctuations are shown in Figure 3.4. In the following, the behavior of SSN for sub-micron channel length (Leff < ljum) output drivers are explained using constant voltage scaling scheme and negative feedback effects. 3.2 Theory and Modeline Simultaneous switching for the worst case analysis is modeled. A level 1 SPICE-type device model with Vt n — \Vt p \ is assumed. 39 Internal Output L,,R|,C, Bonding Porosities Logic Driver Cells Cell L2, R2,C2 Package Pin Porosities Lpi Rp, Cp Vss Plane Porosities Internal Vss Bus External Vss Bus Bonding Porosities Vss Package Plane Pin Porosities Figure 3.1 Typical multilayer chip-package interface parasitics. 40 C load Figure 3.2 CMOS output driver with lumped package parasitics. 41 I(mA) Figure 3.3 Typical CMOS output driver switching characteristics. 42 Vnn 1 ON ON/OFF 1 1 1 L _n_n v. V, _ ------0 o----- /V w — ► t Vss Figure 3.4 On-chip Vd d /V ss bus, and noise feed through mechanisms. 43 It is assumed that the maximum worst case switching current is the sat uration current. In practice, the switching current is smaller than the saturation current. If n is the number of similar output drivers switching together, the maxi mum current J, sourced to ground by each driver is li = f [Vin — Vt — Vnf (3.1) where Vn is the ground noise produced by n output drivers switching simultaneously, Vt is the threshold voltage, and K = fin C0x % for the N-channel output driver device. Note that, from (3.1), the current through each bond pad is a non-linear function of ground noise. The maximum total current (J#) sourced to ground by n identical output drivers switching simultaneously is: It = » § [V<„ - >t - Vnf . (3.2) From Figure 3.2, ignoring the effect of resistance in the ground noise calculations (resistance is very small, ~ 0 .112), the ground noise appearing on the chip ground bus, which is connected to the source of the N-channel trnsistor is: Vn (3.3) Here L v ss = ■—- is the total effective lumped inductance from bonding wires, package plane and package pins, where one-to-one correspondence between chip- plane bonds and package pins, with inductance L1 for each equal path has been assumed. Also, let us assume the total current through the ground bond pad has a triangular waveform for noise calculations. This would be the approximate case, for example, if the transient switching current was all due to CMOS driver “through- current”. Then Vn is L1 It Vn » (3.4) P T 5 I 44 where T is the time taken for the switching current spike to travel from zero to its maximum peak value I*. Note that T depends on whether the switching current is controlled by the through-current (overlap current) or discharging current. T can be calculated from SPICE or UANTL [3 .8], or obtained from experiment. Studies have shown that T remains almost constant with n (number of outputs switching simultaneously) for commonly used package parasitics and loads [3.9]. From equa tions (3.2) and (3.4), ground voltage as a function of number of simultaneously switching signals is described by PT Vn2 — 2 Vn Vk + + y*2 = 0 (3.5) Lx n K where Vk = V in - Vt . Often it is assumed that the ground noise is proportional to the number of output drivers switching simultaneously. It is clear from equation (3.5) that the ground noise is not a linear function with respect to the number of simultaneously switching CMOS outputs. This is because negative feedback reduces the switching current when the ground noise increases. From equation (3.5), _£___P_ L1 n K Vn — Vk + 1 - Wl + 2 14 (3.5a) L1 n K p T Note that equation (3.5a) will always have a valid solution as long as the output drivers are not in the cut-off region, and as n approaches infinity V n will approach V k . From equations (3.4),(3.5), a very useful (^) ratio, with and without the effect of negative feedback, for a given output driver design and package parasitics, can be calculated: P = (Vk - V n)2 L1 K = (V k - V n f rpj (3.6) n 2 V n T V k2 Inlw.o.feedback where [El = *LEJL. (3.6a) Tl J w.o. feedback 2 Vn T 45 It is clear from equation (3.6), either decreasing p or increasing n , and vice versa, has similar trend in noise calculations. This is sensible because, increasing n or decreasing p both result in non-linear increase in total switching current. That is, for a fixed number of outputs switching (n fixed) if one increases or decreases the number of Vd d /V s s pad-pin connections, negative feedback influence must be used to calculate the new corresponding switching noise. In practice, more than one type of CMOS output driver may share the same on-chip Vss bus. For example, consider n total number of CMOS output drivers switching simultaneously with several different types (different drive strengths) and switching speeds. Assuming that each output driver is switching symmetrically around the point To (any arbitrary time) with K = Ki and T = Ti, Y''n K l i p 2 ^ = 1 Tj L1 Vn = Vk .+ 1 — i/l + 2 Vi (3.7) L1 E L i i f and P - v y 2 r, (3.8) v (3.10) Here it is presumed that Vn is actually a triangular waveform with full-width of T, and thus risetime of This sort of sinusoid-like waveform is observed experimen tally for Vn, instead of a square pulse. From equations (3 .2 ) and (3.10) for n similar 4© output drivers (including the current through the capacitor) switching noise can be described by Vn2 - Vn 2 Vife + + vV (3.11) n K (y * ¥>: From (3.11), current through capacitor Cyss is negligible only if T2 p T 2 Cvss « (3.12) 2 L1 2 Lvss For example, when X1 = 5 nH, p — 5, T = 1 ns, for 10 percent of the total switching current to go through the capacitor requires C vss # 50 pF. However when the rise times become smaller, the current through the capacitor will increase and one has to take into account this effect in noise calculations. 3.3 Ground Noise and Pad-Pin Connection Calculation Modeling and simulation of simultaneous switching was done using both SPICE simulation and the negative feedback equations given in Section II. Results from the two techniques are very close for a large number of output drivers switching simultaneously. SPICE simulations are computationally expensive. It is important to accurately pre-estimate (before selecting a package for a given chip design) the number of power and ground pad-pin connections needed. This is because improper pre-estimation of power and ground pad-pin connections may force the design to demand a larger I/O pin count (due to the increase Vd d /V s s pad-pin connections requirement from the switching noise) package finally. Note bonding, package plane, and/or pin inductance for each path can be different due to their placements (due to the mutual coupling). A recently developed package plane parasitic extractor (UALGRL [3.10]) can be used to calculate the frequency independent plane para- sitics for different sink/source placements in power and ground planes. 47 The maximum allowable ground noise for a given system design depends on the process and the geometry. Note that maximum tolerable noise (m axim um noise immunity of TTL compatible input receivers) not only depends on the switching noise pulse amplitude but also on its width [3.9]. For worst case, maximum allowable noise of 400 mV amplitude with a very small pulse width was selected in this work. This is because more than 400 mV ground noise may corrupt the output level of receiver TTL circuits. Knowing p (# of pad-pin connections) and Vmax, substituting Vn — Vmax in equation (3.7), one can calculate n (# of si multaneous switching outputs). Since n must be an integer, one needs to round-off the answer to the nearest smaller value integer. Now for this integer n, correspond ing ground noise (Vn) can be calculated using (3.7) again. Similarly, knowing n and Vmax one can calculate how many pad-pin connections (p) are required to con trol the ground noise within the maximum allowable noise. In this case, p has to be round-off to the nearest larger value integer. For this integer p, corresponding ground noise (%*) can be calculated. Note, equation (3.7) is only valid if all the output drivers are switching symmetrically around a single point in time To. Note that for skewed output drivers, one cannot use this simple approach, instead an iteration scheme is required to calculate the switching noise. 3.4 Results In Figure 3.5, ground noise is plotted as a function of the number of simul taneously switching outputs for three different types of CMOS output drivers. The drive capabilities of these drivers are: 1 ) PLIO (3.2 mA D.C. sink with K>j=0.4v), 2 ) PLI03 (8.0 mA D.C. sink with V’o/=0.4v), and, 3) PLI05 (12 .0 mA D.C. sink with VdZ=0.4v). It is clear that the ground noise is a sub-linear function of the number output drivers simultaneously switching. 48 ( I Ground Pod-Pin ) PLI05 12 mA PL 103 8 mA PLIO Z2 mA 5 Z X) i 2 o O • = SPICE Simulations 4 6 8 10 12 Number of Outputs Simultaneous Switchings Figure 3.5 Ground noise vs. # of simultaneous switching output drivers. 49 Table 3.1 shows the percentage error if linear assumption is used instead of the negative feedback equations. Note that, even for smaller drive strength CMOS output drivers (e.g. PLIO : 3.2 mA), four outputs switching simultaneously produces more than 50 percent error in ground noise value if the conventional (linear assumption) method is used. In Figure 3.6, ground noise as a function of the number of ground pad-pin connections (p) is shown for sixteen output drivers simultaneously switching. As expected, when we increase p, ground noise does not decrease linearly. This is because when p increases, the inductance decreases, but the switching current through each pad-pin connection increases, which tends to increase Vn. Table 3.1 Ground noise with and without negative feedback influence. y CMOS Output No. of Simultaneous Switching Percentage Error Caused by Driver Tvoe CMOS Output Drivers Neglecting Negative Feedback PLIO 1 2 .2 99 2 8.3 99 4 52.9 99 8 116.6 PLI03 1 4.6 99 2 29.7 99 4 82.9 99 8 181.1 PLI05 1 9.8 99 2 30.2 99 4 92.5 99 8 2 2 0 .0 50 (16 PLIO 5 Output Pads Simultaneous Switching) • = SPICE Simulations p 3.0 PLI05 PLIO Number of Ground Pads-Pins Figure 3.6 Ground noise vs. # of ground pad-pin connections. 51 3.5 Behavior of Simultaneous Switching Noise with Scaling To show the trends in simultaneous switching noise for scaled CMOS out puts, constant-voltage [CV] scaling scheme was used to calculate the switching cur rent. For this, a is the scaling factor (<% > 1). Dimensions (except junction depth and oxide thickness) are scaled down by Gate oxide thickness is scaled down by Doping refers to channel doping and is scaled up by a 2. Voltage refers to the applied voltage to the device and remains constant. Note that all voltages are with reference to substrate which is grounded. Under the above [CV] scaling scheme, the drive current capability of CMOS output driver increases by ^/a [3.11]. In Figure 3.7, the ground noise is plotted as a function of channel length for constant-voltage scaling. For demonstration a standard output driver (for 1 micron Leffi Wp ~ 250, Wjv = 160) is selected. This output driver was designed to switch a 100 pf load in 6 ns. The total (bonding+plane+pin) parasitics are, L=5.5 nH, R= 2 Cl, and C= 1 2 pF. For noise calculations (Teff < 1 /zm), the constant-voltage scaling scheme and negative feedback noise equations are used. For the above one micron output driver, eight and sixteen output drivers simultaneously switching through four and eight ground pad-pin connections are simulated using SPICE with 1 ns rise/fall times. This corresponds to a FF-00 and FFFF-0000 switching case in a typical eight and sixteen bit data/address bus. As expected, the noise increases when the output driver devices are scaled down. It is clear from Figure 3.7 that the noise increases rapidly when Z-eff < 0.5 yum. This is because in going from one micron to smaller geometries, the scaling factor increases rapidly, thereby causing the switching current to increase rapidly. 52 M = # of Simultaneous Switching Drivers N = # o f Ground Pads and Pins > 15 0.875 0625 0375 0 125 Leff (^m) Figure 3.7 Simultaneous switching noise as a function of [CV] scaling. 53 3.6 Summary An investigation into the calculation of simultaneous switching noise for packaged CMOS devices was presented. It was found that due to negative feed- backsimultaneous switching noise exhibits a sub-linear behavior with the number of outputs switching simultaneously. As a result, when calculating the switching noise, negative feedback influence must be incorporated in the equations. This effect must also be account for in the power and ground pad-pin connections calculations. The trends in output driver switching noise with constant-voltage [CV] device scaling were explained. 54 C H A P T E R 4 THE MODELING OF POWER/GROUND PLANE PARASITICS AND THEIR CONTRIBUTION TO THE “EFFECTIVE” INDUCTANCE OF VDD/V Ss CHIP-PACKAGE INTERFACE 4.1 Introduction Complex high density VLSI chips (i.e. microprocessors, microcontrollers, and digital signal processors) require packages with Vdd/Vss plane(s) and a large number (> 100) of I/O pins for controlled signal impedance and external communi cations. However, in typical single layer packages, conductors are metal leadframe connected to the die (chip) with bond wires. Note that single metal layer pack age does not contain a separate Vdd/Vss reference planes, and the current path is confined to the metal lines and bond wires. Typical single layer packages are; 1) PDIP/CDIP (Plastic/Ceramic Dual-In-Line Package), PLCC (Plastic Leadless Chip Carrieer, 3) PQFP (Plastic Quad Flat Pack), and 4) CerQUAD (Ceramic Quad Flat Pack). In multi-layer packages, connections from the die to the external world may be through signal traces, bond wires, metal planes, vias, and pins. Vias are used to connect signals from plane-to-plane. Due to these complex Vdd/Vss connections at the chip-package interface, modeling “Leff” (to a single lumped inductance) involves a detailed understanding of the current path through these connections. A software tool describing the current distribution on the Vdd/Vss planes is essential to model the reference plane inductance, and thereby the effective inductance “Leffn. 55 In this Chapter, a method of modeling Vd d /V s s plane inductance is pre sented. In this work, it is assumed that there is only one Vss plane, and package pins connect this plane to the ideal ground. Source points (current entering points to the planes) are lumped into a single source point at the center of a plane, and sink points (current leaving the plane) are the package-pins which are distributed over the plane. In reality, bonding wires (or TAB) inject current into the Vss plane. Note that the above mentioned single source point assumption is valid only if the chip die area is much smaller than the Vd d /V s s plane area. A typical “direct connection” package Vss connection without vias is shown in Figure 4.1. A UA software tool called UALGRL [4.1] was used to calculate the plane inductance under the assumption that magnetic diffusion effects on the plane are negligible. This tool can be used to calculate both the resistance and the induc tance with or without perforations in the Vss on-chip buses are used, they may be connected to the same Vss plane connections, and decoupling is not assured. In such cases, package plane parasitics play a major role in coupling output driver switching noise to the internal gates and also to the input circuits [4.3]. In the past mutual elements of the package plane inductance network were neglected, and it was assumed that plane inductance decreased inversely with the increase in num ber of package-pins (sink points). Results have demonstrated that due to mutual inductance in the plane Vd d /V s s plane inductance saturates for large number of package-pin connections [4.2],[4.4]. 56 (Direct Plane Connections without Vias) Vcc Plane 7__Lower Bonding Shelf Bonding Wire t=0.05cm Copper Plane 3cm x 3cm Figure 4.1 Typical “direct-connection” package Vss connections. 57 4.2 Mathematical Formulation of UALGRL [4.11 In UALGRL the mathematical constraint is that the current injected into the plane is equal to the total current removed through all, the package-pins, 9 p Ii(source) = Ij(sink) (4.1) 8=1 j=l where q is the total number of source (bond-pad) points, and p is the total number of sink (package-pin) points. Additional assumptions: a) if frequency (f) is such that skip depth > thickness of the plane, field variation with thickness is neglected. Thus, fields are function of x,y where x,y are the coordinates on the plane surface. In addition, fields are assumed to have zero z components. b) if frequency (f) is such that skin depth < thickness of the plane, it is assumed that current flow is restricted within a skin depth and the assumption of (a) still hold. Inside the plane, the electric field is given by E = —V — jjwA , (4.2) where J = —(rW J = — Neglecting charge accumulation at the boundaries of the plane and using the fact that J satisfies the continuity equation V • J = 0 , (4.5) we conclude that the potential V 2 (j) — 0 . (4.6) A finite element solution for the potential 1 ) At plane boundaries (4.7) 2 ) At source and sink points . I = t j> 3 • n dl . (4.8) Here t is the thickness of the plane. Knowing the current density from equation (4.4) and using the free-space Green’s function G(r \ r'), where G(r 1 r,) = 4 r l / - r-| ' (49) the magnetic vector potential A is A = fi f J(r') G(r | r')dv' . (4.10) J V Resistance and inductance of a plane are calculated from, R | Itot I2 = - f r-Jd v, (4.11) & J V 59 r-Adv . (4.12) A perforated reference plane structure with multiple sink/source points is shown in Figure 4.2a [4.5]. In Figure 4.2b [4.2], the contour “c” used in equation (4.7) is shown. 4.3 Effective Inductance “Lvg<;” Modeling Using UALGRL one can calculate the reference plane inductance and re sistance for an arbitrary number of sink/source points. Some restrictions apply on the placement of perforations near the plane boundary, and on the discretization distance [4.6]. In reality for a given chip-package interface there could be q number of bond-pad connections and p number of package-pin connections. In this work, a single (no double or triple) bonding connection is assumed. Note that, as mentioned earlier, it is assumed that all bonding connections are to an area small enough to be approximated as a point. Single chip-package interface model and it equivalent inductance network is shown in Figures 4.3a and 4 .3b, respectively. For p ^ q, LySS — Lbondisi) "b Lpiane(p) + Lpin(p) . (4.13) Here Lbond(q) is the effective inductance of q number of bond-pad connections, LpUneip) is the effective inductance of Vss plane with p number of package Vss pins, and Lpin(p) is the effective inductance of p number of package-pins. It is assumed that the Vss bond-pads and the package pins are separated by either Vdd or signal bond-pads and package pins respectively. With this assumption, mutual inductance between Vss bonding connections, and between package pins are negligible. Equation (4.13) can thus be written as L vss » ^ (4.14) 60 (a) y \ • source (or sink) (b) \ ------/ Figure 4.2 a) Perforated Vss plane with multiple sink/source points [4.5]. b) Contour “c” used in equation (4.7). 61 VSs Bus Bonding Wires Source Point Plane (b) (I), (2), (3): Sink Points Figure 4.3 a) Single chip-package interface model, b) Equivalent inductance network. 62 Lfrond and L'pin are the partial self-inductance for a single connection bond-pad and package-pin, respectively. Closed-form equations have been derived to approx imately calculate the bond-pad [4.7] and package-pin [4.8] inductance. However, when the pitch of Vss bond-pads and/or package pins is reduced significantly, the mutual inductive coupling between neighboring connections will increase, and must be included in L yss calculations. Note that neighboring Vdd bond-pad or package- pin connections always reduce the Vss path effective inductance, whereas neighbor ing signal bond-pad or package-pin connections can either reduce or increase the effective inductance. This is because current paths in Vdd and Vss connections are always in opposite directions, and current paths in signal and Vss connection can be either in the same or the opposite direction for bi-directional 1 / 0 drivers. The objective of this work is to model and calculate the effective inductance L yss for a given chip/package design. Knowing the maximum allowable switching noise, the minimum number of Vss connections required to assure zero (or low) probability false switching can be calculated. With the assumption that there is one-to-one mapping between bond-pad and package-pin connections (i.e. p=q), L vss » + £PI.».(P) + ^ • (4.15) For single metal-layer packages (no Vss reference planes) with the above assump tions equation (4.14) reduces to L vss = ^ , (4.16) P P where L'pin corresponds to the leadframe plus the pin inductance for a single Vss pin connection. Note that, mutual inductance between lead frame elements are neglected in equation (4.15). However, leadframe elements can be long and mutual inductance must be included. 63 Again, in deriving equation (4.14) it is assumed that the chip die area is much smaller than the Vss plane area, and the source points are lumped into a single equivalent source point at the center of Vss plane. It is also assumed that all sink points are at an equipotential, and all source points are at a different equipotential. From Section 4.2 (equations (4.8) and (4 .1 2 )), it is clear that Lpiane(p) not only depends on the number of package pins p, but also on the placement of these pins. Because of this, different Vss package-pin placements have different Lpiane values. Even with the same number of Vss package-pins and for a fixed package- pins placement, Lpiane values can vary significantly if any one of the current paths between source and sink points are perturbed due to the perforations. This effect is explained qualitatively in Figures 4.4a and 4.4b using three sink points on the Vss plane with and without perforations respectively. Note that perforations in the Vss plane always increase the effective plane inductance, so that in Figures 4.4a and 4.4b L'P(Z) > Lp(3). To demonstrate this effect, a copper plane (cr = 5.8 x 107 S/m, fi = 12.56 x 1 0 - 7 H/ to) was selected and the inductance was calculated with and without perforations. A 2 cm x 2 cm ground plane with 0.05 cm thickness was selected for this analysis. Sixteen sink points were selected and placed around the source point (located at the center) as shown in Figure 4.5. For the perforated ground plane model, two arbitrary rectangular cuts (metal removed from the copper planes) were selected as shown in Figure 4.5 with dotted lines. The calculated plane inductance values are given in Table 4.1. Impact of individual package-pin placement on the effective L yss is explained in the following section using superposition theory and the equivalent inductance network. 64 (a) ® Source o Sink (b) Figure 4.4 a) Current distribution on a V5 5 plane without perfora tions. b) Current distribution on a Vss plane with perforations. Figure 4.5 Perforated copper V copper Perforated 4.5 Figure 2 cm LVj Hole Source ® Sink o 55 plane with two arbitrary rectangular cuts. rectangular arbitrary two with plane Copper Plone: thicknesscm =0.05 ct -^S.SXIO 256X07H/m = XI0'7 12.566 7S/m 65 Table 4.1. Effect of perforations on L p iane and Rpiane values. Ground Plane Model Inductance fnHl Resistance (fiQ,) Ground Plane without perforations 2.615 12.63 Ground Plane with perforations 6.132 23.12 4.4 Reference Plane Inductance Network Calculation Consider a Vss plane with a single perforation and three Vss pins as shown in Figure 4.6a. A copper plane with the area 2 cm x 2 cm, and thickness of 0.05 cm was selected for this analysis. The inductance network model corresponding to the Figure 4.6a package Vss plane is shown in Figure 4.6b. To calculate the equivalent inductance network, the following superposition technique was developed. Plane inductance values are calculated using UALGRL by connecting all possible com bination of VI, V2 , and V3 (taken one at a time, two at a time, or all three) to ground and performing the inductance calculations. Sink point combinations for three package pins, and the corresponding inductance values (not necessarily the network element values) are shown in Table 4.2. The inductance values correspond ing to sink points VI, V2 , and V3 individually at ground potential are the element values T n, T22, and T 3 3 respectively. The superscript in Table 4.1 corresponds to the sink points grounded to calculate the inductance values (marked with subscript) which will later be used to calculate the inductance network element values. Note that Lu = L* , (4.17) and by equating the stored energy of a physical system using two representations, 9 (4.18) 67 Source (a) (b) Figure 4.6 a) A Vss plane with three VSs pins, b) Equivalent inductance network of Figure 4.7 VSs plane. 68 Table 4.2. [Jjj] inductance calculations. Sink Points Inductance Notation Inductance fnH) VI L 1 7.681 V2 L 2 8.398 V3 L 3 8.376 VI, V2 L(i,2) 5.391 VI,V3 5.394 V2,V3 j ( 2-3) 6.074 V1,V2,V3 X(1.2,3) 4.743 where I is the total current into the plane, and J j, and Ij are the partial cur rents through ith and j th sink points, respectively. Partial current through each sink points (J j and Ij) are extracted from U A L G R L simulations, and the following inductance network matrix [Lij\ is calculated from Table 4.2 and , / 7.681 2.764 2.770 \ [Lij] = 2.764 8.398 3.762 . (4.19) \ 2.770 3.762 8.376 / It can be shown by using mathematical induction theorem that in order to calculate the inductance matrix elements [Lij] for p number of package-pin connections, one needs to run U A L G R L for p(p+ l)/2 different ground connections. Note that proper utilization of any existing symmetry in the package-pin connections reduces the computational labor significantly. For example, utilizing the symmetry between sink points (2) and (3) in this example would reduce six U A L G R L computations to four computations (i.e. L22 = L33, Z-12 = L13). The plane inductance value with all sink point (VI, V2, and V3) grounded corresponds to Z^1,2,3\ and this value 69 is used for consistency check to verify the calculated inductance network matrix elements. 4.5 Results A typical 168 pin Pin-Grid-array (PGA) package Vss copper plane with area of 3 cm x 3 cm and a thickness of 0.05 cm was selected for this analysis. Eight Vss package-pins were placed around the source point (again source points are lumped into a single source and placed at the center of the plane) as shown in Figure 4.7. Each sink point location is numbered and the sink points are referenced by these numbers in later discussions. The inductance network is calculated using the methodology described in Section 4.4, and the corresponding inductance network /14.07 7.10 5.74 4.85 4.71 4.85 5.74 7.10 \ 12.28 7.10 5.47 4.85 4.55 4.85 5.47 14.07 7.10 5.74 4.85 4.71 4.85 12.28 7.10 5.47 4.85 4.55 14.07 7.10 5.74 4.85 12.28 7.10 5.47 14.07 7.10 12.28/ (4.20) Since Lij = Lji, only part of the matrix in equation (4.20) is filled. To study the effects of perforations on the Vss plane inductance, the inductance network is calculated for the perforated Vss plane structure shown in Figure 4.8. Note that these two planes (Figures 4.7 and 4.8) are identical except the perforations. Inductance network element values for the perforated Vss plane structure are given in equation (4.21), 70 3 cm (7) (6) (5) O O O (0.5,25) (1.5,2.5) (2.5,2 5) (8) (4) 3 cm O e O (0.5,1.5) (15,15) (2.5,1 5) (1) (2) (3) O O O (0.5,05) (1.5,05) (25,0.5) O sink • source 0.05 cm copper plane Figure 4.7 A non-perforated V55 plane with eight sink points. 71 3 cm 2.25,2.75) (7) o (0.5,25) (1.75,2.25) ( 8 ) (1.5,1.5) (4) 3 cm O # O (0.5,1.5) (2.5,1.5) (175,125) g§g -re (1.25,0.75) ( 1 ) ( 2) (3) O O O (0.5,05) ( l .5,0.5) (2.5,0 5) O sink • source 0.05 cm copper plone Figure 4.8 A perforated V55 plane with eight sink points. 72 /15.01 8.59 6.18 4.93 4.94 5.04 6.01 7.53 \ 14.62 8.54 6.17 5.72 5.00 5.28 6 .1 2 14.95 7.50 6.44 4.90 4.54 4.83 12.58 7.81 5.05 4.41 4.28 15.93 6.29 5.31 4.65 12.61 7.34 5.62 14.00 7.15 12.41/ (4.21) By comparing both the inductance network matrices (equations (4.20) and (4.21)), it is clear that perforations perturb the current distribution on the ground plane, and thereby the self and mutual inductance values are larger in [Lij]' compared to [L{j\. For example, the perforation placed between source point and the sink point number (2 ) not only increases the self inductance L22 but also increases the mutual inductance £ 12, -&23, and Z13. Perforations placed between two neighboring sink points increase the mutual inductance between these points. This effect is clear by comparing L'^ with in equations (4.20) and (4.21). In Figure 4.9, the plane inductance of these two ground planes are com pared. Note that the number of sink points on the x-axis of the Figure corresponds to 1,2,3,...,N sink points with their exact placement as shown in Figures 4.7 and 4.8. As expected, the plane inductance of the perforated Vss plane is larger than the non-perforated Vss plane. Notice due to the perforation placed between source point and the sink point number (2 ), the difference between L'piane(p) and Lpiane(p) is the largest when the number of sink points equal to 2. These difference decreases as the number of sink points increase from 4 to 8 . This is because, as we increase the number of sink points, due to the other sink points contribution, L'piane approaches Lpiane’ To study the effect of package plane inductance on the simultaneous switch ing noise, L'bond=2-5 nH, and L'pin=2.5 nH were used. 73 With Perforotions Without Perforations Number of Sink Points Figure 4.9 Comparison of perforated and non-perforated Vss plane induc tance vs. # of sink points. 74 Simultaneous switching noise for two cases, sixteen 3 mA (D.C. sink with Vo/= 0 .4 v) CMOS outputs, and thirty-two 12 mA (D.C. sink with K>j=0.4v) CMOS outputs was studied. For 3 mA and 12 mA CMOS outputs, T = 1.0 ns (defined in Section 3 .2 ) was used in this analysis. The effective inductance L v s s was calculated using equation (4.14) with p=q for one to eight Vss package-pins. Plane inductance Lpianei?) was calculated using UALGRL. Simultaneous switching noise (including the negative feedback effects) is calculated using equation (4.22), Vk + i - 1 + 2 Vk L v ss (4.22) L vss 53L i t 8=1 The results are shown for: 1) a model with negative feedback effects including plane mutual inductance effects, 2 ) a model with negative feedback effects without plane mutual inductance, and 3) a model without negative feedback effects and with plane mutual inductance. Note that L v ss is given by the equation (4.15). Simultaneous switching noise for sixteen 3 mA output drivers, and thirty- two 12 mA output drivers is shown in Figures 4.10 and 4.11 respectively. As ex plained in Chapter 3, to have meaningful ground noise calculations, not only an accurate L vss model is essential but also detailed (including negative feedback effects) circuit models are essential. In Figure 4.10 and 4.13, the plane mutual in ductance, and also the negative feedback effect, saturates the ground noise for large numbers of Vss connections and/or for large numbers of drivers switching simul taneously. Note that when both the plane mutual inductance, and the negative feedback effects are considered, the ground noise saturates for a lower number of Vss bond-pad/ package-pin connections due to the additive effects. 75 (16 Outputs Simultaneous Switching) (I) Negative Feedback with Plane Mutual Inductance (2) Negative Feedback without Plane Mutual Inductance (3) Plane Mutual Inductance without Negative Feedback Number of \4s Pins Figure 4.10 3 mA drivers, 16 outputs simultaneous switching noise. 76 i i 3.0 - (32 Outputs Simultaneous Switching) 2.5 _ 2 0 > tn0) O Z 1.5 "O c3 O O 10 (1) Negative Feedback with Plane Mutual Inductance T = 1.0 ns (2) Negative Feedback without Plane Mutual Inductance U Ld=2.5nH 0.5 (3) Plane Mutual Inductance without Negative Feedback L ^= 2 .5 n H 1 i I______I I I >► 00o 2 3 4 5 6 7 8 Number of Vss Pins Figure 4.11 12 mA drivers, 32 outputs simultemeous switching noise. 77 The errors in calculating ground noise values without the plane mutual inductance or without the negative feedback effects increase as the number of simultaneously switching outputs increase, and/or with increase in the drive strength of these output drivers. This effect is clear by comparing the curves (1), (2), and (3) of Figures 4.10 and 4.11. 4.6 Summary A method of calculating the effective Vd d /Vss chip-package interface in ductance “Leff” was presented. It was found that package-pin placement has a strong influence in the plane inductance (especially for a small number of pack age Vss pins). Perforations on the Vss plane perturb the current distribution in the ground plane, and these perturbations increases the plane inductance. Un published results have also shown that having symmetrical connections in the sink points greatly reduces the package plane inductance. The effect of Lplane on simul taneous switching noise was explained, and errors associated with neglecting plane mutual inductance were discussed. 78 C H A P T E R 5 CHARACTERISTICS OF SIGNAL PROPAGATION OVER PERFORATED REFERENCE PLANES 5.1 Introduction Due to increases in system speed and density, designers are confronted with several practical problems imposed by interconnect structures. In short, miniatur ization can force different types of transmission-line discontinuities. Deviations from an ideal transmission line can be thought of as belonging to one of two cat egories: (1) the signal conductor departs from the reference plane (e.g. package leads, sockets, and connectors); and (2 ) the reference plane is not continuous (e.g. mesh planes, isolated ground regions, and multiple supply regions)[5.1]. The first category of discontinuities has been well-characterized, and it has been shown that lumped-element models can be used to represent these structures [5.2],[5.3], [5.4]. In this work, a detailed analysis of the effects on signal propagation of reference plane openings is attempted. The intent is to establish which modeling tools and methods can be used to extract equivalent circuits that accurately predict time-domain wave forms in cards, boards, and modules containing reference plane openings. Results to within engineering accuracy are required, with minimum model complexity and analysis time. In Figure 5.1, the cross-section of a srtipline interconnect structure with an opening in the top reference plane is shown. Two electrical test structures have been designed specifically for this work. 79 ------► Direction of Propagation //////////////////// j /////// ///////////////////////// J U l T777777T777T7777T77777777T77777T77777777T7777777777T777" H------1,------H h ------Z2 ------H d Zi ^2 [ 3 I I Figure 5.1 Equivalent circuit model of a perforated reference plane stripline interconnect structure. 80 These have been constructed with the recognition that TDR measurements of small discontinuities are often difficult. Typically, other discontinuities which are difficult to eliminate from the experimental set-up (such as connectors), can mask the dis continuity reflections one tries to measure. For this reason, a scaled-up model con taining a single reference-plane opening was constructed for initial measurements. The second test structure is an actual FR-4 card containing many small openings in the reference planes. After discerning the general features of the discontinuity from the scaled model, one can more easily isolate and understand the discontinu ity effects in realistic structures. Photographs of the scaled model and the FR-4 card measured in this work are shown in Figures 5.2 and 5.4. Cross-sections and dimensions for both models are given in Figure 5.3 and Figure 5.5. The basic modeling approach followed in this work is to construct lumped- element equivalent circuits which represent the transmission-line over the small re gion containing an opening in the reference plane. By “represent”, we mean that the time-domain waveforms predicted from circuit-simulation match the measurements obtained to within 5-10 %. The circuit simulations are performed using ASTAP [5.5]. The lumped-element models for the reference openings are extracted using four distinct techniques: (1) S-parameter measurements, (2 ) two-dimensional and (3) three-dimensional inductance and capacitance extraction programs, and (4) a full-wave electromagnetic parameter-extraction program. In order to fully charac terize their impact on propagating signals, reference plane openings of different size and shape are studied. Another objective of this study is to determine the limits of applicability of the four techniques mentioned above. Finally, guidelines are pre sented for package designers which indicate when routing signal lines over reference plane openings will have a significant noise impact and when they can be ignored. 81 Figure 5.2 Scaled-up, perforated reference plane stripline model. 3 0 .5 < >■ Signal Trace Length = 61 cm Distance from Gap = 20.1 cm Connectors at Ends = 4 cm Figure 5.3 Scaled-up model crossection. 83 Figure 5.4 Periodically perforated card structure. Perforation Z„= 5 0 .7 4 0 ////////////////// / ////////////////// 1...... 1^1.4 i 1 ------H = 6 2 h=2l 2 0 1 r 1r //////////////////////////////////////////////// (Cross-section) (Dimensionsin Mils) (Top View) Figure 5.5 Card structure interconnect crossection. 85 5.2 Impact of Reference Plane Openings for Strivline Geometries The opening in the top reference plane introduces an inductive discontinuity in the stripline since return current is forced to flow around it. The signal reflection produced by an opening in one reference plane of a stripline structure depends on the distance between the signal conductor and the discontinuous reference plane, since a larger return current will be present in the reference plane closest to the signal line. For a buried microstrip line (no top reference plane), it has been shown there exists a critical conductor height above the single reference plane (hc), below which the effect on transmission-line parameters L, C, and Zq of adding a top reference plane are negligible [5,6]. Detailed analyses of buried microstrip electrical characteristics were also shown in [5.7]. As the conductor height increases above hc, however, a larger fraction of the E-field lines are not collected on the bottom plane, and the effect of adding a top reference plane become significant. Furthermore, if an opening is present in the top plane, some of these fields will escape into air (outside the stripline structure). In this case, the stripline will suffer a significant impedance discontinuity in the re gion of the reference plane opening. In Figure 5.6, the calculated impedances for a stripline and a buried microstrip are compared as a function of normalized conductor height. These impedances were calculated using a two dimensional, TEM approxi mation transmission-line parameter extraction tool [5.9]. The dielectric is assumed to be Plexiglass, which has a relative dielectric constant of 2.6 over commonly-used frequency ranges [5.8]. From the figure, it is clear that AZ, which we define as the difference between the buried microstrip and stripline impedances, AZ = Z(bmsl) — Z(sl) , (5.1) 86 ///////// Buried Microstrip \\ \ \ \ \ \ \ Buried Microstrip - 40 Stripline Normalized Ratio. Stripline, buried microstripline impedance vs. conductor height. 87 increases rapidly as the conductor height increases. Here Z(bmsl) is the buried microstrip line impedance and Z(sl) denotes the stripline impedance. In Figure 5.7, AZ is plotted for two different normalized linewidths to indicate the sensitivity expected. Note that the reflection coefficient (pa) is directly proportional to (AZ): AZ (5.2) Pd ^ Z(bmsl) + Z{sl) ' This expression is only rigorous for the case where the upper reference plane is com pletely split, since the region containing a finite-size opening is only approximated by a microstrip line. This figure can be used for estimating an upper bound on reflection coefficients associated with narrow reference plane openings. In common packaging structures, X-Y wiring pairs are used in a stripline configuration; most nets will be affected by openings even if they occur in only one plane. From an estimate of the reflection coefficient associated with a reference plane opening, the noise pulse amplitude for digital signals can be estimated based on the risetime. Specifically, it can be shown that an inductive discontinuity will produce a reflection with magnitude greater than roughly one-tenth of the incident voltage when (5.3) where Tr is the incident signal risetime, Ld is the discontinuity inductance, and Zq is the nominal characteristic line impedance. Provided the effect is deemed to be significant, the techniques described in the next sections can be used to build accurate ASTAP or SPICE models of the stripline interconnects. 5.3 Connector Characterization Using S-Parameter Measurement Techniques Frequency-domain, two-port measurements are used in this work primarily to characterize the connectors used to bring signals to the scaled model and the test card. 88 /> = ♦0 375 (50& stripline) / -=- = 0 2 9 , ^ = 0 . 0 8 4 Stripline Buried Stripline Microstrip /» = ^0 286 (5 0 A stripline) O 15 ^= + 0 167 (50 H stripline) Normalized Ratio, %: Figure 5.7 Reflection coefficient (p), AZ vs. conductor height. 89 Since we are not interested in studying the connectors explicitly, the S-parameter technique provides a quick way for extracting their lumped-element equivalent cir cuits. However, an attempt was made to characterize the striplines containing the reference discontinuities as well, in order to check the feasibility of using the ap proach to measure such small discontinuity effects. The connectors used in the scaled model and test card introduce parasitic capacitance and inductance, which have to be calculated and incorporated into an ASTAP or SPICE model to simulate the correct time-domain signals. Measure ments of the two-port S-parameters for a calibration line containing only connector discontinuities can be matched to simulations performed in the frequency-domain for a lumped-element model of the connector having variable element values. This is essentially performed automatically using the Touchstone(TM) software [5 .10], together with a network analyzer (HP 8753A) and an S-parameter Test set (HP 85046A). Both the magnitude and angle are measured for all four S-parameters, after a proper two-port calibration is conducted to eliminate the influence of the cable. The S-parameters are measured across the frequency range from 10 Mhz to 1.1 Ghz. The frequency-domain, two-port circuit model for the calibration line and connectors is shown in Figure 5.8. This model is fed to Touchstone, which then op timizes the lumped-parameter values to achieve convergence with the S-parameters measured from the actual structure. A buried microstrip line (without a top ref erence plane) is used in addition to the stripline to check for consistency between calculated connector values. Good agreement for the connector lumped-element values is obtained for the two different structures. The optimization procedure is allowed to run until the error e converges to its minimum value. Connector Perforation Connector Two-port Model Sij(w) _ i Figure 5.8 Two-port network equivalent transmission line model. 91 Touchstone uses both random and Quasi-Newton optimization methods to minimize e, defined as 6 = E E [$u” ("-t) - . (5.4) k = l i,j= l Here Sijm(u>k) are the measured and Sijc(u>k) are the calculated two-port S- parameters. Optimization is performed over eleven different frequencies, from 10 Mhz to 1.1 Ghz in 100 Mhz steps. Several different lumped-element topologies (e.g. Tee and Pi) were tried to best-fit the connector model. With the connectors well-characterized, the S-parameter technique was used to extract equivalent circuit models for the reference plane discontinuities in the scaled model. Results from the Touchstone optimizations, along with the errors associated with each calculation, are shown in Table 5.1. Table 5.1 Touchstone-calculated lumped-element values and optimization error. Discontinuity LfnH) / CfnF) Error (e) connector 12.7/5.2, R=4.4 Q 0.11 perforation 5x1 cm 1.52/0.95 0.21 perforation 5x4 cm 7.20/1.82 0.40 perforation 5x8 cm 9.52/2.54 0.52 perforation 10x1 cm 1.37/0.89 0.31 perforation 10x4 cm 12.56/1.73 0.48 perforation 10x8 cm 13.25/3.42 0.67 perforation 20.4x20.4 cm 27.42/6.86 1.21 Note that for larger perforation sizes the error increases. This is because for large 92 perforation areas (more than 15 % of the total top reference plane area), simple lumped-element models for the discontinuity become inadequate. Another comment on this technique is that it is observed upon minimizing the error e, that different sets of lumped element values (not one unique solution) can give comparable error values. One way to select the best set is to use each in ASTAP simulations and compare with TDR measurements. The TDR measurement setup used in this study was shown in Figure 5.9. Results which can be identified by visual inspection as unphysical are discarded. In general, it is found that the S-parameter matching technique is useful for calculating the connector parasitics, which are large, but for the smaller effects produced by discontinuities such as ground plane openings, the methods described later in this work are more effective. This is due to the fact that it is difficult to resolve the added reflection due to the discontinuities of interest in the frequency-domain when other, larger sources of reflections (namely, the connectors) are present. Also, this technique is dependent on measurement data and is therefore not appropriate for pre-hardware analysis and has no predictive capability. 5.4 Modeline Using a Two Dimensional (TEM) Approximation In Figure 5.10, a stripline with and without a perforated reference plane is shown. The general technique for constructing an L-C circuit to represent the transmission-line in the region of a reference-plane perforation is now described. First, the Per-Unit-Length (PUL) parameters for the calibration stripline (without perforations in the reference planes) are calculated using parameter extraction pro grams. If the width of the perforation (Wp) is very large compared to the width of the signal line conductor (Wc), that is Wp » Wc , then two-dimensional extraction programs may be used. 93 Cable Stripline Stripline Connector Perforationt Connector R L L o- T c T Figure 5.9 TDR measurement setup and connections. 94 Note that in practice, perforations are often small (compared to the total plane area) in size, and may be repetitive. For example, let the top plane perforation window width be Wp (arbitrary units). If Wp is not greater than several signal linewidths, three-dimensional extraction programs should be used. Once the PUL inductance (Z-s) and capacitance (Cs) are calculated for the calibration stripline, the appropriate 2-D or 3-D tools are used to re-calculate the PUL parameters for the actual structure. The difference in PUL transmission-line parameters is due to the presence of the perforation in the reference plane. The 2-D capacitance and inductance extraction programs are simplest to use. For the perforated-plane case shown in Figure 5.10(b), the PUL inductance (Lp) and capacitance (Cp) have been calculated using a 2-D program internal to IBM. The top reference plane is modeled as two distinct grounded conductors sep arated by a distance equal to the perforation window width (Wp). Knowing the PUL inductance and capacitance values for the two structures, the differences due to the discontinuity, AL and AC, can be computed: AL = (Lp — Ls) lp , (5.5a) AC = (Cp - C9) lP . (5.56) Note, that AC will be negative for this type of discontinuity. These values are compared in Table 5.2 with the values obtained using the S-parameter matching technique described earlier. A separate check on these calculations is provided by capacitance measurements, which were carried out using a capacitance meter (@ 1 Mhz). The total capacitance (between signal and ground) was measured for different perforation sizes in the scaled model. These values are compared with the 2-D calculated values in Figure 5.11. As expected, due to the edge and connector effects, the 2-D calculated values underestimate the total capacitance. 95 XWWWWNWWVWNWNWWSVNX w 77777777777777777777777777777 Stripline Per-unit-length Porometers l_5= nH/cm Cs= pF/cm ////////////////// UJIUILLLLLLLLL 77777777777777777777777777777 Perforated Stripline Per-unit-length Parameters Lp= nH/cm Cp= pF/cm Figure 5.10 Two-dimensional (PUL) capacitance/inductance modeling. Figure 5.11 Total, scale model measured and calculated capacitance values. capacitance calculated and measured model scale Total, 5.11 Figure Capacitance (pF) 0 5 0 4 2) (cm Area Open Cut 0 3 Calculated Measured A Cut Width = 5 cm 5 = Cut Width A • Cut Width = 10cm Width Cut • 96 8>T However, when the perforation discontinuity inductance (A £) and capacitance (AC) are calculated using the 2-D approach, the edge and connector effects are cancelled out in the subtraction. In the next section, 3-D calculations are per formed to further refine this approach. 5.5 Three-Dimensional Modelins Technique Three-dimensional parameter extraction programs [5.11] are used to calcu late the inductance values for different size perforations. As shown in Figure 5.12, total inductance is calculated with and without the perforation in the top reference plane. Because computed inductance values strongly depend on the current path, it is necessary to use a finer modeling grid in the vicinity of the opening for both planes. The calculated inductance values are tested for convergence by reducing the grid size. The partial-element inductance bars used in the 3-D scaled model calculation are shown in Figure 5.13. In the simulation, the signal line and the two reference planes are shorted together at one end, while the two reference planes alone are tied at the other end, as shown in Figure 5 .1 2 . The total loop inductance (Lsg) for the stripline structure without perforations, and for the perforated struc ture (X^y) are calculated for several different perforation sizes. Using these values, the discontinuity inductance (AX) is calculated: AX = L'sq — L sg • (5.6) In Figure 5.14, L'SG and AX are plotted as a function of conductor/ plane thickness (assuming the reference plane and signal conductors have the same thickness). This data is for the 10x8 cm opening. The fact that AX is observed to be constant over a wide range of conductor thicknesses indicates that the values obtained for AX will be insensitive to skin effect. Signal Propagation Signal CO o Inductance = Inductance Figure 5.12 Three-dimensional inductance modeling. inductance Three-dimensional 5.12 Figure Stripline L sg Perforation 6 s Discontinuity in Ground Plane in Ground Discontinuity ' Inductance =Inductance Perforated Stripline Stripline Perforated Reference Plane Reference L sg ' 98 99 Figure 5.13 X-Y bar formations for 3-D inductance modeling. 100 AL, Inductance (nH) Conductor/Plane Thickness, t (cm) Figure 5.14 Total, and AZ inductance values vs. conductor/ plane thickness. J 1 0 1 Table 5.2. Comparison of calculated lumped-element values. AL/AC AL/AC AL Discontinuitv Model S-Parameter L2 D/C 2D L3D connector 12.7/5.2, R=4.4 Q N/A N/A perforation 5x1 cm 1.52/0.95 1.29/0.56 2.67 perforation 5x4 cm 7.20/1.82 5.11/2.25 6.73 perforation 5x8 cm 9.52/2.54 10.23/4.49 11.69 perforation 10x1 cm 1.37/0.89 4.68/0.63 5.38 perforation 10x4 cm 12.56/1.73 10.68/2.53 11.24 perforation 10x8 cm 13.25/3.42 15.35/5.05 17.99 perforation 20.4x20.4 cm. 27.42/6.86 39.45/13.09 44.67 Units: AL = nH, AC = pF, N/A = Not Applicable. In Figure 5.15, 2-D and 3-D calculated AL values are compared for different per foration areas. Notice that in the limit of large perforation areas, the 2-D and 3 -D calculated values begin to converge. It is observed that the 2-D calculation should only be used for large-area perforations, specifically when the opening is very wide compared to the signal line width (as discussed earlier). The 3-D total loop inductances L'SG and L sg are plotted as a function of signal line height in Figure 5.16. For the stripline structure (without perforation), symmetrical inductance values are observed about the midpoint height (h = H/2). For the perforated structure, larger inductance values are obtained as the signal line is moved closer to the top reference plane. 102 A Cut Width = 5cm • Cut Width = lOcm # • Cut Open Area (cm2) Figure 5.15 Comparison between 2-D and 3-D inductance values. 103 2 0 .4 X 2 0 4 Cut 10X8 Cut No Cut Conductor Height, h (cm) Figure 5.16 Total inductance with and without perforation vs. conductor height. 104 In Figure 5.17, non-rectangular fixed-width “gap” perforations are shown. Discon tinuity inductance values are calculated for these structures using the 3-D method. Results show that these discontinuities generally introduce a larger inductive discon tinuity compared to a rectangular hole of identical area, however, lower capacitance values are obtained. As the gap width increases, the inductance and capacitance values for these slotted structures approach the values associated with equal-area rectangular openings. 5.6 Comvarison Between Measurements and Simulations The TDR measurement setup used in this study was shown in Figure 5.9. Figure 5.18(a) shows the ASTAP simulation (smooth solid line) and the measured (ragged line) waveforms for the calibration line. Signal reflections received from the scaled model are shown within the highlighted box. Notice the two different discontinuities: 1 ) BNC connector T-junction, and 2 ) connector (including a BNC connector) to the scaled model. The risetime at the end of the launching cable was measured to be 920 ps. It is observed that it is almost impossible to match exactly the connector transients with simulation. The reason is that the bandwidth of the oscilloscope used is limited to 1 GHz with a T-junction connection (R=lmfZ, C=10 pF). However, in the scaled model, the distance between the connector and perforation discontinuity is large enough so that each of the different discontinuities can be identified uniquely in the TDR measurements. In Figures 5.18(b), 5.19(a), and 5.19(b), comparisons between measure ments and simulations are shown for a 5x1 cm, 5x4 cm, and 5x8 cm perforation, respectively. The total top reference plane area is (30.5x61 cm) 1860.5 cm2. Here the 3-D inductance and 2 -D capacitance values are used with a lossless transmission line in all of the ASTAP simulations. 105 Top Reference Plane 2 0 c m 3 0 c m — ► Direction of Transmitted Pulse Uffl Reference Plane Perforation GapSize1h Inductance,AL Gap Size, h Inductance, A L (cm)______(nH) (cm) (nH) 1.0 2 2 6 0 1.0 22.66 2 0 2 6 2 6 2 .0 2 6 2 9 Figure 5.17 Inductance modeling for “gap” type perforation discontinuity. Figure 5.18 Figure Voltage (V) Voltage (V) - 0.5 0.0 0.5 1.0 2.0 1.5 - 0.5 stripline, b) 5x1 cm perforation size. perforation cm 5x1 b) stripline, ) oprsn ewe maueet ad iuain for simulations and measurements between Comparison a) 0.0 0.5 ie (sec)Time ie (sec)Time 1.0 1.5 xicr xicr 8 8 2.0 106 iue51 a Maueet ad iuain for simulations and Measurements a) 5.19 Figure Voltage (V) Voltage (V) size, b) 5x8 cm perforation size. perforation cm 5x8 b) size, ie (sec)Time 5 x 4 m perforation cm 107 iue52 a Maueet ad iuain fr 01 m perforation cm 10x1 for simulations and Measurements a) 5.20 Figure Voltage (V) Voltage (V) size, b) 10x4 cm perforation size. perforation cm 10x4 b) size, ie (sec)Time 108 109 In Figure 5.20(a), 5 .2 0 (b), and 5.21(a), comparisons are shown for 10x1 cm, 10x4 cm and 10x8 cm perforations. Good agreement on signal reflection (AV) amplitudes and general waveform characteristics are obtained between measurements and sim ulation for all structures. In these figures, 1.0 V corresponds to a 50 impedance. The measured impedance of the model is 45.8 ft, compared to a calculated value of 42.4 ft. A launching-cable impedance of slightly less than 50 ft is observed due to the T-junction, high-impedance connection to the scope. In Figure 5.21(b), signal propagation over a large (> 20 % of the total reference plane area) perforation is shown. As expected, AV increases with per foration area. In Figure 5.22(a), the effect of perforation size is shown for a 5 cm perforation width. A similar set of waveforms are shown in Figure 5.22(b) for a 10 cm-wide perforation. The TDR measurements demonstrate that for very small perforation widths and/or lengths, a narrower AV (spike) is observed. In Figure 5.23, the effect of perforation area on AV is shown for three different perforation widths (5cm, 10cm, and 20.4 cm). 5.7 Full-Wave Analysis of a Periodically-Perforated Structure A three-layer FR-4 test card has been built and studied which contains periodic ground plane openings located directly beneath a stripline (see Figure 5.4). This test line is amenable to study using in-house full-wave EM tools which require that the structure to be analyzed fits on a uniform, periodic grid [5.12]. Two major test lines are designed into the 62-mil thick card: (1) a stripline with six (300x50 mil) perforations; and (2) a stripline with eleven (225x25 mil) perforations. The perforations are on a 1 inch and 0.5 inches pitch for the two cases, respectively. iue52 a Maueet ad iuain fr 08 m perforation cm 10x8 for simulations and Measurements a) 5.21 Figure Voltage (V) Voltage (V) size, b) 20.4x20.4 cm perforation size. perforation cm 20.4x20.4 b) size, ie (sec) Time 110 Figure 5.22 a) Signal disturbance disturbance Signal a) 5.22 Figure Voltage (V) Voltage (V) 0.5 — oainwno it, b) width, window foration perforation window width. window perforation (AV) Time(ns) ie (ns)Time vs. perforation length for 5 cm per cm 5 for length perforation vs. V A vs. perforation length for 10 cm 10 for length perforation vs. 111 112 Time (ns) Figure 5.23 AV vs. perforation area (different widths). 113 A unit cell discontinuity model used in the 3 -D inductance calculation is shown in Figure 5.24. Using the full-wave program, both structures are analyzed, resulting in values for the per-unit-length inductance, capacitance, and impedance for the lines. Current distributions for the conductors are also obtained, as exemplified in Figure 5.25. The connectors are not modeled, but lumped-element equivalent circuits are obtained for them using the S-parameter approach described in section 5.3. It is found that the SMA connector and plated-through hole are well-represented by a single inductance and capacitance with values of 0.11 nH and 1.06 pF, respectively. The creation of a mixed transmission-line/lumped-element model for the striplines proceeds in a similar way to the methods described earlier. First, the L and C values obtained from simulation for the lines, both with and without the ground plane perforations, are compared. Any additional inductance observed for the former case is due to the presence of the openings. The change in per-unit- length inductance is divided by the number of openings per unit length in order to arrive at a lumped-element, additional inductance for each opening. This value is added to the nominal inductance associated with a length of line equal to the length of the opening. The resulting inductance is placed in series with transmission-fine segments at the location of every opening. A similar exercise is performed to derive the shunt capacitance at each opening. The inductance values obtained using the full-wave method are compared to values obtained using a straightforward, 3-D partial-element equivalent circuit modeling program. The data are given in Table 5.3. The final measure of the accuracy of this approach is in how well the mea sured TDR waveforms can be duplicated in time-domain circuit simulation. 114 Top Reference Layer 0 0 0 0 0 H Connection Scheme Bottom Reference 200 225 Layer Figure 5.24 Card structure, unit cell discontinuity inductance modeling. 115 > > ^ . .Y .Y .... Y* Y% Y T? A " A" A A" AA‘'‘A”A 'A >: A >:••>;• aa■•A'A"A">. Y Y ,Y. *« Y# .Y# r. ^ V. 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X T Y Y Y.....X .X X X X H: ^ ^ ^ ^AA ^A A ^ A ^ ^ 1 Y Y Y A A A AA A A X, X X, X X X Y Y Y-i-.X^ ^X X.X V ^X. ^ ^ ^ ' Jj ' J «•■• f Y Y Y A A A AA A A r Y Y Y .. .^e.. ^ta. ..^. r . .Y..Y- Y..r X. X...X..X -X. X...^... ^ ^ ^ A A A AA AA A X X .r. Y . J ^..!. jj .Ji-.X .X ..X..X. .ji...j^....~. l i t XY Y r a a 1 1 % % k A A A XY Y Y .Y ^ ! ' ■ >' A " A A T' ^ X k A A A X X X X X XY A A A f'A A A A Y X X XY Y Y Y > X X X XV Y .Y Y k H A "'"A A A A A % % AAA "A A A A A % r t ,.t. ^ v >■ Figure 5.25 Return current path on the top perforated reference plane. 116 21 22 23 24 25 26 xlO"9 Time (sec) Figure 5.26 Measurement and simulation comparison for eleven perforated model. 117 In Figure 5.26, TDR-measured transients are compared with ASTAP simulations for the eleven-perforation model, using the lumped-element values obtained from the full-wave tool. It should be noted that the periodic structure provides a very stringent test of this approach, since any small deviation in lumped parameters results in a significant change in not only the amplitude of the reflections, but in their occurence in time as well. Table 5.3 Comparison of calculated lumped-element values. LgaP{riH)/CgapiviF) Lgap{xiB?)/Cgap{^ Discontinuitv Model Full-Wave Method L3 D Method 225x25 mil 0.65 nH/0.058 pF 0.63 nH/(N/A) 300x50 mil 0.81 nH/0.063 pF 0.87 nH/(N/A) N/A = Not Applicable 5.8 Summary Successful package engineering relies on accurate and rapid prediction of time-domain waveforms inside real structures. A method for constructing equivalent circuit representations for signal propagation over non-continuous reference planes has been described. The method can employ a number of very different tools, including partial-element and full-wave tools, and arrive at the same equivalent circuit. Through comparisons with measured data, confidence in the ability of this approach to provide acceptable accuracy has been shown. Appropriate ranges of applicability have been established to aid in selecting the best combination of modeling tools. For example, it was shown that when the perforation area becomes small (relative to the reference plane total area), detailed 3-D inductance modeling is 118 essential for accuracy. Design guidelines were also presented to help estimate when perforation discontinuities can be safely ignored. In high-speed applications where they are important, the method described here can be used to predict time-domain waveforms accurately prior to hardware prototyping. 119 C H A P T E R 6 NOISE IMMUNITY CHARCTERISTICS OF CMOS RECEIVERS AND EFFECTS OF SKEWING/DAMPING/CMOS DRIVER SWITCHING WAVEFORM ON THE “SIMULTANEOUS” SWITCHING NOISE 6.1 Introduction In high-speed, high-density CMOS VLSI chips, many output drivers may switch simultaneously. Due to package parasitics, when these outputs switch si multaneously, a significant amount of power/ ground noise may be generated in the package Vd d /V ss planes and also in the internal (on-chip) Vd d /V ss busses. Note that simultaneous switching noise characteristics (i.e., amplitude, width and damp ing behavior) not only depend on the drive strength of these output drivers, but also depend on the package parasitics [6.1]. Unless these power/ ground noise fluc tuations are controlled, simultaneous switching noise can degrade or even limit the system performance. In practice, several inputs (both TTL compatible and CMOS) may share the same power/ground busses with the output drivers on chip. Note that even if separate external (for output drivers) and internal (for input receivers and logic) Vd d /V ss busses are used, they may be connected through the same Vd d /Vss plane connections in multichip modules. Thus electrical decoupling is not assured. Since TTL compatible input switching points are centered around 1.2-1.6 volts, ground noise must be controlled carefully to avoid false switching on TTL receiver 120 inputs. To avoid such disaster, one has to take into account the maximum noise immunity of these receivers. Due to the device and associated parasiitcs, input receiver noise immunity depends on both the amplitude and width of the noise spike. A general noise pulse width vs. amplitude noise immunity curve is shown in Figure 6.1. Recent studies have shown that when we scale down devices, due to the parasitics associated with CMOS circuits [6 .2] noise immunity of these receivers do not scale down linearly. To demonstrate this non-linear behavior, CMOS receiver noise immunity design curves (for both CMOS and TTL compatible inputs) are shown for different channel lengths in the following sections. One awy to control switching noise is to increase of bond connections and package pins connected to power and ground. However, if the multichip module is bond pad-package pin limited, the system designer may be confronted with the problem of having to minimize the power/ground fluctuations by indirect reduction in the number of outputs switching simultaneously realized by delaying switching of some outputs. Usually high speed designs require that many outputs be able to switch within one clock wait cycle (for example, eight or sixteen bit data/address bus switching from FF-00 or FFFF-0000). Because of (bonding+plane+pin) para sitics connected through the source end of the output transistors, both power and ground noise generally exhibit underdamped oscillations. Underdamped oscillatory switching noise waveforms are generated from each output, and noise from “early switching” outputs generally superposes on noise generated by the switching of the “later switching” skewed outputs. The damping coefficient and frequency is a func tion of multichip module parasitics. In order to damp out power and ground noise, additional damping resistors may be used at the source end of both P and N channel transistors of output drivers [6.3]. Figure 6.1 Typical input receiver noise immunity characteristics. immunity noise receiver input Typical 6.1 Figure Ground Noise Amplitude, A (V) e Region fe a S rud os dh W(ns) W idth, W Noise Ground Receiver H h- W -H U nsafe Region nsafe U Internal Logic Internal DC " Switching Voltage "DC Switching 121 122 Design curves are shown to explain the trade-offs in using an additional damping resistor and the effects of skewing outputs in high-speed output driver designs. 6.2 Driver Switching Noise and Receiver Noise Immunity Consider n CMOS output drivers switching simultaneously with several different (drive strengths) and switching speed. Assume each output is switch ing symmetrically around the point To (any arbitrary time). Using an equivalent lumped (R,L,C) model for package parasitics from on-chip Vss bus to the end of the package Vss pin, it can be shown that the ground noise produced by n number of output drivers simultaneous switching noise Vn is given by [6.4] P Vi + — f 1 + 2 U* ^ ~ 1 ^ X1 (6.1) V E ”=i # P where Ki = pnCox(W/L) for the ith N-channel output driver device and p is the number of Vss bond pad-package pin (one-to-one correspondence between chip- plane bond and package pin) connections. Here T, is the time taken for the ith switching current spike to travel from zero to its maximum peak value, L1 is the effective inductance of each Vss pad-pin connection and 14 = I'm — Vt (V# is the threshold voltage of the N-channel device). A very useful ratio (relating n and p) can be derived [6.4], P (Vk- Vn)2 Ll (6.2) E IU # 2v-n From here on only ground noise and ground noise immunity is analyzed. It is clear from equations (6 .1) and (6 .2 ) that ground noise exhibits sub-linear behavior as a function of both n (number of outputs switching) and p (number of pad- pin connections). The negative feedback mechanics which cause such sub-linear behavior are explained detail in [6 .1],[6.4], In Figure 6.2, ground noise is plotted as a function of number of simultaneously switching outputs for different channel lengths. 123 A 1.0 ns rise time and L1 / p=2.5 nH were used for SPICE (with typical level- 2 device parameters) simulations. Note that L is used for output driver channel length in Figure 6 .2 . Note that from equation (1) as n approaches infinity, ground noise approaches V& (« 4.0 V). As we scale down the output devices (to minimize delay), ground noise approaches Vk at a faster rate for small geometry devices. When the drive strength and/or the number of outputs simultaneously switching increases, ground noise increases. A detailed analysis of switching noise behavior with device scaling is contained in [6 .2]. From equation (1 ), one method to reduce the ground noise is to increase the number of I/ss pad-pin connections. This method can be expensive due to the increase in number of Vss chip-bond pads and package pins. To have a reliable system, one needs to specify the maximum tolerable ground noise. To specify such values, it is essential to understand the noise immunity of the devices which are connected through the same V5 5 busses and planes. In Figure 6.3, TTL level compatible (switching point around 1.2-1.6 V) CMOS receiver noise immunity characteristics are shown. This receiver is connected to internal logic. A CMOS inverter (switching point around 2 .2- 2 .8 V) was used as a representative of internal logic. Typical lumped package parasitics (R = l mfl, L=5 nH, and C= 1 pF) were used for SPICE simulations. Note that the critical noise amplitude and width curve is where the receiver triggers the internal logic. The region (corresponding amplitude and width) above the immunity curve will lead to false switching, while below the curve it is safe. For noise pulse widths less than 2 ns the receiver can tolerate larger noise amplitudes compare to widths greater than 2 ns. For widths greater than 3 ns, the noise immunity is fixed at a certain amplitude. Ground Noise (V) Figure 6.2 Ground noise vs. # of simultaneously switching outputs. switching simultaneously of # vs. noise Ground 6.2 Figure ubro iutnosSicig N Switching, Simultaneous of Number 124 125 j , > Internal < Receiver Logic -o 2 0 CL E < o o j______i______i______i______i______i_ *■ o I 2 3 4 5 6 Noise Width, W (ns) Figure 6.3 TTL level compatible CMOS receiver noise immunity behavior. 126 This makes sense since the noise levels the receiver sees are a constant voltage level for a “long” period of time. In the previous noise immunity curves, the ground noise was injected into the input of the receiver. The reason for this is that while many outputs are switching simultaneously some of the outputs can be D.C. “ON”. These D.C. “ON” drivers can permit feed through of the ground noise (N-channel device acts as a resistor) onto the input of the receivers. In Figure 6.4 the D.C. “ON” driver ground noise feed through is shown. It is assumed (for worst case) that this driver is connected to a TTL compatible CMOS receiver placed close to the driver (neglect the attenuation and dispersion of noise spikes due to traces connecting them) in a multichip module. As expected, ground noise with pulse widths less than 3 ns can tolerate larger amplitudes compared to pulse widths greater than 3 ns. The exact cut-off point can vary for different technologies. This is because the cut-off point depends on the parasitics associated with the device. However the trend is similar and it is shown in Figure 6.4 for different device channel lengths. 6.3 Effects of Skewing Output Drivers If a system design permits the designer to skew (within one clock wait cycle) some of its outputs, then not all outputs are switching together at point To. For the simplest case, consider two outputs with one switching at To and the other at To + AT (skewed by AT time). Due to the R,L,C circuit on the ground path, switching current obeys the differential equation [6.5] L£m + Rm + m = 0 (6.3) Notice, for most package parasitics, R2 - 4 - < 0 , 127 Receiver Ground Noise Width, W (ns) Figure 6.4 Effects of ground noise feed through from D C. “ON” drivers. 128 WP/WN = 303/I96 CL= 25 pF L = 0.25/im Skewed Time, AT (ns) Figure 6.5 Effects of skewing CMOS output drivers. 129 and the waveform follows an underdamped oscillatory behavior. This underdamped current waveform damps out with a damping coefficient of R ex p (^ -)t and has period which decreases with time. The quasi-period (T /) for an impulse response is [6.5] I L C Td' (6.4) where the quasi-period is defined as the first (maximum) period of the underdamped current waveform. Knowing the underdamped characteristics for the switching cur rent and neglecting the effect of resistor (« Imfi) on ground noise (6.5). Vn * L j ; ’ one can calculate the oscillatory behavior of ground noise. The corresponding quasi period for damped ground noise (Td) is Td % Td /2 [6.4]. Note that if the oscillation is a periodic waveform (without damping), when outputs are skewed by AT time, the minimum ground noise would occur at AT=T, 3T, 5T, ... where T is defined in Chapter 3.0. However, for a quasi-periodic wave form (damping), there will be a global minimum followed by several local minima. This is because amplitude of an underdamped ground noise waveform decreases with time. To minimize the switching noise by skewing outputs, it is important to skew the outputs with appropriate AT to achieve this global minimum. For quasi- periodic underdamped oscillations described by equation (3), the global minimum occurs at ATS, where ATS (6.6) and is an average half quasi-period of the damped ground noise. Notice T / only depends on the package parasitics, and T depends on both package parasitics and output driver strength. 130 (Output Driver Final Stage) < 150 Rd = Damping Resistor Average Delay Figure 6.6 Performance vs. switching noise limitations on output drivers. 131 To demonstrate the effects of skewing, a case of eight similar outputs switching was simulated using SPICE. In this example four outputs switch simultaneously at To and the other four outputs switch simultaneously at To + AT. Using equations (6.4), (6.6) and with lumped package parasitics R=1 mfi, L=5 nH, and C=1 pF, the global minimum ground noise occurs when ATS=0.78 T. In Figure 6.5, ground noise is plotted as a function of AT, where T for 2.0 /xm and 0.25 fim. channel length output drivers are different. Results from SPICE simulations and use of the quasi- periodic waveform technique agrees well. For scaled devices, and/or more than four outputs simultaneously switching, ground noise can be reduced significantly by skewing half of the output drivers with ATS time. For commonly used packages and typical drive speeds, ATS is in the order of 1-2 ns. When the output switching speed increases, T decreases and thereby ATS decreases. 6.4 Trade-offs in Usins Damvins Resistor For a given CMOS technology, once the device sizes are chosen for speed, switching noise is limited by that output driver device size. To show this limit, a simple CMOS output driver was simulated for a specific load (C'z,oo (2 Output Drivers Simultaneously Switching) Wp/WN = 303/196 L =IO/im C^=25pF Z 0.2 P 0 .0 Time (secX 10 ) Figure 6.7 Underdamped oscillatory ground noise behavior. 133 WP/W N = 3 0 3 /1 9 6 L = lO^im C|_= 25pF •S 3 0 * 2 0 Number of Simultaneous Switching, N Figure 6.8 Effects of damping resistor on the switching noise. 134 If silicon area is not a criteria, poly interconnect resistor can be used as a damping resistor. Poly interconnect resistors provide smaller variations on the resistance values with process/ temperature variations compare to diffusion resistors [6.3]. In Figure 6.7, the two output drivers simultaneously switching case was simulated to show the trends in ground noise behavior with and without damping resistors. The output driver sizes (Wp=303 /mi, Wn=196 /ma, and L=1.0 /mi) were selected to drive Ci,oad=25 pF with an average delay [(tpL# + ipHi)/^] of 2 ns. Note that ground noise reduces by 40 % when a 50 ft resistor is used, and for a 100 ft resistor the noise reduces by 75 %. Even with 100 ft damping resistor, to drive the same load (Cxoad=25 pF) in 2ns average delay time, the driver sizes only need to be increased to Wp=345 /mi and Wn=224 /mi. It is clear from Figure 6.7, as we increase the number of outputs switching simultaneously, the use of an addi tional damping resistor can greatly reduce the noise without degrading the switching speed. The trade-off is in silicon area to increase the channel widths of the output driver circuit and realization of damping resistors using either poly interconnect or diffusion resistors. In Figure 6.8, ground noise is plotted as a function of the number of outputs switching simultaneously for different values of damping resistors. A 1.0 ns rise time and T1/p=2.5 nH were used for SPICE simulations. As expected, the ground noise decreases for larger values of damping resistors. Selection of damping resistor value to reduce the ground noise depends on specific system requirements on speed, noise levels, area, and sink/source capabilities of output drivers. 6.5 Summary A detailed investigation into the maximum tolerable ground noise was pre sented using noise immunity curves. A rule-of-thumb on skewing outputs was de rived to minimize the switching noise by skewing outputs. Use of an additional 135 damping resistor in the output driver circuit to reduce the switching noise was demonstrated. Trade-offs in using an additional damping resistor were analyzed. 13© C H A PTER 7 APPLICATION SPECIFIC OUTPUT DRIVER CIRCUIT DESIGN TECHNIQUES TO REDUCE SIMULTANEOUS SWITCHING NOISE 7.1 Introduction \ As we scale down CMOS devices into the sub-micron region, the operating frequency of an output driver increases (frequencies over 60 MHz) which translates to reduction in rise/fall times and pulse width. For a 5 V supply, this corresponds to an output transient time less than 0.4 V/ns for a given load capacitance (i.e. Tr = Tf < 2.0 ns for Cioad = 25 pF). As explained in the previous chapters, SSN must be limited within the maximum allowable noise level. Unless power and ground noise are controlled, reliable operation of logic devices that are connected to the same Vd d /V ss busses is not guaranteed. Some of the encounted problems with false-operations due to simultaneous switching noise are; 1) false triggering, 2) double clocking, and/or 3) missing clocked pulses [7.1]. Some techniques to reduce simultaneous switching noise are explained in the previous Chapters. Notice that each technique has its own advantages and its limitations. As we switch more and more high current drive outputs, not only a low effective inductance “L v s s” is essential, but also clever circuit designs to control the rate of change of switching current (di/dt) through device-package Vdd/Vss is essential to reduce SSN. Two different custom output driver design methodologies are often practiced in Application Specific Integrated Circuits (ASIC’S) [7.1]; 1) 137 Current Controlled (CC) output driver [7.2], and 2) Controlled Slew Rate (CSR) output driver [7.3]. In this Chapter both the current controlled, and the controlled slew rate output driver design methodologies are investigated in detail. In addition to reduce SSN, circuit design techniques have also been used to control the reflec tion noise by controlling the output rise/fall times of the output drivers [7.4],[7.5]. Application specific, tri-statable controlled slew rate CMOS output drivers were designed, and their performance and SSN are analyzed in detail. Performance and l SSN of CSR output drivers were compared with conventional (current unregulated) output drivers. Advantages in using these CSR output drivers to switch a large number of outputs (> 32) are explained. 7.2 CMOS Output Driver Switching: Current Components In order to design application specific Current Controlled (CC) or Con trolled Slew Rate (CSR) output drivers, it is essential to understand the output driver switching current components. Note that the rate of change of switching current (di/di) is proportional to the ground noise for a given package design (L vss fixed). As explained in Chapter 3, both the through current (also known as the over lap current) It , and the charging/discharging current Id contributes to the total switching current through the Vd d /V ss device-package interface. To demonstrate the impact of these current components on the total switching current, a standard CMOS output driver (for 1-^ m Leff. Wp=250, W)v=160) with 1 ns input risetime was used [7.1]. The simple final stage of a CMOS output driver circuit is shown in Figure 7.1a. Three different capacitive loadings were selected for this study. Output voltage switching characteristics are shown in Figure 7.1b for CLoad—Q, 25, 100 pF using curves A, B, and C respectively. 138 —4 In Out CLOAD (a) Time (ns) (b) Time (ns) (c) Figure 7.1 a) CMOS output driver switching characteristics, b) Voltage' switching characteristics, c) Current switching characteristics. 139 Switching current through the Vss device-package interface path (source end of the N-channel transistor) is plotted in Figure 7.1c. Notice that since both the final stage P-channel and N-channel transistor inputs are connected to the same node (gates are tied together), and therefore through current is not minimized. This effect is illustrated in Figure 7.1c where the rising edge of the total switching current is controlled by the through current for all three capacitive loadings. Because of this, the maximum di/dt is almost same for Cz,Oa In = ^ ( V , - V,„)2 , (7.1) where K n = UnCoxi^j;)-, Vg is the gate voltage, and Vtn is the N-channel transistor threshold voltage. Similarly, the P-channel saturation current is [7.6] /p = ^ (Vdd - V3 - V,t f , (7.2) where K p = ^pC'0i(^-), and Vtp is the P-channel transistor threshold voltage. It has been shown that by requiring that Ip = In , the switching voltage Vqt is [7.7], T7 y/Kp Vdd + \/K n Vtn — \/K p Vtp (7.3) VGT = ------^ + ------140 The maximum through current Jr (max) is gi ven by [7.7], KpjKp Ixirnax) {vDD - vtp - vtny (7.4) 2 ( x/Z jv + y / K p ) The discharging current {Id) when the output switches from Vdd to 0 volts is, dV CLoad (7.5) or, approximately, Vdd I d Cload (7.6) Tf where Tf is the output fall time. Notice that Tf is a function of CLoad- 7.3 Current Controlled Output Drivers The objective of a Current Controlled (CC) output driver is to control the maximum switching current Imax of the switching output. Here I max ~ max [7t , To] . (7.7) Notice, controlling the switching current also limits the switching speed of the out put driver. For example, if the maximum switching current is limited to Imax then for a given load capacitance CLoad, the output switching transient is limited by, CLoad Vd d 0 \ r = ------. (7.8) d-max In Figure 7.2, a typical current controlled CMOS output driver circuit is shown. For the current controlled output driver circuit shown in Figure 7.2, the charging and discharging currents are limited by Jp(max) and 7#(max). Here 7p(max) and 7#(max) are realized using simple current mirrors [7.8]. From equation (7.8), the output driver rise/fall times are limited to, CLoad Vd d Tr (7.9a) Ip(max) and _ CLoad :Vd D (7.96) I^{max) 141 1 ) Ip(mox) In(mox) Figure 7.2 Current controlled CMOS output driver. 142 The increase in output transient time, and the realization of a low V0i for a given I0l are major limitations in using current controlled output drivers. Note that the switching speed of a fully current controlled output driver is always less than or equal to the switching speed of an equivalent current unregulated output driver. To have both the current unregulated (when switching current is lower than Imax) for the slower switching conditions, and the controlled (switching current is equal or greater than I max) for the faster switching conditions, a complimentary switch is designed. In Figure 7.3, due to symmetry, only the sink portion of the current controlled output driver circuit with a complementary switch is shown. Notice that input signal to the output driver controls the switch to turn ON and OFF the unregulated (P2, N3, and N1 OFF) and the controlled (P2, N3, and N1 ON) switching current. 7.4 Controlled Slew Rate Output Drivers The objective of a Controlled slew Rate output driver is to control the output driver’s switching rise and fall times. To control the rate change in switching current (di/dt) by controlled slew rate, designer has to make sure that the output driver design is not limited by the through current. This can be achieved by not connecting the gate terminals of the output stage P-channel, and the N-channel transistors and making sure that there is a skew between the P-channel and the N-channel turning OFF/ ON and ON/ OFF times. In Figure 7.4, a commonly used tri-statable (with enable high) CMOS output driver circuit is shown. In practice, the pre-driver Vd d /V ss are connected to the internal (also called clean) Vd d /V ss buses, and final stage output driver Vd d /Vss buses are connected to external (also called noisy) Vd d /V ss buses. This is because, final stage driver device sizes (channel width) are very large compared to the internal or even to the pre-driver device sizes. 143 DD T max Figure 7.3 Switching current controlled/unregulated CMOS output driver. 144 VDD Enable H ------P re-d riv er------►H------Driver------N Figure 7.4 A typical tri-statable (enable high) CMOS output driver. 145 As explained in Chapter 3, increase in channel width increases the drive strength, and also increases the switching noise. However, increase in final stage output driver device sizes also increases the input capacitance of these devices. The increase in input capacitance of the final stage may demand a larger drive strength pre-driver’s compared to the internal gates drive strength to minimize the delay of the overall output driver [7.1]. Note that NAND, NOR, and other logic gates (except inverters and pass transistors) require larger silicon area with high input capacitance compared to simple inverter to achieve a certain current drive. A high-speed, tri-statable (with enable low) CMOS output driver circuit utilizing the inverters for pre-driver’s is shown in Figure 7.5. The functionality of these tri-statable drivers shown in Figures 7.4 and 7.5 are given in Tables 7.1 and 7.2 respectively. Table 7.1 Tri-statable (enable high) CMOS output driver (Figure 7.4). Enable Data Out 1 X Z 0 0 0 0 1 1 Table 7.2 High drive, tri-statable (enable low) CMOS output driver (Figure Enable Data Out 0 X Z 1 0 0 1 1 1 Here x = don’t care and Z = high-impedance or high-Z state. Enable Pre-driver -Driver Figure 7.5 High-speed, tri-statable (enable low) CMOS output driver. 147 It is important to skew the arrival times of the input signals of the final stage to minimize the output driver through current component. This can be realized by selecting an appropriate pre-driver device sizes. Skewing the switching time at the final P-channel and N-channel transistors give rise to the overall delay. However, for high current drive output drivers, with a little trade-off in delay, significant reduction in switching noise can be realized. In Figure 7.6, a typical tri-statable output driver voltage and current switching characteristics are shown for a standard, and reduced through current output drivers. Even with reduced through current output drivers, there exist a delay-SSN limitation. This is because increase in final output driver device channel widths to reduce the overall delay increases the switching noise. In Figure 7.7, delay-SSN curve for a 8.0 mA (D.C. sink for T4/=0.4 v) tri-statable output driver is shown. This delay-SSN limitation can be a major limiting factor in a system design, especially when a large number of high current drive outputs switch simultaneously. It is important to control the maximum switching current Imaxi and also the time it takes for this current spike to reach its maximum value (T) to reduce the “effective” simultaneous switching noise. In Figure 7.8, Controlled Slew Rate (CSR) tri-statable CMOS output driver circuit is shown. Functionality of this driver is given in Table 7.1. These CSR output drivers were designed for the following drive strengths; 1) PLIO (3.2 mA D.C. sink for Vof=0.4 v), 2) PLI03 (8.0 mA D.C. sink for V'o/=0.4 v), and 3) PLI05 (12.0 mA D.C. sink for Po/=0.4 v). As shown in Figure 7.8, in these CSR output driver designs, final output stage of these drivers are split into several driver segments. It was found, when the current drive of the drivers increase, the number of optimal segments required to control the “effective” di/dt also increases [7.9]. 148 V (Volts) Time (ns) A: Standard Output Driver B: Reduced Through-put Current Output Driver Time (ns) Figure 7.6 Tri-State output driver switching characteristics. 149 C|_= lOpF (Pre-driver + Driver) Average Delay (ns) Figure 7.7 Driver delay-switching noise limitations. 150 Enable D river # 2Driver #1 Driver # 2Driver Driver # 3 Figure 7.8 Tri-statable, Controlled Slew Rate (CSR) output driver. 151 Simulations have demonstrated that more than three driver segments in the final stage is useful only when the output ^current drive is greater than 32 mA (D.C. sink for Voi=0A v), and driving a load capacitance of 25 pF or greater [7.9]. A final output driver stages using there driver segments (as shown in Figure 7.8) was used in PLIO, PLI03, and PLI05 CSR output driver designs. The weighted ratio of 1:2:3 was selected for driver segment (1, 2 and 3) device sizes respectively. For example, for a conventional PLI05 driver Wp=624 fim and Wjv=414 fim , the following device sizes were selected for the CSR PLI05 driver stages; 1) Wp\ =104 /wn, Wjvi=69 /mi, 2) Wp2=208 /ma, Wjv2=138 /mi, and 3) Wp3=312 /tm, Wjv3=207 /mi. Similar weighting scheme (1:2:3) was used to calculate the device sizes of final stage output driver segments of the PLI03 and the PLIO output drivers. Notice that the increase in driver device sizes increase the input capacitance, and this act increases the delay time between each driver segment’s switching time AT. For example, if N or P-channel transistor in driver stage number one switches at T0 (arbitrary time) time, then second driver switches at T0+ A T \ time, and the final (or third) driver switches at T0 + AT2 time. Note that all the P-channel and N-channel transistors in each driver segments are designed to minimize the through current on all driver segments. The input capacitance (C/) of each stage is proportional to, C l — k W^total Cunit (7.10) where W(oW=total channel width, k=fringing factor, and Canif=per-unit-length capacitance for a given CMOS technology (Leff fixed). With the switching point centered around volts, and using RC tree, delays between segments can be calculated [7.10]. A T f = i R 2 (C f 2 + C f ) + 5 JZi C f 3 (7.11) 152 A T ? = 1 e 4 Cf3 , (7.12) A T ? = ^ Ei (Cf2 + Cf3) + ^ E3 Cf3 , and (7.13) .AT? = ±R3CP (7.14) where the supercripts on AT and Cj denotes the P or N-channel transistor. Note that the appropriate AT value can be realized by adjusting the driver segments device sizes (vary Cj), and/or changing the resistor (R j) values. The selection criteria depend on the trade-offs between the driver delay and the si multaneous switching noise for a specific application. In this work, a standard 1 Kf2 resistance was used for all four resistors. Even though, poly resistors (sheet) have little variation with process and temperature (% 60 ± 10f2), diffusion resistors (sheet) (% 130 ± 25Q) were used to save silicon area. Note that to control the slew rate by adjusting the AT, the ratio between resistors are important, and not the absolute value. In Figures 7.9 and 7.10 a typical CSR output driver voltage and cur rent switching characteristics are compared with the conventional output drivers. As expected, including the additional resistors (Ri, Eg, E3 and E4) n the output driver design increases the driver delay for a given load capacitance. However these delays are very small compared to the “effective” switching noise pulse width re duction. A typical lumped PGA package parasitics (L yss=5 nH, C V ss=l pF, and E y s s = l mO), and C'i,oa Conventional Driver (I) Driver (1+2) Driver (1 + 2 + 3) Time (ns) Figure 7.9 CSR output driver voltage switching characteristics. M------T + A*------H Time (ns) Figure 7.10 CSR output driver current switching characteristics. 155 From the noise immunity curves shown in Chapter 6, it is clear that larger number of simultaneously switching CSR outputs can be integrated safely compared to the conventional output drivers for a noise limited system design. Table 7.3 Performance-SSN comparison of conventional and CSR output drivers. Driver Tvpe Performance-N oise Conventional Driver CSR Driver PLIO Delay [lh+hl]/2 (ns) 9.6 10.3 5? Sink/Source (mA) 3.5 3.4 95 Noise Pulse Amp. (mV) 430 424 9? Noise Pulse Width (ns) 1.3 0.7 PLI03 Delay [lh+hl]/2 (ns) 7.5 7.8 99 Sink/Source (mA) 9.2 8.3 99 Noise Pulse Amp. (mV) 655 637 99 Noise Pulse Width (ns) 1.6 0.9 PLI05 Delay [lh+hl]/2 (ns) 4.9 5.1 99 Sink/Source (mA) 12.5 12.1 99 Noise Pulse Amp. (mV) 800 741 99 Noise Pulse Width (ns) 2.0 0.8 7.5 Summary Detailed investigations on the CMOS output switching current components, and their impact on the simultaneous switching noise were performed. Current 156 controlled output driver circuit design technique and its capabilities and limitations are explained. Controlled slew rate output driver design technique, and methods of realizing skewing times between driver segments are given. The advantage in using controlled slew rate output drivers over the conventional output drivers to minimize the “effective” simultaneous switching noise was demonstrated. 1ST C H A P T E R 8 SIMULTANEOUS SWITCHING NOISE SIMULATOR (SSNS) ARCHITECTURE 8.1 Introduction In previous Chapters, methods of calculating Simultaneous Switching Noise (SSN) for CMOS based systems, and some techniques to reduce SSN were discussed. Note that these techniques require some trade-offs in the maximum clock frequency or in the silicon area to reduce SSN. As we scale down CMOS devices (Le/ / < l^m) with the reduced-supply-voltage (3.3 or 2.0 volts), and increase the maximum op erating frequency ( /c) together with increase in data/address bus width (> 32-b switching), SSN to signal ratio increases rapidly. Increase in noise to signal ratio can be a limitation in high level integration Multi-Chip Modules (MCMs) [8.1][8.2]. For high level integration CMOS systems, it is essential to minimize SSN by using several techniques, such that SSN is minimized and within the acceptable limits. For a given number of bond-pad and package-pin Vd d /Vss connections, SSN can be reduced with proper placement of bond-pad and package-pin connections. An optimal placement minimizes the effective inductance “L y s s” by minimizing the mutual inductive elements in the inductance network. In addition, SSN can also be minimized by using application specific output drivers instead of conventional out put drivers [8.3]. Measurements have demonstrated that the use of external (other than Vdd ~ Vss plane decoupling capacitor) decoupling capacitors also reduce the overall SSN [8.4]. To implement any of these techniques to reduce SSN, system 158 designers need to incorporate these techniques at the early stages of the system design. This is because these implementations may alter other performance metrics (mechanical, thermal, reliability and cost), and may require formal reliability and quality assurance verifications. A Simultaneous Switching Noise Simulator (SSNS) based on a trial architecture was designed to calculate SSN and to minimize SSN by using several techniques explained in the previous Chapters. A software tool (C program) was developed to verify the functionality of each modules in the ar chitecture, and to assure the overall flow through this architecture. Note that this tool is intented for early system simultaneous switching noise analysis, and/or to guide system designers in the selection of appropriate detailed (computationally expensive) simulations for final verifications. 8.2 Simultaneous Switchine Noise Simulator fSSNS) Architecture In Figure 8.1, a trial architecture to calculate SSN for a CMOS based system is given. Note that, this SSNS architecture requires an “effective” chip- package inductance (L vss) as seen by the output driver’s in their Vss path. In Chapter 5, a method to reduce the chip-package Vss connection inductance network to an equivalent “effective” inductance for a single chip package was explained. A method of modeling “X vss” using similar techniques (as explained in Chapter 4.0) for MCMs is explained in the following section. Knowing the chip-package interface “L v s s ”, and the output driver device and switching characteristics, SSN can be calculated using the methodology explained in Chapter 3. Note that these models include the output driver negative feedback effects which are important in calculating the SSN. Using the above methodology, SSN can be calculated on the on-chip Vdd/Vss buses, or at the package Vdd/Vss planes. 159 Negative Feedback Equation# D C. ON' Driver Perturbation Internal Switching Current Power S Ground Pads/PIns Calculator Effective Waveform Modeling Package Plane Paraaltica Forced Pad/Pin Location Pad/Pin Placement New Faraaltlce? Figure 8.1 Simultaneous switching noise simulator (SSNS) trial architecture. 160 As explained in Chapter 3, the internal gates switching current, and the D.C. “ON” sink/source current also contribute to the overall SSN. In SSNS ar chitecture, the D.C. “ON” driver perturbations are included. This offset voltage is calculated using the D.C. sink/source current and the switching current. For p number of D.C. “ON” N-channel drivers with each sinking D.C. current Ij in their Vss path, the D.C. offset voltage is, P Voffset = Ij(sink) Rvss 4" R v SS (S-l) j=l where Irms(max) is the maximum root-mean-square current, and Irms(max) = (8.2) Note that it is very hard to calculate the internal switching current at any given time exactly, and need an estimation of this current for a given system design. There are empirical formulas relating the number of gates, design architecture, and device feature size to the internal switching current. However, these empirical formulas are very specific for each CMOS chip design house’s, and in SSNS it is defined as a user specified information. In SSNS, knowing the number of V5 5 connections, SSN can be calculated or vice versa. For example, knowing the worst case outputs switching activity, and the maximum tolerable noise, the minimum required number of pad-pin connections is calculated. If the calculated minimum number of pad-pin connections exceed the practical implementation limit, methods of reducing SSN by skewing and/or damping switching noise waveform can be explored. Methods of calculating SSN and trade-off in using these techniques are explained in Chapter 6 . In addition to these techniques, use of Current Controlled (CC) or Controlled Slew Rate (CSR) output drivers also reduce SSN. The negative feedback effects of CC and CSR drivers 161 are very much application specific (to broad to generalize), therefore not included in this version (1.0) of the SSNS architecture. Knowing the minimum required number of Kss pad-pin connections, one can further decrease SSN or the number of Vss pad-pin connections needed for a given maximum tolerable noise level by utilizing an optimal bond-pad/ package-pin placements. Note that proper pad-pin placement can distribute SSN evenly on the Vd d /Vss buses and the planes, and also reduce SSN by reducing the mutual inductive elements in the “L y s s ” inductance network.. 8.3 Modeline: for MCM V A typical MCM Vss connection system is shown in Figure 8.2. A chip- package level with two V s s planes is selected for simplicity. Note that, in all these V s s planes, there are qi number of source points (current into the plane) and pi num ber of sink points (current leaving the plane). In general q, p, and their placements can be arbitrary, however there could be many symmetries in their placements. The frequency-independent package plane parasitic calculator UALGRL [8.5] was used to model the Vss planes. A method of calculating the inductance network using a superposition method for a single chip package with one Vss plane is explained in Chapter 4.0 [8.6]. A similar technique can be used here. The inductance model for Figure 8.2 chip-package Vss connections is shown in Figure 8.3. There are K\ number of chip-package connections (including wire bonding, TAB, or C4) to the first Vss plane. First Vss plane is connected to the second V s s plane with K 2 number of vias. Note that these K 2 number of vias are source points and p number of pins coming out of this plane are the sink points for the second V s s plane. In this first order model, it is assumed that each source point on the Vss plane is at an equipotential, and each sink point is also at a (different) equipotential. 162 Chip-Package Interface Level q, = Number of Vias Above Vss #1 p,=q2=NumberofVias Between Vss# l and Vss# 2 Vcc#2 Figure 8.2 Multi-chip module chip-package Vss connections. 163 Chip-Plane P la n e# I K, Vias plane Plane # 2 Figure 8.3 Multi-chip module “Z-vss” inductance network model. 164 Also mutual inductance between neighboring Vss chip-plane connections, vias, and package-pins connections are negligible. These assumptions are fulfilled if the sink points on the planes are symmetrical around the source points, and each Vss con nections are isolated with Vbd connections. This is because, current flow through Vdd and Vss chip-package connections are in opposite direction and this reduces or even cancels out mutual inductance. Consider a MCM with N number of chips each having $,• number of chip-package Vss connections. Here g; is a percentage of the total number of I/O ’s. In addition, there are m number of Vss planes, with adjacent Vss planes strapped together by means of Ki number of via connections between plane i and i+1, and p number of pins connected to the bottom most Vss plane. Using Figure 8.3, the effective inductance “L v s s” as seen by the output driver is, m—l m—1 r j,j+l L c- p L y ss P3 + E LU°«'(K‘) + E + LJSaneW H---^ (8.3) L i = i 9i i= l J = 1 Here Lc- P is the chip-package inductance for a single connection, Lpiane is the inductance of the ith Vss plane inductance, L^’/a+1 is the inductance for a single via connection between planes j and j+1, and Lpin is the package-pin inductance for a single connection. In this model, mutual inductance between planes is not included. However, for unevenly distributed via or pin connections on an MCM Vss planes, mutual inductance between planes need to be incorporated in the L v ss model. Note that N=1 with m = l in equation (8.3) corresponds to a single chip with one Vss plane connection. 8.4 Simultaneous Switching Noise Calculation for CMOS MCMs Consider N number of “equivalent” CMOS chips in a MCM. Decrease in channel length, and increases in data/address bus width from each chip increases 165 the SSN at the local chip site Vd d /V ss buses. With increase in number of chips and similar probability of outputs switching on other chip sites, SSN increases on all global Vd d /Vss connections. Uncontrolled SSN may degrade or even limit the system performance. From CMOS SSN calculator given in Chapter 3, the maximum peak ground noise Vn for n number of outputs switching simultaneously is, Vn = Vk + 1 - 1 + 2 V& L v ss 5 3 (8.4) L vss 52 8=1 T; \ 8=1 Here Ki = fj,n Cox (W /L) for ith N-channel output driver device, Tt- is the time taken for the ith current spike to travel from zero to its maximum peak value, and Vk=Vin - Vt. L vss is given by equation (8.3). Using equation (8.1), the maximum peak simultaneous switching noise voltage at the on-chip Vss bus is , l/S’S7v(mCUr) — Voffset -b Vn (8.5) To calculate workstation application MCM SSN, the following number of simulta neously switching outputs (n) was used. — (^ of logic chips) {data/address bus width) (8.6) Note that this is not a worst case. It represents a typical case where either the data or the address bus in 50% of the logic chips are switching from low-to-high or high-to-low at a given arbitrary time T. Rent’s rule with appropriate constants (k and /)) for CMOS based MCMs was used to calculate the total number of chip-plane connections Np, Np = 1.4 (Nc ■ NJ/0)° a (8.7) Nc is the number of chips in an MCM, and Nj/o is the number of I/O ’s for each chip. Note that only a certain percentage of these I/O ’s are Vssi and the remaining I/O ’s 166 are Vdd and input/output signals. In practice, only a part of these chip-package Vss connections are package Vss pins (i.e., there is no one-to-one correspondence). In this work, it is assumed that the number of Vss package pins are 50 % of the chip- plane Vss connections. Output driver and package connection parameters used in these calculations are given in Tables 8.1 and 8.2. These parameters are extracted from many industry forecasts [8.1]. In this work, the number of equivalent chips (N) is determined to be, 1 N — (# of logic chips) + - ( # of memory chips) . (8 .8 ) 6 In Figure 8.4, ground noise is plotted as a function of integration level. Note that, with increase in integration level in MCM, the total number of chip-plane connections (Np) and thereby the total number of V s s connections increase. As expected, SSN increases with integration level together with the increase in current drive capability. In Figure 8.4, 10 % (from Np) chip-plane and 5 % package-pin Vss connections were used for SSN simulations. To explain the effects of number of Vss connections on SSN, in Figure 8.5, SSN for 20 % chip-plane and 10 % package-pin V s s connections are plotted. In these Figures, -12 dB noise (SSN) to signal (clean Vdd) ratio is denoted by dash lines. Note that, pushing the noise to signal ratio beyond -12 dB can lead to many unreliable operations. From these results, it is clear that higher levels of integration increase noise to signal ratio. As expected, this ratio increases with reduced supply voltage. Re duction in threshold voltage [8.7], and false triggering even at narrower switching noise pulse in scaled CMOS devices can create many challenges for system designers to reduce noise to signal ratio. 167 Table 8.1 MOM CMOS Chip Integration Parameters. Parameter Year 1991 Year 1995 Year 2000 Leff (fan) 1.0 0.5 0.25 Vdd (v) 5.0 3.3 2.0 V. (v) ±0.9 ±0.6 ±0.4 # of I/O ’s 168 400 608 fchip (MHz) 40 100 250 foot print (cm) 1.75x1.75 2.0x2.0 2.35x2.35 # of logic chips [4,8,12] [4,8,12,16,20] [4,8,12,16,20] # of memory chips [16,32,48] [16,32,48,64,80] [16,32,48,64,80] 1 i i memory/logic 6 6 6 # of equivalent chips [6.6,13.3,20] [6.6,13.3,20,26.6,33.3] [6.6,13.3,20,26.6,33.3] Table 8.2 MCM Integration: Driver and package parameters. Parameter Year 1991 Year 1995 Year 2000 # of drivers switching [32,64,96] [64,128,192,256,320] [128,256,384,527,640] data/address bus width 32/32 64/64 128/128 driver K (A/V2) 4.9xl0“3 9.8xl0-3 19.6xl0“3 T (ns) 1.0 0.7 0.5 Lchip—plane (nH) 1.0 0.7 0.5 Lplane (nH) 0.1 0.1 0.1 Lyia (nH) 0.1 0.1 0.1 4,,* (nH) 1.5 1.2 1.0 ound Noise, dB Figure 8.4 Figure S s MMitgainlvl 1- % (10-5 level integration MCM vs. SSN Number of "Effective Logic" CMOS"Effective ChipsNumber of Year 1991Year er2000Technology 0 0 0 Year2 Year 1995 0 Ci Package Chip 10% % Package-Pin 5% V ,, Connections ,, V Vss connections). 168 Figure 8.5 Figure ound Noise, dB S s MM nerto ee (01 % (20-10 level integration MCM vs. SSN ubro EfcieLgc CMOSLogic" Chips "Effective of Number Year1991 er2000Technology 0 0 0 Year2 Year 1995 0 Chip-Package 20% 0 Package-Pin 10% Vss V«.cConnections connections). 169 170 8.5 Summary A trial architecture to calculate simultaneous switching noise for CMOS based systems, including SSN calculations for MCMs was presented. Applications and limitations in using the SSNS were explained. A method of calculating “L v s s ” for MCM chip-package Vss connections was modeled. Trends in simultaneous switching noise to signal ratio were predicted for future CMOS MCMs. 171 C H A P T E R 9 CONCLUSION An investigation into the behavior of delays and SSN of CMOS devices with constant-voltage scaling was presented in Chapter 2. It appears that interconnects play a major role in the delay calculations for small geometry devices. As a result, accurate modeling of interconnect parasitics is essential for future VLSI chips. Thus detailed modeling of device and also package interconnect parasitics are required to predict the performance of the packaged small geometry CMOS devices/ systems. In Chapter 3, calculation of simultaneous switching noise (SSN) for CMOS based systems was presented. It was found that SSN exhibits a sub-linear behavior with the number of outputs switching simultaneously. As a result, when calculating the switching noise, negative feedback influence must be incorporated in the equa tions. This effect must also be carried out in the power and ground bond-pad and package-pin connections calculations. The trends in output driver switching noise with constant-voltage [CV] device scaling were explained. A method of calculating the “effective” Vdd/Vss chip-package interface inductance “Le/ / ” was presented in Chapter 4. It was found that package-pin placement has a strong influence in the plane inductance values (especially for a small number of package Vss pins). Perforations on the Vss plane perturb the current distribution on the reference plane, and this perturbations increase the plane inductance. Results have shown that having symmetrical placement in the sink points greatly reduce the package plane inductance. The impact of Lpiane on the SSN was explained, and the errors associated with the neglection of plane mutual inductive elements in the inductance 172 network were discussed. In Chapter 5, a method for constructing equivalent circuit representations for signal propagation over non-continuous reference planes was described. This method can employ a number of very different tools, including partial-element and full-wave tools, and arrive at the same equivalent circuit. Through comparisons with measured data, confidence in the ability of this approach to provide acceptable accuracy has been shown. Appropriate ranges of applicability have been established to aid in selecting the best combination of modeling tools. For example, it was shown that when the perforation area becomes small (relative to the reference plane total area), detailed 3-D inductance modeling is essential for accuracy. Design guidelines were also presented to help estimate when perforation discontinuities can be safely ignored. In high-speed applications where they are important, the method described here can be used to predict time-domain waveforms accurately prior to hardware prototyping. In Chapter 6, an investigation of the maximum tolerable ground noise was presented using noise immunity curves. Rules-of-thumb were derived to minimize the switching noise by skewing the outputs. Use of an additional damping resistor in the output driver circuit to reduce the switching noise was demonstrated. Trade-offs in using an additional damping resistor to reduce SSN were analyzed. Investiga tion on the CMOS output driver switching current components and their impact on SSN were analyzed in Chapter 7. Current controlled output driver circuit design techniques, and its limitations are explained. Controlled slew rate output driver design techniques, and methods of realizing skewing times between final driver seg ments are given. The advantage in using controlled slew rate output drivers over conventional output drivers to reduce the “effective” simultaneous switching noise were demonstrated. 173 A trial architecture to calculate SSN for CMOS based systems was pre sented in Chapter 8. Applications and limitations in using SSNS (Simultaneous Switching Noise Simulator) were explained. A method of calculating “L v s s” for MCMs, and thereby a method to calculate SSN using the SSNS architecture for CMOS based MCMs are given. Using SSNS architecture, device-interconnect scal ing rules, and first-order MCMs “L v s s” model, SSN for future CMOS based MCMs are predicted. 174 C H A P T E R 10 DISSCUSSION AND FUTURE WORK 10.1 BiCMOS Outputs Simultaneous Switching Noise Even though Bipolar Junction Transistor (BJT) output driver current drive capabilities are better than its counterpart CMOS output drivers, they dissipate more power. For high level integration Multi-Chip Modules (MCMs), power-delay product is an important performance metric in system performance evaluation. With advancement in CMOS process technology in the last decade, high level of integration can be achieved by using CMOS technology compared to BJT technol ogy. However, one of the trade-off is between speed and integration. With the advancements in scaled (Ze/ / < 0.75/mi) CMOS technology, preliminary trade-off studies have shown that possible technology map for high performance computers, will move from BJT to BiCMOS and eventually to CMOS technology [10.1]. In Figure 10.1, a typical BiCMOS output driver circuit is shown [10.2] [10.3]. Note that, BiCMOS output drivers have best characteristics from both technologies. From BJT devices (Q1 and Q2), a low output impedance and large current drive capability, and from CMOS devices (Ml, M2, M3, and M4), a high input impedance and transient drive with no D.C. power consumption. Owing to the base-emitter voltage of BJT devices, the output swing in BiCMOS output drivers is limited to V0i = Vb e and V0h = Vd d — Vb e - Note that, for the typical BiCMOS output driver circuit shown in Figure 10.1, transistors Ml and M3 provide base current for the BJT transistors Ql and Q2. 175 Vdd Figure 10.1 A typical BICMOS output driver circuit. 176 Transistors M2 and M4 provide a current discharge path for turning-off the BJT transistors Q1 and Q2 respectively. Switching characteristics of BiCMOS output driver depends on several second-order device and associated parasitics [10.4]. Be cause of this second-order effects, negative feedback switching mechanics are com plex, and need more fundamental studies to generalize Simultaneous Switching Noise (SSN) for BiCMOS outputs. Note that, in BiCMOS output drivers, not only the final stage BJT outputs, but also the MOS pre-drivers, and the internal circuits contribute to the overall SSN. 10.2 Use of Substrate-Taps To Reduce Simultaneous Switching Noise As explained in Chapter 4, the effective inductance “L v s s ” include bond ing, package plane, and pin inductance. For a typical 168-256 pins Pin-Grid-Array (PGA) package, bonding, plane, and pin inductance are about 50 %, 10 %, and 40 % of the total “Lvss” respectively [10.5]. One method to reduce “L y s s ” is to reduce the chip-Vss plane connection inductance. In addition to other advantages, con trolled collapse connection (C4) technology provides a low chip-plane inductance. Another method to reduce the chip-plane inductance is to provide an alternate cur rent conduction path from the on-chip Vss buses to the package Vss plane through the substrate (known as “substrate-taps”). Consider a twin-tub, p-type epitaxial CMOS process on a P + substrate. For this CMOS process, there exist a conduction path (if tapped) from the on-chip Vss bus to the bottom ground plane through the substrate as shown in Figure 10.2. With limited measurements on a single product, it was found that SSN can be reduced with the use of substrate-taps. Measure ments have demonstrated that with proper implementation of substrate-taps, even with the removal of all Vss bond connections, the packaged CMOS device was fully functional with reduced switching noise on the on-chip Vss bus [10.5]. 177 Substrote-Top Vss Plane s/s//s// / / / / / / / / / / / / / / / / S//////S///////// a * Conductivity T« Thickness Figure 10.2 Substrate-Taps current spreading. ITS This confirm the existence and the usefulness of the substrate conduction path from the on-chip Vss bus to the package Vss plane through the substrate. The major limitation in evaluating the performance of this technique is the calculation of the parasitics associated with all the conduction path through the substrate. First attempts in modeling these parasitics have demonstrated that it is essential to account for the current spreading in the substrate, and requires rigorous modeling tools [10.6]. A typical chip-package interface parasitics including substrate-taps are shown in Figure 10.3. In Figure 10.3, both the conventional bond ing and the substrate-tap connections are shown. Note that, even if the substrate- tap connection parasitics are comparable to the bonding parasitics (Ls % Li and Rs % Rb)-, a large number of substrate-taps can be placed on most part of the Vss buses. In addition to reducing SSN, substrate-taps also improves latch-up suppres sion [10.7]. Note that, for electromigration limited Vss bus widths (minimum size is determined by the electromigration requirements), use of substrate-taps may de mand to increase the Vss bus widths to fulfill electromigration requirements [10.5]. This is because of the additional taps that are placed in the on-chip Vss buses. 10.3 SSNS Architecture Improvement The SSNS architecture explained in Chapter 9 calculates SSN for a given number of Vss connections, and vice versa. Even though, some methods of reducing SSN and effects of package-pin placements are included, results do not include si multaneous switching noise waveform. In future SSNS development, one can include switching noise waveform modeling. This development can help system designers to evaluate switching noise waveform on the Vss buses, and the package plane as a function of time. 179 Substrate-Taps VSs Bus □ r 3 [’ \ f” ^ Lb f R, R« R, iRb Rbi Plane Rp kp Rp kp 1 Lb, Rb« Cb Bonding 5 Lpio L „ R, Substrate-Taps 3 l-pin Lpk, Rpin Package-Pin ’ Bpm ' Rpin Figure 10.3 Chip-Package interface parasitics with substrate-taps. 180 As explained in Chapter 8, in reality there are additional mutual coupling exist from signal lines to the reference planes, and these mutual inductance elements need to be incorporated in the L vss inductance network. However, with more and more detailed calculations, SSNS will lose its charm as a fast SSN calculator, and may become computationally comparable to the detailed SPICE simulations. Knowing the negative feedback effects in BiCMOS output driver’s, SSN calculation for BiCMOS outputs can also be incorporated. After the development of a de tailed substrate-conduction path parasitic extractor, substrate-taps method can be included in future SSNS. This can be realized by developing a separate inductance network calculator module for substrate-taps, and using it in conjunction with the present inductance network calculator. 181 REFERENCES Chapter 1 [1.1] M. A. Plonus, “Applied Electromagnetics,” McGraw-Hill, Inc., New York, 1978. [1.2] S. Ramo, J. R. Whinnery, and T. V. Duzer, “Fields and Waves in Communi cation Electronics,” John Wiely & Sons, Inc., New York, 1984. [1.3] G. A. Katopis, “Delta-I Noise Specification for a High-Performance Computing Machine,” IEEE Proceedings, vol. 73, no. 9, p. 1405, September 1985. [1.4] A. J. Rainal, “Computing Inductive Noise of Chip Packages,” AT&T Bell Laboratories Technical Journal, vol. 63, no. 1, p. 177, January 1984. „ [1.5] E. E. Davidson, “Electrical Design of a High Speed Computer Package,” IBM Journal of Res. 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