Signal Integrity Simulation and Equivalent Circuit Modeling

Home , Signal integrity

NTU

Tzong-Lin Wu

Department of Electrical Engineering National Taiwan University Taipei, Taiwan [email protected] NTU Outline

z Introduction

z Signal Integrity Simulation in SPICE A case Study: Driver Board of TFT Display Panel

z TDR Concept and Layer Peeling Technique (one port)

z Macro-model Synthesis for Coupled Discontinuities of Signal Path (two-port)

z Challenge of SI Modeling for Real PCB and Package

z Summary NTU Introduction

z With rapidly increased clock rate and denser interconnect layout, noise caused by the discontinuities can be a critical factor to degrade the signal integrity (SI) of circuit systems.

0.025 z Example: Via coupling 0.02

0.015

) t l Signal rising time V o

step v 100ps ( 0.01 50ps

Coupling DT 20ps T 10ps V 0.005 VTDT

-0.005 0 2E-011 4E-011 6E-011 8E-011 1E-010 1.2E-010 t (s)

3 NTU Introduction

Extracting SPICE-compatible models for those discontinuities are essential.

Benefits: 1. More convenient integration with chip circuits under SPICE environment. 2. Better accuracy with higher order of equivalent circuits.

GND

Power 4 NTU Case Study: Driver Board of TFT Display

Time Controller (T-CON)

Driver PCB

Driver IC NTU Case Study: Driver Board of TFT Display

z Objectives of this project: { Signal integrity modeling for the driver PCB and compare with the measured results.

z Approaches: { Establishing SPICE-compatible model for all interconnects and doing SI simulation on HSPICE.

z IC I/O Buffer Model { SPICE model { IBIS model Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

Step 1: Trace all interconnects from driver (T-CON) to receiver (driver IC)

Differential line TCON (with GND) via1

Differential line (no GND) via3 via3

via2

FPC FPC FPC Driver IC Driver IC Driver IC Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

Step 2: Extract SPICE Compatible models for each partitioned interconnects by Ansoft Q3D (Differential signals)

Differential line (no GND)

Differential line (with GND)

GND Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

Step 2: Extract SPICE Compatible models for each partitioned interconnects by Ansoft Q3D (Differential Via Holes)

Differential line via1. TCON via2. (with GND) via1

Differential line (no GND) via3 via3

via2

FPC FPC FPC Driver IC Driver IC Driver IC Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

Via Macro-model (type 1)

3 4

1 via1. 2

1 3 2 4 Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

Via Macro-model (type 2)

via2. Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

Step 2: Extract SPICE Compatible models for each partitioned interconnects by Ansoft Q3D (Flexible PCB)

Differential line TCON (with GND) via1

Differential line (no GND) via3 via3

via2

FPC FPC FPC Driver IC Driver IC Driver IC Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

•Line pitch : 0.028mm Differential

•Substrate : polyimide (εr3.5) line •Thickness : 0.038mm

Substrate : polyimide Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

Step 4: Comparison between modeling and measurement

Case1 : Open circuit for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)

TCON Measuring Probes (IBISTCON . spice) Differential line (with GND) via1

Differential line (no GND)

100Ω via2 via3 via2 via3

軟板軟板軟板軟板 open open open open Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

Step 4: Comparison between modeling and measurement

Case1 : Open circuit for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)

0.2

0.15

0.1

0.05

-0.05

-0.1

-0.15 Spice IBIS -0.2 measurement Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

Step 4: Comparison between modeling and measurement

Case2 : Using IBIS model for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)

TCON 訊號觀測點 (IBISTCON . spice) Differential line (with GND) via1

Differential line (no GND)

100Ω via2 via3 via2 via3

軟板軟板軟板軟板 Driver IC Driver DriverDriver IC Driver Driver (IBIS) (IBIS) (IBIS) (IBIS) Case Study: Driver Board of TFT Display NTU -- HSPICE Approach

Step 4: Comparison between modeling and measurement

Case2 : Using IBIS model for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON) NTU Outline

z Introduction

z Signal Integrity Simulation in SPICE A case Study: Driver Board of TFT Display Panel

z TDR Concept and Layer Peeling Technique (one port)

z Macro-model Synthesis for Coupled Discontinuities of Signal Path (two-port)

z Challenge of SI Modeling for Real PCB and Package

z Summary NTU TDR basic theory

Vstep Vr Coaxial cable Time-Domain Reflectometry (TDR) DUT

VTDR

VTDR =VVstep + r

VVTDR =+step Vr =(1 +Γ) ⋅Vstep Γ =−()ZLLZZ00/ ( +Z)

open circuit Γ = 1 2Vstep

2t d cable load circuit Vstep Γ = 0

19 short circuit 0 Γ =−1 NTU TDR theory

Vstep Vr Coaxial cable Time-Domain Reflectometry (TDR) DUT

VTDR

VTDR =VVstep + r

Vstep

Z0 Z0 capacitive dip

C 0

Vstep Z0 Z0 inductive peak L

20 2005/6/18 0 NTU TDR theory

21 Fig. Source: HP TDR NTU Layer Peeling Technique (LPT)

Vt( ) Z Z s I (t) Z1 2 Zi Zi+1 T Td d Td Td x1 x2 x3 xi x Vtin () i+1 − a− a a+ 1, j ij, ij, b− b− b + 1, j ij, ij, a+ −+ ij,1+ aaij+1, = i, j + −−b ++ − ij,1+ +−Zaii−1 ( +=bi) −1 Zi(ai+bi) −+ ZZii− −1 ⎡aabij,,i,1⎤⎡⎡⎤1 −Γ ij⎤ Z 2 2 bbi ij+1, = i, j+1 Γ≡i =⎢1 11⎥⎢=−Γ()1 ⎥ Z0 +−− Z2 − −+i ⎢⎥+ ZZ+ bb a()abii−=−Γ()ai−1bi ii−1,1⎣⎢ ij,,ZZ i⎦⎣⎥⎢⎣⎦i ij⎦⎥ ← Δ→X ii−1

X 1 X 2 X 3 22 Begin NTU Layer Peeling Technique (LPT)

Z0 = 50,i = 1 − − V aa1,j = 1 TDR ⇒ − − Vin bb1,j = 1

− bi,1 1+ Γi Γ=i − Zii= Z −1 ai,1 1−Γi Vt( ) Z Z s I ()t Z1 2 Zi Zi+1 T T T T d d d d ⎡aa+−⎤⎡−1 ⎤ x1 x2 x3 xi x ij,,2 ⎡⎤1 −Γi ij Vtin () i+1 =−Γ1 2 ⎢ +−⎥⎢()i ⎢⎥⎥ − bb−Γ 1 − a + ⎣⎢ ij,,⎦⎣⎥⎢⎣⎦i ij⎦⎥ a ij, a 1, j ij, i=i+1 b− b− b + 1, j ij, ij, − + + a aaij+1,= ij , jNi=1, 2, 3," , − ij,1+ b+ −+ ij,1+ bbij+1,= ij ,+ 1 jNi=1, 2, 3," , −

Z1 Z0 Z2

←ΔX → i=N?

X X X 1 2 3 23 2005/6/18 End NTU Layer Peeling Technique (LPT)

VTDR

110 100 ohm 100 0.3

) 90

hm 80

0.25 O

)

( t

70 ohm

e ol

v 70

( nc

0.2 R

da 60 50 ohm

V m

0.15 I 50 40 ohm

ne 40 0.1 Li 30

0.05 20 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 724 2005/6/18 t (ns) t (ns) NTU Outline

z Introduction

z Signal Integrity Simulation in SPICE A case Study: Driver Board of TFT Display Panel

z TDR Concept and Layer Peeling Technique (one port)

z Macro-model Synthesis for Coupled Discontinuities of Signal Path (two-port)

z Challenge of SI Modeling for Real PCB and Package

z Summary NTU Broadband Macro-Models of Differential Via

IC S G G shorting vias S Through-hole via IC Differential via

2005/6/18 26 NTU Broadband Macro-Models of Differential Via

trace1 trace2 VTDR

Anti-Pad VTDT

Via-Pad Terminatted traces

trace3

trace4 VTDR Port 1 Z0 Z0

M1 Vstep RL = Z0 M V 3 TDT Port 2

27 M 2 RL NTU Step responses and macro-PI model

Step response : a : incident wave bi b : reflected wave m n : stimulative port ytmn ()= i an m : detected port

ymn : step response

Pencil of matrix method i rmn :residues Lmn iii pmn :poles ytmn()=−∑ r mn exp( pt mn ) i=1 Lmn :mode numbers 28 NTU Step responses and macro-PI model

Port 1 Z0 Z0

Lapalace transformation: M1 RL

Lmn i M r 3 ys= mn Port 2 mn ()∑ i M 2 i=1 sp+ mn RL Lmn ri Impulse response: ()ss mn ξmn = ∑ i i=1 s + pmn

⎡⎤(1 +−ξ 1)(1(1 ξξ−+ξ11) +)(1 ξξξ22 ) +( 12(1)(+ξξ21 ))(−1 +2ξξ21 ) −ξξ Ms()= 11 22 12 21 11 22 12 21 ⎢⎥1 Z0 ⎡⎤AB Z0122ξξ21(1 ++ξξ1)(1 22) −()ξ12(ξ21)21 ⎢⎥= ⎢⎥ ⎣⎦CDN i ⎢⎥1 iN(1 −−ξ111)(1 +−iiξξ22 ))(−1ξξ12ξξ21i) +()(1 −ξ(ξ11)N(1)−+ξ2ξ22 ) +ξξi12 *21 0Ms()rr= 1111 22 12 21 21()r M s =+ss⎢⎥2Z 01kk+ ()22ξξ1k+K i ()∑∑⎣⎦02iiZ01(11++ξξ1)(1 22) −i()ξ12∑(ξ21)21iii kk==11ss++αα01kk()jβ1k+k=1s(α1k+jβ1k)− 12⎡ DAξ−−111⎤ Ms[]MM()= M= 21 3 123⎢ 29 ⎥ 2005/6/18 Z01(1 ++ξξ1)(1⎣ BB22) −()ξ12(ξ21)B⎦ NTU Order reduction

i ii N0 rriN11 i N() r i* M ss01kk 1 kK i ()s =++∑∑iiiii+ () ∑ i kk==11ssjsj++++−ααβαβ01kkkkk()()11 k = 11

We define a parameter D for mode selection

D : 0.1% ~ 5% maximum residue

i i N0 rriN1 i Ms 01kk s i ()s =+∑∑ii( i kk==11ssj+++α01kk()αβ1k ii rD01kk≥≥rD

i Ni1 * ()r1k ++∑ ii)Ki k=1 sj+−()αβ11kk i rD1k ≥ 30 2005/6/18 NTU Passivity criterion

PVIVYV==≥Re{ ** }Re{ } 0

−Y M3 12

YY+ YY+ M1 M 2 11 12 22 12

YMM11=+ 1 3 ⎡⎤YY11 12 ⎡MM 13+− M 3⎤ YY==−⎡⎤Mj13()ωω M+− MjY == () ω Mj 3 () eigen{12Re ⎢⎥ 21 3 ⎢⎥YY ⎢ −+M MM} ≥ 0⎥ −+Mj()ωωω⎣⎦21 Mj 22 ()⎣ Mj323 () ⎦ YMM22=+⎣⎦ 2 3 323 31 2005/6/18 Systematic lumped-model extraction technique NTU (SLET)

i ii N0 rriN11 i Ni() r* M ss01kk 1 kK i ()s =+∑∑ii()ii + ∑ i +i kk==11ssjsj++++−ααβαβ01111kk()kk k = 1 ()k ii i rD01kk≥≥rD rD1k ≥

K0 qrsvPsK1 + () M ()ssii s i K ii=+∑∑2 ++ ii==11sh+++ii s usmQsi() qvii>>00

KK12= ==1/ Z 0 K 3 0

32 Systematic lumped-model extraction technique NTU (SLET)

K0 q K1 rvsPs+ () M ()ssi s ii K ii=+∑∑2 ++ ii==11sss+++hi ui mi Qs() qvii>>00 v C = i i m R i Ci 1 ⎛⎞ri RCi =−⎜⎟ui vi Ci Ci ⎝⎠ R 1 Ci 1 RR=− Li r Ci R i 1 Ci R ⋅r Ys= R L Li i R = 1 Li i L = C Ci s +q i Cm⋅ i iRC ii 1 Ci i C = i h R sL C + C R i Ci ii iLi Ys= 33 2005/6/18 s2 ()RLC++RLC s(RRC+L)+R Liiii Cii iC L iii Li Systematic lumped-model extraction technique NTU (SLET)

Ps() K2 q K3 rv s+ ssi ii K =+∑∑2 +i Qs() ii==11 s+++hi sui s mi qvii<<00

RL + Vs() − i +− Vs() Ci Ci L RC Ci RC C i 2()Vs i i Ci 2()Vs Ci + Vs() − Li 2()Vs Li

1 −vi 1 RCi = CRiL==i−RCi qi mrii −1 1 ⎛⎞rRiLi⋅ri Ci = Ru=+ L= hR Ci ⎜⎟i i iCi vCii Ci⋅mi 34 ⎝⎠ Port 1 Z0 Z0 Port 3 NTU M C Vstep 1 RL

M3 Port 2 Port 4

M 2

−

+ M 3

−

+ −

+ Vs() C +

− - Vs+ C () -

−

+ + - - −

+ 2()VsC

+ +

2()VsC VsL ()

M1 - - − +

2()Vs− L +

−

+ 35

M 2 TDR or FDTD NTU Flow chart

i bm ytmn ()= i an Lmn ii ytmn ()=−∑ rmn exp( ptmn ) i=1

Port 1 Z0 Z0

M1 RL i ii N0 rriN11 i Ni() r* 01kkM3 1 k M i ()s = ss∑∑ii+++()ii ∑ iK Port 2 kk==11ssjsj++++−ααβαβ01kk()11kk k = 1 ()1k ii i 1 (1−++ξ11 )(1ξξξξ 22 ) rD01kk≥≥() 12( 21rD) −2 21 rD 1k ≥ M 2 Ms1 ()= RL Z (1++−ξξξξ )(1⎡⎤ )Mj()()()ωω+− Mj () ω Mj () 0112eigen{Re2113221 3 }≥ 0 ⎢⎥ ⎣⎦−+Mj323()ωωω Mj () Mj () 1 (1+−+ξ11 )(1ξξξξ 22 ) ()() 12 21 −2 21 Ms2 ()= Z01(1++−ξξξξ12 )(121 ) ()()221

12ξ21 Ms3 ()= Z011221221(1++−ξξξξ )(1 ) ()()

36 NTU Example: asymmetric vias

Transmission line 50 Ohm S = 3 mil Port 1 Port 2

GND Coupling Vias

R L ε r = 4.3 R L

Port 3 Port 4

Port 1 Z0 Z0

M1 RL

M3 Port 2

M 2 RL 37 NTU Eigen-values profile of asymmetric vias

⎡⎤Mj()ωω+− Mj () ω Mj () eigen{Re 13 3 }≥ 0 ⎢⎥ ⎣⎦−+Mj323()ωωω Mj () Mj ()

0.05

asymmetric vias £f1

0.04 £f2

l a

v 0.03

i E

0.02

0.01 0.1 1 38 10 GHz NTU Stability

i i N0 rriN1 i Ms 01kk s i ()s =+∑∑iii( kk==11ssj+++α01kkk()αβ1 ii

rD01kk≥≥rD −

+ M i 3

Ni1 *

()r −

+ −

++) Ki ∑ ii + k sj+−()αβ =1 11kk −

i + rD1k ≥ −

−

M2 39 2005/6/18 Transmission line 50 Ohm S = 3 mil Port 1 Port 2

GND Coupling Vias

R L ε r = 4.3 R L NTU Time-domain response – V11 Port 3 Port 4

i ii N0 rriN11 i Ni() r* M ss01kk 1 kK i ()s =+∑∑ii()ii + ∑ i +i kk==11ssjsj++++−ααβαβ01111kk()kk k = 1 ()k ii i rD01kk≥≥rD rD1k ≥

0.25

0.2

)

o v

( 0.15

1 V 0.1

3D-FDTD 0.05 extracted model mode 54 extracted model mode 44

0 0 10 20 30 4040 50 60 70 80 t (ps) Transmission line 50 Ohm S = 3 mil Port 1 Port 2

GND Coupling Vias

R L ε r = 4.3 R L NTU Time-domain response – V12 &Port V 3 22 Port 4

i ii N0 rriN11 i Ni() r* M ss01kk 1 kK i ()s =+∑∑ii()ii + ∑ i +i kk==11ssjsj++++−ααβαβ01111kk()kk k = 1 ()k ii i rD01kk≥≥rD rD1k ≥

0.035

0.25

0.025

V 1

0.2 2

) &

t 0.015

v 2

( 0.15

(

2 v

0.005 o

V l

0.1 t )

3D-FDTD -0.005 0.05 extracted model mode 54 extracted model mode 44

0 -0.015 0 10 20 30 4041 50 60 70 80 t (ps) Transmission line 50 Ohm S = 3 mil Port 1 Port 2

GND Coupling Vias

R L ε r = 4.3 R L

NTU Port 3 Port 4 Frequency-domain response - S11 & S21

0 200

-10 150

100 -20

) 50 g

B) -30

(

( 0

1 1

-40 1 S S -50 -50 -100 3D-FDTD S11 3D-FDTD S11 extracted model mode 54 extracted model mode 54 -60 -150 extracted model mode 44 extracted model mode 44

-70 -200 0 5 10 15 20 25 30 0 5 10 15 20 25 30 GHz GHz 0 200

-10 150

-20 100

-30 ) 50

(

-40 ( 0

2 S -50 S -50

-60 3D-FDTD S21 -100 extracted model mode 54 3D-FDTD S21 -70 extracted model mode 44 -150 extracted model mode 54 extracted model mode 44 42 -80 -200 0 5 10 15 20 25 30 0 5 10 15 20 25 30 GHz GHz Transmission line 50 Ohm S = 3 mil Port 1 Port 2

GND Coupling Vias

R L ε r = 4.3 R L

NTU Port 3 Port 4 Frequency-domain response - S31 & S22

5 200

150 0 3D-FDTD S31 100 extracted model mode 54 extracted model mode 44

) 50

-5 g

( (

3 S -10 S -50

3D-FDTD S31 -100 -15 extracted model mode 54 extracted model mode 44 -150

-20 -200 0 5 10 15 20 25 30 0 5 10 15 20 25 30 GHz GHz 0 200

-10 150

100 -20

) 50 g

B) -30

(

( 0

2 2

-40 2 S S -50 -50 -100 3D-FDTD S22 3D-FDTD S22 extracted model mode 54 -60 extracted model mode 54 extracted model mode 44 -150 extracted model mode 44 43 -70 -200 0 5 10 15 20 25 30 0 5 10 15 20 25 30 GHz GHz NTU Example: Differential via

Transmission line 50 Ohm S = 3 mil Port 1 Port 2

GND Differential Vias

GND R R L ε r = 4.3 L Port 3 Port 4

Port 1 Z0 Z0

M1 RL

M3 Port 2

M1 RL 44 NTU Eigen-values profile of differential vias

⎡⎤Mj()ωω+− Mj () ω Mj () eigen{Re 13 3 }≥ 0 ⎢⎥ ⎣⎦−+Mj323()ωωω Mj () Mj () 0.05

0.045 Differential via £f1 £f2

0.04

l a

v 0.035

g i E 0.03

0.025

0.02 0.1 1 45 10 GHz NTU Time-domain response – V11 & V21

0.04

0.25 0.03

V 1

0.2 0.02 2

)

v 2

( 0.15 0.01

(

V l

0.1 0 t )

0.05 3D-FDTD -0.01 extracted model

0 -0.02 0 10 20 30 40 50 60 70 80 46 t (ps) NTU Frequency-domain response - S11 & S21

10 200

0 150 3D-FDTD S11 -10 100 extracted model

-20 ) 50

(

-30 ( 0

1 S -40 S -50

-50 -100 3D-FDTD S11 -60 extracted model S11 -150

-70 -200 0 5 10 15 20 25 30 0 5 10 15 20 25 30 GHz GHz 0 200

-10 150 3D-FDTD S21 extracted model -20 100

-30 ) 50

(

-40 ( 0

2 S -50 S -50

-60 -100 3D-FDTD S21 -70 extracted model S21 -150 47 -80 -200 0 5 10 15 20 25 30 0 5 10 15 20 25 30 GHz GHz NTU Frequency-domain response - S31 & S41

5 200

150 0 100

-5 ) 50

(

( 0

3 3

S -10 S -50

-100 -15 3D-FDTD S31 extracted model S31 3D-FDTD S31 -150 extracted model

-20 -200 0 5 10 15 20 25 30 0 5 10 15 20 25 30 GHz GHz 0 200

-10 150

-20 100

-30

) 50

( d -40

( 0

4 S

-50 S -50

-60 -100 3D-FDTD S41 3D-FDTD S41 extracted model S41 -70 -150 extracted model 48 2005/6/18 -80 -200 0 5 10 15 20 25 30 0 5 10 15 20 25 30 GHz GHz NTU Outline

z Introduction

z Signal Integrity Simulation in SPICE A case Study: Driver Board of TFT Display Panel

z TDR Concept and Layer Peeling Technique (one port)

z Macro-model Synthesis for Coupled Discontinuities of Signal Path (two-port)

z Challenge of SI Modeling for Real PCB and Package

z Summary NTU Challenge of Modeling the Real PCB and Package

4-layer Motherboard for Desktop Computer (PCB) NTU Challenges for Modeling the Real PCB and Package

4-layer Motherboard for Desktop Computer (PCB)

Bottom side

Top side NTU Challenges for Modeling the Real PCB and Package

4-layer BGA Package, 37.5mm × 37.5mm, 788 pin balls

Power Layer (layer 3)

Ground Layer (layer 2) NTU Challenges for Modeling the Real PCB and Package

Real PCB and Packages

1. Several thousands traces routed on a PCB. 2. Several thousand through hole vias 3. Perforated power and ground planes 4. Irregular power/ground planes partitions.

In SI simulation, we need to think

How accurate you need? How complicated your circuits are? How much (computing) resources you have? NTU Challenges for Modeling the Real PCB and Package

Material Characteristics:

1. Substrate: Broadband information of dielectric constant and loss tangent.

2. Conductor: frequency dependent loss (skin effect)

εε( ffjf)=−''( ) ε'( ) Challenges for Modeling the Real PCB and Package in High-speed NTU Circuits

Signal Propagation Characteristics:

1. Signal line referred to the perforated power or ground planes.

2. Broadband single (differential) via models Challenges for Modeling the Real PCB and Package in High-speed NTU Circuits

Power distribution networks characteristics

Challenges: (how accurate?) • Power/ground ring with shorting vias • Thousands of via holes on power/ground planes • Vertical interconnects modeling and linking between package and PCB • Mutual coupling between package and PCB Challenges for Modeling the Real PCB and Package in High-speed NTU Circuits

IBIS Model for Power Noise modeling

IIIIIVDD≅ sig+++ shot pd() clamp

IVDD I are considered in IBIS model I sig pd (pull up and pull down current) Isig Power Pre-drive Network Circuits

The pre-drive current Ipd and shot-through Ishot current Ishot are not considered in IBIS model Challenges for Modeling the Real PCB and Package in High- NTU speed Circuits IBIS Model for SSN modeling Pre-drive current

Pull up current NTU Summary

z As an example, a driver PCB for TFT display panel is modeled by two approaches. One is using commercial SI design tool, and the other is based on the HSPICE environment by constructing equivalent SPICE-compatible models.

z TDR concept and layer peeing technique for extracting equivalent circuit models is introduced based on time domain response.

z A synthesis approach for macro equivalent circuit model for coupled discontinuity is also discussed.

z Challenges for SI design tool in modeling the real PCB and package in high- speed circuits are discussed. They includes material characteristics, signal propagation characteristics, power distribution networks, and IBIS model for SSN.