ECE 570 Session 11 – Part 1 IC 752-E Computer Aided Engineering for Integrated Circuits

Signal Integrity Issues

Objective: Define basic problems in signal integrity

Outline: 1. Introduction 2. Signal integrity issues in digital systems 3. Signal delay and delay equations 4. Effects of noises 5. Performance metrics

1 1. Introduction

Technology Trends and Signal Integrity

Device parameters • reduced: channel length, gate oxide thickness • reduced gate delay ⇒ increased role of interconnects • faster devices, shorter rise time ⇒ more internal noises

On-chip interconnects • increased line resist. ⇒ increased wire delays • tighter metal pitch ⇒ increased line coupling ⇒ increased cross-talk • increased number of metal layers ⇒ complex simulation • increased wire delay sensitivity to activities on neighboring lines • electromigration ⇒ decreased reliability

Power supply

• low supply voltage ⇒ reduced noise margines ⇒ incr. sensitivity to parasitics.

2

2. Signal Integrity issues in digital systems

Phenomena in signal transmission

• attenuationU| • dispersion V − interconnect properties •−cross talkW| •−reflections termination properties,.disc

•−coupling via pwr / gnd interconnect / grounding properties •−int erference package / cabinet properties

Representative quantities

•=signal delay ; TpD Tclk TpD +TIL +Tskew • ""noise representation • receiver noise sensistivity

3

Important and complex problem - modeling:

relating the quantities of interest such as delay and noise to design variables:

• interconnect geometries • interconnect and grounding structure • cabinet properties • material properties • circuit and layout design • driver/receiver properties • packaging and board technologies

4 3. Signal delay and delay equations

Signal delay may be determined using transmission line models as shown before. However, transmission line analysis provides only one component to a delay.

There are two other components:

a) delay contribution due to discontinuities, loads, and terminations, b) delay contribution caused by activities on the coupling lines.

The first component is deterministic in nature and can be estimated using simulation of interconnects. The simulation results can be stored in the form of look-up tables and used to calculate delay equations needed in design for signal integrity.

The second component varies randomly, as it depends on activities on neighboring lines and its statistical model can be predicted using extensive simulation of transients in interconnecting structures.

5 4. Effects of noises

digital circuits and systems

logic errors, false switching varying delay clock jitter timing design must include margins for noise analog circuits and systems

phase errors distortion reduction of accuracy mixed-signal circuits and systems

glitches in digital-to-analog converters reduction of SNR and SFDR in conversion

6 5. Performance metrics – examples

digital circuits and systems

signal delay maximum attainable clock frequency composite noise level noise reserve: noise level noise margin < tolerance > analog circuits and systems (operational amplifiers)

open-loop gain transfer characteristic input impedance output impedance cut-off frequency ( the unity gain bandwidth)

7 Common Mode Rejection Ratio offset, drift slew rate full-power bandwidth SNR - signal to noise power ratio over the bandwidth of interest

Analog circuits in communication applications: filters, mixers, low noise amplifiers, power amplifiers signal generators

8

Performance of mixed-signal circuits - signal converters

Definition of Signal to Noise Ratio (SNR) for analog-to-digital converter (ADC) variance of input signal F σ 2 I SNR = 10logF I = 10log signal AD/ HG variance of A / D quntization noise KJ G σ 2 J H A/D noise K

To show the effect of input signal amplitude it is convenient to introduce a loading factor, LF, as a ratio of signal standard deviation to nominal peak- to-peak input voltage, Vp , defined as follows

F σ I LF = G signal J H Vp K .

9

Elementary algebra applied to the signal standard deviation yields

F σ I σ = signal V signal G V J p H p K LF Introducing the loading factor into the expression for SNR results in

2 2 FbLFg Vp I SNR = 10log AD/ G 2 J σ . H A / D noise K

Actually measured SNR of a converter is usually lower due to converter imperfections and noises.

The measured level of signal-to-noise ratio, designated by SINAD (Signal to Noise And Distortion ratio) is a metric of converter performance reflecting the effects of noises.

10 Another metric called Effective Number Of Bits (ENOB) is useful to depict the effect of noises on converter performance.

Toward this end we introduce a fictitious, ideal converter with such a number of bits, Neff , that its theoretical SNR matches the measured SINAD. The formula for the effective number of bits is SINAD −17. 6 ENOB = 60. 2 The Spurious Free Dynamic Range (SFDR) is defined as follows:

SFDR = SNRAD/ − SPNR where (SPNR) is the Spur-to-Noise Ratio.

11 Spurious signals may be generated due to improper sampling time caused by noises (clock jitter). The Spur-to-Noise Ratio (SPNR) is defined as follows

F σ 2 I SPNR = log SP G σ 2 J . H A/D noise K

σ 2 where A/D noise is the variance of uncorrelated converter noise and 2 σ SP is the variance of spurious signals.

12