3-D System Integration of Processor and Multi-Stacked Srams Using

856 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link Makoto Saen, Kenichi Osada, Member, IEEE, Yasuyuki Okuma, Kiichi Niitsu, Member, IEEE, Yasuhisa Shimazaki, Member, IEEE, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Member, IEEE, Atsushi Hasegawa, and Tadahiro Kuroda, Fellow, IEEE

Abstract—This paper describes a three-dimensional (3-D) and wireless) have been proposed [1]–[10]. A major wired-in- system integration of a full-fledged processor chip and two terconnect technique is through-silicon via (TSV) [6]–[10]. The memory chips using inductive coupling. To attain a 3-D commu- density of 3-D inter-chip connections can near that of on-chip nication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation wires when using the TSV technique. However, it increases due to unused inductors are important challenges. Therefore, cost of chip fabrication due to increase of fabrication-process we developed a new 3D-integrated wire-penetrated multi-layer complexity. On the other hand, inductive coupling [1]–[4], a structure for a shorter link distance and an open-skipped-inductor major wireless-interconnect technique, does not increase the scheme for suppressing signal degradation. In addition, to avoid process complexity because inductors for inductive coupling undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control are formed using metal layers of standard CMOS process. scheme with a pinpoint-data-capture scheme. We demonstrate Therefore, inductive coupling is an inexpensive 3D-integra- that three fabricated chips can be successfully AC-coupled using tion solution. An inductive-coupling link for high-bandwidth inductive coupling. The power and area efficiency of the link are P between one processor chip and one memory chip was reported 1 pJ/b and 0.15 mm Gbps, respectively, which are the same as [2]. Their work shows that an inductive coupling link can con- those of two-chip integration. nect a processor chip and a memory chip with high-bandwidth. Index Terms—Inductive coupling, three-dimensional system In addition to the increase in bandwidth, increase in memory integration. capacity is also necessary to improve performance of processor systems. Our technical challenge is to achieve large memory ca- I. INTRODUCTION pacity using the inductive-coupling link [1]. The simple and effective solution for this purpose is to stack multiple same-sized memory chips on a processor chip. However, there are two is- HE processing performance of processor chips continues sues to address. The first is to develop 3D-stacking technology T to increase by integrating more processing cores in a to attain a shorter link distance for a smaller area and lower chip, from dual core to many core. To improve the performance power consumption of interconnect circuits. The second issue for practical applications, inter-chip bandwidth between a is to prevent signal degradation due to unused inductors. processor chip and a memory chip and memory capacity must We developed 3-D system integration techniques as solutions be also increased. to these issues. For the first issue, we developed a new 3D-in- In improving inter-chip bandwidth with conventional tegrated wire-penetrating multi-layer structure. For the second system-on-a-board implementation, long inter-chip distance issue, we developed an open-skipped-inductor scheme. In the and limited number of interconnections prevent improvement following sections, we discuss these techniques and also de- in inter-chip bandwidth. Three-dimensional (3-D) integration scribe a proposed memory-access-control scheme with a pin- is recognized as a breakthrough technology for improving the point-data-capture scheme for avoiding undefined-value propa- interconnect bandwidth. It reduces the inter-chip distance and gation in stacking multi-memories using the inductive-coupling increases the number of interconnections dynamically by ver- link. tical stacking. Several 3-D interconnection techniques (wired

II. 3D INTEGRATION WITH INDUCTIVE-COUPLING Manuscript received August 24, 2009; revised November 16, 2009. Current LINKS AND WIRES version published March 24, 2010. This paper was approved by Guest Editor Masayuki Mizuno. M. Saen, K. Osada, Y. Okuma, and N. Irie are with the Central Research Lab- A. System Overview oratory, Hitachi, Ltd., Kokubunji-shi, Tokyo 185-8601, Japan (e-mail: makoto. [email protected]). In this section, we explain our 3-D integrated system. In this K. Niitsu, Y. Shimazaki, Y. Sugimori, Y. Kohama, K. Kasuga, and T. Kuroda system, a full-ﬂedged processor chip [11] and two memory are with Keio University, Yokohama, Kanagawa 223-8522, Japan. chips (SRAM0/1) are stacked, and they are connected using Y. Shimazaki, I. Nonomura, T. Hattori, and A. Hasegawa are with Renesas Technology Corporation, Kodaira-shi, Tokyo 187-8588, Japan. inductive coupling. The processor accesses stacked memories Digital Object Identiﬁer 10.1109/JSSC.2010.2040310 via the inductive-coupling links.

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Fig. 1. Block diagram of 3D-system.

Fig. 3. 3D-integration with wire-penetrated multi-layer structure.

on the SRAM0 chip. Each chip is back grinded to a thickness of m for a shorter link distance. The data are vertically transmitted using the inductive-coupling links among the chips. On the other hand, the power for the SRAM0 and SRAM1 chips is supplied using conventional low-cost wire bonding. Although inductive coupling can supply power, it is inferior to wire in transmission efficiency. Such 3D-integration with hybrid connections makes integra- Fig. 2. Micrographs of chips and risks of 3D-integration. tion difficult. To attain a shorter link distance, two points need to be improved. One is to reduce the space for wire bonding as much as possible while avoiding a short between the SRAM0 A block diagram of the system is shown in Fig. 1. The wire and the back-side of the SRAM1 chip (short risk A in processor chip includes eight processor-cores (PUs), a control Fig. 2), or a short between the SRAM0 wire and the edge of circuit of inductive-coupling connection (ICCP), an on-chip in- the SRAM0 chip (short risk B in Fig. 2). The other point is to terconnect (OCIC), which is a switch fabric connecting the PUs apply wire bonding to the very thin SRAM1 chip without any to the ICCP, a transmitter circuit (Txp), a receiver circuit (Rxp), cracks (crack risk in Fig. 2). To achieve this bonding, it is neces- and inductors. Each memory chip includes a 1-MB SRAM sary to fill the narrow space with glue without any gaps despite array, a control circuit of an inductive-coupling link (ICC0/1), the existence of wire bonding. To satisfy both points, we devel- a transmitter circuit (Tx0/1), a receiver circuit (Rx0/1), and oped a new structure. inductors. An overview of the new structure is shown in Fig. 3. This The inductive-coupling links are classified into an uplink structure is based on two techniques. One is a wire-shaped con- from the processor to the memories and a downlink from the trol technique for reducing the space between stacked chips memories to the processor. The links use a source-synchronous without any shorts. A key to the wire control is to place ad- method, sourcing a clock along with data. Each link contains a ditional shaping plates on the package board. By using these 600-MHz clock signal, 16-bit data signals, and control signals. shaping plates, we can change the direction of the wire and control the wire shape. The other technique is a wire-penetra- B. 3D-Integrated Wire-Penetrated Multi-Layer Structure tion-into-glue technique for filling the space without any gaps. Microphotographs of the fabricated chips are shown in Fig. 2. This is achieved by applying a special glue, Hitachi-Chemical The processor chip is fabricated in a 90-nm-CMOS process and glue (HS series), in which the wires penetrate. A 40- m-thick the memory chips are fabricated in a 60-nm-CMOS process. A space is achieved using these techniques. good feature of 3-D integration is that chips fabricated in dif- The process flow of the wire-penetration-into-glue is de- ferent processes can be integrated. scribed. First, the SRAM0 chip is glued on the processor chip A side view of 3-D integration by stacking the chips is also which is mounted on the package board. Next, wire bonding for shown in Fig. 2. The processor chip is mounted face down on a the SRAM0 is made with the shaping plates. In addition, the package board using C4 bumps. The SRAM0 chip is glued face special glue is attached to the back side of the SRAM1. Then, up on the processor chip, and the SRAM1 chip is glued face up the SRAM1 is stacked on the SRAM0 and they are heated with

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TABLE I DEGRADATION OF SIGNAL STRENGTH BY UNUSED INDUCTOR

a pressure. In this process, wires penetrate the glue. After that, this integrated module is cured. Finally, wire bonding for the SRAM1 is made. As described above, this process flow does not include technical difficulties, so the wire-penetration-into-glue is manufacturable. Micrographs of the new structure are shown in Fig. 3. The processor, the SRAM0, and SRAM1 chips are stacked vertically. The shaping plate for controlling the wire shapes is placed Fig. 4. Receiver and transmitter circuit with open-skipped-inductor scheme. on the package board. This micrograph shows that wires for (a) Receiver circuit Rx0/1 of SRAM 0/1. (b) Transmitter circuit Tx0/1 of the SRAM0 chip successfully penetrate into the 40- m-thick SRAM 0/1. glue; the wires are bonded without any shorts, and the wires for the SRAM1 chip are successfully bonded to the very thin chip without any cracks. the unused (skipped) inductor is opened to suppress the in- As described above, we succeeded in stacking 50- m-thick ductive current in it. When the SRAM0 chip is unselected in chips while supplying power by wire bonding at low cost. The the uplink, the receiver circuit in the SRAM0, Rx0, is opened. achieved link distance between the processor chip and the upper When the SRAM0 chip is unselected in the downlink, the SRAM1 chip is m. transmitter circuit in the SRAM0 transmitter, Tx0, is opened. A receiver circuit (Rx0/1) and a transmitter circuit (Tx0/1) III. OPEN-SKIPPED-INDUCTOR SCHEME are shown in Figs. 4(a) and 4(b), respectively. The receiver circuit uses a current-sense circuit for low power consumption and A. Signal Degradation by Unused Inductors receives transmitted data at rising edges of a receiver-enable In this section, we describe the second issue, signal degra- signal (Rx0_en or Rx1_en) [3]. For the open-skipped-inductor dation by unused inductors. When three chips are stacked and scheme, the receiver circuit has a bias control signal (B0_en communication occurs between two of these chips, there are un- or B1_en). By disabling this signal, an inductor connected to used inductors in the chip that do not join the communication. the receiver circuit is opened. On the other hand, the transmitter For example, in the uplink from the processor transmitter (Txp) circuit flows current into its inductor by applying a pulse on a to the SRAM0 receiver (Rx0), the inductive currents flow not transmitter-enable signal (Tx0_en or Tx1_en). The transmitter only through the inductors of Rx0, but also through the unused circuit opens its inductor by maintaining the transmitter-enable inductors of Rx1 in the SRAM1 chip. The currents in Rx1 de- signal (Tx0_en or Tx1_en) at a low level. crease the signal strength of the uplink. Fig. 5 shows a timing diagram of the uplink communication. Simulation results on the signal degradation are listed in A transmission from the processor to the SRAM0 chip is de- Table I. In case 1, in which a processor chip and a memory chip scribed below. The transmission begins by activating Txp_en, were stacked, there were no unused inductors causing signal by which the signal current is flowed into the inductors degradation. In case 2, two memory chips were stacked on a of the processor transmitter. induces the inductive current processor chip and there were unused inductors causing signal in the inductor of the SRAM0 chip and the inductive cur- degradation. The signal degradation increases as link distance rent in the opened inductor of the SRAM1 chip. How- increases. In particular, in the uplink from the processor trans- ever, with our proposed scheme, is suppressed to such a mitter to the SRAM1 receiver, the link strength degraded by up low level that the current is only minimally degraded. to 10.8%, even though the strength is at its lowest. does not become 0 because of parasitic capacitances. Then, is amplified by the pulse on Rx0_en. To obtain correct data, B. Open-Skipped-Inductor Scheme the pulse of Rx0/1_en must also be inserted in a narrow timing To reduce signal degradation, we propose a new open- margin. Therefore, it is designed that the timing of Rx0/1_en is skipped-inductor scheme. The concept of this scheme is that adjustable [2].

The open-skipped-inductor scheme is more effective as more SRAM chips are stacked in the same distance. Fig. 6(b) plots improvement in link strength when the communication distance is 210- m. For example, when four SRAM chips are stacked, the strength of the inductive-coupling link improves by 25%. This means that our developed circuit scheme will be more effective in future 3-D integration where thinner chips will be stacked.

IV. MEMORY-ACCESS-CONTROL SCHEME FOR STACKING MULTI-MEMORIES A memory-access-control scheme for stacking memories on a processor is discussed in this section. In simple implementation of such multi-memory-stacked systems (including our system), stacked-memories share the downlink (clock and data). In order to avoid collisions on the downlink, each memory chip sends clock and data to the downlink only during response of read data and does not output these the rest of the time. As a result, there are time periods when values on the downlink are undefined. Propagation of the undefined value may cause a fatal error in the processor chip. This problem does not occur in single-memory Fig. 5. Timing diagram of uplink communication with open-skipped-inductor stacked and conventional wire-linked systems. For conventional scheme. wired links, an effective circuit method for avoiding such undefined-value propagation has been established [12]. Wired links are pulled-up (or down) with high-resistance connection, and the links are always in defined-value even when no transmitter outputs valid signal. Unfortunately, the inductive-coupling link is difficult to continue to output constant signals because the link communicates with narrow pulses induced by change in the current on the transmitter’s inductor. For this problem, we propose a pinpoint-data-capture scheme. Data from the inductive-coupling link are obtained only at calculated capture timing. This scheme enables the removal of undefined-data caused by opened inductors. Next, we describe a circuit for the pinpoint data capture scheme. Fig. 7 shows a block diagram of the ICCP. The ICCP consists of the pinpoint-data-capture circuit, a request controller circuit for issuing memory-access requests, a buffer circuit for buffering data from Rxp (RSBF), and an interface-control circuit for connecting the ICCP to the OCIC (ICRSC). The pinpoint-data-capture circuit has a timing generator, which generates the capture timing of read-data with two counters (a response-latency counter and a capture-number counter) and asserts a capture-trigger signal at the timing. The response-la- Fig. 6. Increase in link strength using open-skipped-inductor scheme. (a) Number of stacked memories: 2. (b) Number of stacked memories: 2 to 4. tency counter is set to the number of clock cycles between the read request and the first cell of read-data. In the other hand, the capture-number counter is set to read-data size divided by We evaluated how much the open-skipped-inductor scheme width of captured read data in the pinpoint-data-capture circuit increases the strength of the links. Fig. 6(a) shows simulated (32 bit for the case in Fig. 7). For example of 8-byte read, the results when two memories are stacked on the processor chip capture-number is 2 (64 bit/32 bit). (shown in Fig. 3). Differences in signal strength between up- An example of a timing diagram is also shown in Fig. 7. In links and downlinks are caused by differences in circuit charac- this case, the ICCP receives 8-byte read-data. There are time pe- teristics between the processor chip and the SRAM chips, which riods when values on downlink signals are undefined. The pin- chips are fabricated in different process (90 nm-CMOS for the point-data-capture circuit sets the response-latency and capture- processor chip and 65 nm-CMOS for the SRAM chips). In the number to the two counters, respectively, when memory-access uplink from the processor chip to the SRAM1 chip, the link requests are issued. Then, the values in the counters are counted strength increased by 5.5%. This scheme makes it possible to down and the capture-trigger signal is asserted based on values communicate among three chips using inductors with a 240- m of the counters. By introducing the circuit, the processor chip radius. receives only valid-data and discards undefined-data.

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TABLE II PERFORMANCE SUMMARY

The performance results of our developed 3-D integration system are summarized in Table II. The total layout area for the inductive-coupling link is mm , and the total bandwidth is 19.2 Gbps. The Power consumption and area efﬁciency of the link are 1 pJ/b and mm , respectively, which are the same as those of two-chip integration [2].

VI. CONCLUSIONS We presented a 3-D system integration of a fully functional processor chip and two memory chips using inductive coupling. To attain a shorter link distance for a smaller area and Fig. 7. Block diagram of ICCP and timing diagram of memory-access-control. lower power consumption, a new 3D-integrated wire-penetrating multi-layer structure was developed. The thickness of the inter-chip space was reduced to 40- m by applying the wire-penetration-into-glue technique while supplying power by wire bonding at low cost. In addition, to prevent signal degradation due to unused inductors, we developed an open-skipped-inductor scheme. The scheme improves signal strength degraded by unused inductors from 5.5% to 25%. In addition, to avoid error due to undeﬁned-value propagation, we proposed a memory-access-control scheme with a pinpoint-data-capture. In demonstrations, three fabricated chips were successfully connected by inductive coupling. Our demonstration was the ﬁrst one of inductive-coupling links Fig. 8. Measurement results of timing margins of each link. among a processor and multiple memory chips.

V. E XPERIMENTAL RESULTS AND PERFORMANCE ACKNOWLEDGMENT SUMMARY OF SYSTEM The authors thank Mike Razo at UMASS Amherst for his We evaluated timing margins of the inductive-coupling effort in establishing the measurement system. links by measuring our developed 3-D integration system. The measurement results are shown in Fig. 8. The margin of links REFERENCES between the processor and SRAM1 chips is smaller than that [1] K. Osada et al., “3D system integration of processor and multi-stacked between the processor and SRAM0 chips. The difference in SRAMs by using inductive-coupling links,” in Symp. VLSI Circuits margins comes from the difference in the distance between Dig. Tech. Papers, May 2009, pp. 171–182. the chips. The margin of the downlink (4) from the SRAM1 [2] K. Niitsu et al., “An inductive-coupling link for 3-D integration of a 90 nm CMOS processor and a 65 nm CMOS SRAM,” in IEEE ISSCC chip to the processor is 27% smaller than that of the downlink Dig. Tech. Papers, Feb. 2009, pp. 480–481. (3) from the SRAM0 chip to the processor. However, timing [3] N. Miura et al., “A 1 Tb/s 3 W inductive-coupling transceiver for margins were discussed [2] and, according to this discussion, 3D-stacked inter-chip clock and data link,” IEEE J. Solid-State Cir- the margins of our system are sufﬁcient for the links. Thus, cuits, vol. 42, no. 1, pp. 111–122, Jan. 2007. [4] Y. Sugimori et al., “A 2 Gb/s 15 pJ/b/chip inductive-coupling pro- the three chips are successfully AC-coupled by the inductive grammable bus for NAND ﬂash memory stacking,” in IEEE ISSCC coupling. Dig. Tech. Papers, Feb. 2009, pp. 244–245.

[5] A. Fazzi et al., “3D capacitive interconnections with mono- and bidi- Kiichi Niitsu (S’06–M’10) was born in Japan in rectional capabilities,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, 1983. He received the B.S. degree summa cum pp. 356–357. laude and the M.S. and Ph.D. degrees in electrical [6] K. Takahashi et al., “Through silicon via and 3-D wafer/chip stacking engineering from Keio University, Yokohama, Japan, technology,” in Symp. VLSI Circuits Conf. Dig. Tech. Papers, Jun. 2006, in 2006, 2008, and 2010, respectively. pp. 114–117. He is currently an Assistant Professor at Gunma [7] H. Yoshikawa et al., “Chip-scale camera module (CSCM) using University, Kiryu, Japan. Since 2005, he was engaged through-silicon-via (TSV),” in IEEE ISSCC Dig. Tech. Papers, Feb. in a research on the low-power circuit design in the 2009, pp. 476–477. inductive-coupling inter-chip interface for high-per- [8] U. kang et al., “8 Gb 3-D DDR3 DRAM using through-silicon-via tech- formance, low-power 3-D system integration and the high-speed yet low-power circuit design for short- nology,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 130–131. range inter-chip communication. His current research interests are in the low- [9] N. Miyakawa, “A 3-D prototyping chip based on a wafer-level stacking power and high-speed technologies for analog and mixed-signal VLSI circuits. technology,” in Proc. ASP-DAC, Feb. 2009, pp. 416–420. From 2008 to 2010, Dr. Niitsu was a Research Fellow of the Japan Society [10] M. Koyanagi et al., “Future system-on-silicon LSI chips,” IEEE Micro, for the Promotion of Science (JSPS), a Research Assistant of the Global Center vol. 18, no. 4, pp. 17–22, 1998. of Excellence (GCOE) Program at Keio University and a Collaboration Re- [11] M. Ito et al., “An 8640 MIPS SoC with independent power-off control searcher of the Keio Advanced Research Center (KARC). In 2007, he was with of 8 CPUs and 8 RAMs by an automatic parallelizing compiler,” in Renesas Technology Corporation studying circuit design of inter-chip inter- IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 90–91. face for low-power VLSI circuits. He received the 2006 excellent graduation [12] Sh7785 Hardware Manual, Renesas Technology Corp. [Online]. Avail- thesis award from the Department of Electronics and Electrical Engineering able: http://www.renesas.com in Keio University, the 2006 Keio Kougakukai Award from Keio Kougakukai, the 2007 INOSE Science Promotion Award from the Foundation of Electrical, Electronics, and Information Science Promotion, the 2008 IEEE SSCS Japan Chapter Young Researcher Award and the 2009 IEEE SSCS Japan Chapter Academic Research Award, both from IEEE Solid-State Circuits Society Japan Makoto Saen was born in Hyogo, Japan, in 1974. He Chapter, the Best Student Paper Award from Keio University GCOE Program received the B.S. and M.S. degrees in electrical engi- and IEEE Tokyo Section, and the 2008 Fujiwara Award from the Fujiwara Foun- neering from Hiroshima University, Japan, in 1997 dation. He is awarded as a Distinguished Research Assistant of the Global COE and 1999, respectively. Program (GCOE-DRA) in 2009. He was awarded as an SDC Certiﬁcate at the He joined Central Research Laboratory, Hitachi, student design contest in 2008 IEEE Asian Solid-State Circuits Conference Ltd., Japan, in 1999 and spent eight years working (A-SSCC). He served as a student committee in the 2009 VDEC Designers on various low-power system LSIs. His activities in- Forum and served as the 2009 student Technical Program Committee in the clude on- and off-chip interconnect development and IEICE ICD Technical Meeting for Young Engineers and Researchers. He is a chip-temperature management architecture design. member of IEEE and IEICE (the Institute of Electronics, Information and Com- munication Engineers of Japan).

Kenichi Osada (M’95) was born in Nagano, Japan, in 1969. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Keio University, Tokyo, Japan, in 1992, 1994, and 2005, respectively. In 1994, he joined the Central Research Labora- Yasuhisa Shimazaki (M’99) received the B.E. tory of Hitachi, Ltd., Tokyo, Japan, where he was and M.E. degrees in electrical engineering from initially involved in research into and development Nagoya University, Nagoya, Japan, in 1991 and of high-speed and low-power circuits for the cache 1993, respectively. memories of the SH-4 microprocessor. From 1998 He joined Hitachi, Ltd. as a VLSI circuit engineer to 1999, he was working on the cache memories for upon graduation. From 2000 to 2001, he was a the SH-5 microprocessor at Hitachi Semiconductor Visiting Researcher at University of California, America in U.S.A. From 2000 to 2002, he developed low-power 16-Mb SRAM Berkeley. Since 2003, he has been engaged in and invented several design techniques that prevent cosmic-ray-induced soft er- developing low-power microprocessors at Renesas rors and reduce gate tunnel-leakage currents. From 2003 to 2005, He was in- Technology Corporation. Currently, he is in charge volved in research into the phase change memory. Currently, he is leading the of developing an ultra low-power embedded SRAM research groups of digital and analog circuits and architecture. at Renesas and is working toward the Ph.D. degree in electrical engineering Dr. Osada is a member of the IEEE Solid-State Society. at Keio University. His research interests include energy-efﬁcient digital integrated circuits and high-speed and low-power interface circuits.

Yasuyuki Okuma received the B.S. and M.S. degrees in electrical engineering from Tokyo Uni- versity of Science, Tokyo, Japan, in 1997 and 1999, respectively. In 1999, he joined Central Research Laboratory, Hitachi, Ltd., Japan, where he has engaged in the research and development of low power analog circuit Yasufumi Sugimori received the B.S. and M.S. de- techniques for HDD driver and RF-IC. From 2003 grees in electrical engineering from Keio University, through 2006, he was a visiting researcher at YRP Yokohama, Japan, in 2007 and 2009, respectively. Ubiquitous Networking Laboratory, doing research Since 2006, he has been engaged in research on in the ﬁeld of low-power circuits and systems for the 3-D-stacked inductive inter-chip wireless inter- sensor network. his research interests include ubiquitous computing technology face for System in a Package. He is now with Sony and wireless communication technology. He has been a visiting researcher Corporation. at Extremely Low Power LSI Laboratory, Institute of Industrial Science, The University of Tokyo, since 2009. He is interested in extremely low power LSI circuits and systems.

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Yoshinori Kohama received the B.S. and M.S. de- Toshihiro Hattori (M’06) was born in Kyoto, Japan, grees in electrical engineering from Keio University, on March 30, 1961. He received the B.S. and M.S. Yokohama, Japan, in 2007 and 2009, respectively. degrees in electrical engineering from Kyoto Univer- Since 2006, he has been engaged in research on sity, Japan, in 1983 and 1985, respectively. He re- the 3-D-stacked inductive inter-chip wireless inter- ceived the Ph.D. degree in informatics from Kyoto face for System in a Package. He is now with IBM University, Japan, in 2006. Japan, Ltd. He joined the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, in 1985. He engaged in logic/layout tool development. From 1992 to 1993 he was a Visiting Researcher at the University of California Berkeley, with a particular interest in CAD. He joined the Semiconductor Development Center in the Semiconductor Integrated Circuits Division in Hitachi Ltd. in 1995. He moved to Renesas Technology Corporation in 2003. He was belonging to SuperH (Japan), Ltd. Kazutaka Kasuga was born in 1986. He received the from 2001 to 2004 to conduct SH processor licensing and development. He B.S. degree in electrical and electronic engineering conducted CPU core design including multi-core systems. He is currently from Keio University, Japan, and is currently working working with Renesas Technology conducting Soc design for mobile-phone. toward the M.S. degree. Dr. Hattori is a member of ACM, IEICE, and IPSJ. Since 2008, he has been engaged in research on the 3-D-stacked inductive inter-chip wireless interface for System in a Package. Atsushi Hasegawa received the B.S. degree in computer engineering from the University of Electro Communication, Tokyo, Japan, in 1979. He joined Hitachi Microcomputer engineering Ltd. and worked on computer system boards, microprocessors, and software development tools for Itaru Nonomura received the B.E. degree in elec- Microcomputers. From 1991 to 1992, he was at trical engineering from Waseda University, Tokyo, Carnegie Mellon University as a visiting scientist. Japan, in 1993. He designed Gmicro Microcomputer, SuperH CPUs In 2007, he joined Renesas Technology Corpora- and other processors at Hitachi ULSI systems, tion. He has worked on the development of on-chip Hitachi Semiconductor America, and SuperH Inc. interconnect of system LSIs. Since 2004 he has been with Renesas Technology and leading CPU core, IPs, and semiconductor design methodology development organization.

Tadahiro Kuroda (M’88–SM’00–F’06) received the Ph.D. degree in electrical engineering from the Uni- versity of Tokyo, Tokyo, Japan, in 1999. In 1982, he joined Toshiba Corporation, where he Naohiko Irie received the B.E. degree in electrical designed CMOS SRAMs, gate arrays and standard engineering and the M.E. degree in information cells. From 1988 to 1990, he was a Visiting Scholar systems from Kyushu University, Japan, in 1988 and with the University of California, Berkeley, where 1990, respectively. he conducted research in the field of VLSI CAD. In He joined the Central Research Laboratory, 1990, he was back to Toshiba, and engaged in the Hitachi, Ltd.,Tokyo, Japan, in 1990. He worked research and development of BiCMOS ASICs, ECL on computer architecture and micro-architecture of gate arrays, high-speed CMOS LSIs for telecommu- mainframe, and SMP server after he joined Hitachi. nications, and low-power CMOS LSIs for multimedia and mobile applications. Since 1998, he has worked on architecture for He invented a Variable Threshold-voltage CMOS (VTCMOS) technology to embedded processor and SoC, such as SH-Mobile control through substrate bias, and applied it to a DCT core processor for cellular phones, and led multi-core SoC project and a gate-array in 1995. He also developed a Variable Supply-voltage scheme with Renesas Technology. He was a visiting professor of Kyushu University using an embedded DC-DC converter, and employed it to a microprocessor core from 2007 to 2009. and an MPEG-4 chip for the first time in the world in 1997. In 2000, he moved Mr. Irie received the Best Paper Award for YoungResearcher of IPSJ National to Keio University, Yokohama, Japan, where he has been a professor since Convention and IPSJ Best Paper Award, in 1989 and 1991, respectively. He is 2002. He has been a Visiting Professor at Hiroshima University, Japan, and the a member of IPSJ. University of California, Berkeley. His research interests include low-power, high-speed CMOS design for wireless and wireline communications, human computer interactions, and ubiquitous electronics. He has published more than 200 technical publications, including 50 invited papers, and 20 books/chapters, and has filed more than 100 patents. Dr. Kuroda served as the General Chairman for the Symposium on VLSI Circuits, the Vice Chairman for ASP-DAC, sub-committee chairs for A-SSCC, ICCAD, and SSDM, and program committee members for the Symposium on VLSI Circuits, CICC, DAC, ASP-DAC, ISLPED, SSDM, ISQED, and other international conferences. He is a recipient of the 2005 P&I Patent of the Year Award, the 2006 LSI IP Design Award, the 2007 ASP-DAC Best Design Award, and the 2009 IEICE Achievement Award. He is an IEEE Fellow, an elected AdCom member for the IEEE Solid-State Circuits Society and an IEEE SSCS Distinguished Lecturer.

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