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Intel's Breakthrough in High-K Gate Dielectric Drives Moore's Law Well
January 2004 Magazine Page 1 Technology @Intel Intel’s Breakthrough in High-K Gate Dielectric Drives Moore’s Law Well into the Future Robert S. Chau Intel Fellow, Technology and Manufacturing Group Director, Transistor Research Intel Corporation Copyright © Intel Corporation 2004. *Third-party brands and names are the property of their respective owners. 1 January 2004 Magazine Page 2 Technology @Intel Table of Contents (Click on page number to jump to sections) INTEL’S BREAKTHROUGH IN HIGH-K GATE DIELECTRIC DRIVES MOORE’S LAW WELL INTO THE FUTURE................................................................... 3 OVERVIEW .......................................................................................................... 3 RUNNING OUT OF ATOMS ....................................................................................... 3 SEARCH FOR NEW MATERIALS ................................................................................ 4 RECORD PERFORMANCE ........................................................................................ 5 CAN-DO SPIRIT.................................................................................................... 6 SUMMARY ........................................................................................................... 6 MORE INFO ......................................................................................................... 7 AUTHOR BIO........................................................................................................ 7 DISCLAIMER: THE MATERIALS -
Outline ECE473 Computer Architecture and Organization • Technology Trends • Introduction to Computer Technology Trends Architecture
Outline ECE473 Computer Architecture and Organization • Technology Trends • Introduction to Computer Technology Trends Architecture Lecturer: Prof. Yifeng Zhu Fall, 2009 Portions of these slides are derived from: ECE473 Lec 1.1 ECE473 Lec 1.2 Dave Patterson © UCB Birth of the Revolution -- What If Your Salary? The Intel 4004 • Parameters – $16 base First Microprocessor in 1971 – 59% growth/year – 40 years • Intel 4004 • 2300 transistors • Initially $16 Æ buy book • Barely a processor • 3rd year’s $64 Æ buy computer game • Could access 300 bytes • 16th year’s $27 ,000 Æ buy cacar of memory • 22nd year’s $430,000 Æ buy house th @intel • 40 year’s > billion dollars Æ buy a lot Introduced November 15, 1971 You have to find fundamental new ways to spend money! 108 KHz, 50 KIPs, 2300 10μ transistors ECE473 Lec 1.3 ECE473 Lec 1.4 2002 - Intel Itanium 2 Processor for Servers 2002 – Pentium® 4 Processor • 64-bit processors Branch Unit Floating Point Unit • .18μm bulk, 6 layer Al process IA32 Pipeline Control November 14, 2002 L1I • 8 stage, fully stalled in- cache ALAT Integer Multi- Int order pipeline L1D Medi Datapath RF @3.06 GHz, 533 MT/s bus cache a • Symmetric six integer- CLK unit issue design HPW DTLB 1099 SPECint_base2000* • IA32 execution engine 1077 SPECfp_base2000* integrated 21.6 mm L2D Array and Control L3 Tag • 3 levels of cache on-die totaling 3.3MB 55 Million 130 nm process • 221 Million transistors Bus Logic • 130W @1GHz, 1.5V • 421 mm2 die @intel • 142 mm2 CPU core L3 Cache ECE473 Lec 1.5 ECE473 19.5mm Lec 1.6 Source: http://www.specbench.org/cpu2000/results/ @intel 2006 - Intel Core Duo Processors for Desktop 2008 - Intel Core i7 64-bit x86-64 PERFORMANCE • Successor to the Intel Core 2 family 40% • Max CPU clock: 2.66 GHz to 3.33 GHz • Cores :4(: 4 (physical)8(), 8 (logical) • 45 nm CMOS process • Adding GPU into the processor POWER 40% …relative to Intel® Pentium® D 960 When compared to the Intel® Pentium® D processor 960. -
IBM Z Systems Introduction May 2017
IBM z Systems Introduction May 2017 IBM z13s and IBM z13 Frequently Asked Questions Worldwide ZSQ03076-USEN-15 Table of Contents z13s Hardware .......................................................................................................................................................................... 3 z13 Hardware ........................................................................................................................................................................... 11 Performance ............................................................................................................................................................................ 19 z13 Warranty ............................................................................................................................................................................ 23 Hardware Management Console (HMC) ..................................................................................................................... 24 Power requirements (including High Voltage DC Power option) ..................................................................... 28 Overhead Cabling and Power ..........................................................................................................................................30 z13 Water cooling option .................................................................................................................................................... 31 Secure Service Container ................................................................................................................................................. -
Custom and Multichip Packaging Contract Manufacturing
Custom & Multichip Packaging Contract Manufacturing Micross’ contract assembly offers design and engineering support, BOM procurement, and a wide selection of package, substrate and interposer materials. Micross provides comprehensive semiconductor packaging services for multiple electronic components, including digital, mixed signal, analog, multi-chip and System-in-Package (SiP). We design, build and test hermetic QML and chip scale packaging for various markets including down-hole, aerospace, satellite and military. We combine advanced processes and product development to provide full turnkey support for prototype to volume production of flip chip and wire bond packages including single chip, multichip and SiP applications on organic substrates or ceramic substrates. By ensuring delivery of finished wafers through our relationships with silicon OCMs, and full coordination of customer BOM requirements, we offer complete supply-chain management services for micro- electronic assemblies. Micross Components can support your custom design with: Micross supplies modules and contract assembly services for multiple platforms: industrial, airborne; commercial and government satellites; • Complete turnkey product - including program missile and ordnance; C4ISR and medical. and vendor management of all elements throughout the product lifecycle • Co-development of a statement of work (SOW) Custom Multichip Packaging (MCP) is a die based system or sub-system • Co-design, starting with schematic, netlist or product definition and documentation assembled into a single package which is then mounted to the PCB. • Environmental requirements review In its simplest form factor, two or more of the same die are combined in one industry standard package that is smaller than the equivalent • Package and material selection for optimization of electrical and environmental performance, single die packages combined. -
The Advantages of FRAM-Based Smart Ics for Next Generation Government Electronic Ids
The Advantages of FRAM-Based Smart ICs for Next Generation Government Electronic IDs By Joseph Pearson and Dr. Ted Moise Texas Instruments, Inc. September 27, 2007 Executive Summary Electronic versions of passports and other government-issued identification documents use an Integrated Circuit (IC) or chip to establish a digital link between the holder and personal biometric information, such as a digitized photo, fingerprint or iris image. Designed to enhance border, physical and IT security, electronic chips ensure that the person holding a passport or government document is the one to whom it was legitimately issued. The next generation ICs will employ an advanced embedded memory technology, called FRAM (Ferroelectric Random Access Memory), which considerably improves the speed and reliability of future smart, secure e-passports and government ID documents. More than 50 countries have electronic passport (e-passport) programs, and many countries are also putting in place more secure forms of electronic citizen, visitor and government employee identification. As the volume of document issuance increases and new security threats occur, there is an increased need for industry-standard, next-generation contactless smart IC solutions that securely store, process and communicate data. These new smart ICs will have increased writing speeds to produce and process documents faster and more efficiently, as well as enhanced memory for future security requirements. When FRAM is manufactured at the 130 nanometer semiconductor process node, and embedded in a smart IC, it surpasses the limitations of current Electrically Erasable Programmable Read-Only Memory (EEPROM) and other memory technologies used in government ID applications. The imminent introduction of this innovative memory technology for smart ICs signals a shift in performance in smart card applications deployed in government electronic ID documents. -
1 Intel CEO Remarks Pat Gelsinger Q2'21 Earnings Webcast July 22
Intel CEO Remarks Pat Gelsinger Q2’21 Earnings Webcast July 22, 2021 Good afternoon, everyone. Thanks for joining our second-quarter earnings call. It’s a thrilling time for both the semiconductor industry and for Intel. We're seeing unprecedented demand as the digitization of everything is accelerated by the superpowers of AI, pervasive connectivity, cloud-to-edge infrastructure and increasingly ubiquitous compute. Our depth and breadth of software, silicon and platforms, and packaging and process, combined with our at-scale manufacturing, uniquely positions Intel to capitalize on this vast growth opportunity. Our Q2 results, which exceeded our top and bottom line expectations, reflect the strength of the industry, the demand for our products, as well as the superb execution of our factory network. As I’ve said before, we are only in the early innings of what is likely to be a decade of sustained growth across the industry. Our momentum is building as once again we beat expectations and raise our full-year revenue and EPS guidance. Since laying out our IDM 2.0 strategy in March, we feel increasingly confident that we're moving the company forward toward our goal of delivering leadership products in every category in which we compete. While we have work to do, we are making strides to renew our execution machine: 7nm is progressing very well. We’ve launched new innovative products, established Intel Foundry Services, and made operational and organizational changes to lay the foundation needed to win in the next phase of our company’s great history. Here at Intel, we’re proud of our past, pragmatic about the work ahead, but, most importantly, confident in our future. -
Nano-Cmos Scaling Problems and Implications
CHAPTER 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS 1.1 DESIGN METHODOLOGY IN THE NANO-CMOS ERA As process technology scales beyond 100-nm feature sizes, for functional and high-yielding silicon the traditional design approach needs to be modified to cope with the increased process variation, interconnect processing difficulties, and other newly exacerbated physical effects. The scaling of gate oxide (Figure 1.1) in the nano-CMOS regime results in a significant increase in gate direct tunnel- ing current. Subthreshold leakage and gate direct tunneling current (Figure 1.2) are no longer second-order effects [1,15]. The effect of gate-induced drain leak- age (GIDL) will be felt in designs, such as DRAM (Chapter 7) and low-power SRAM (Chapter 9), where the gate voltage is driven negative with respect to the source [15]. If these effects are not taken care of, the result will be a nonfunctional SRAM, DRAM, or any other circuit that uses this technique to reduce subthresh- old leakage. In some cases even wide muxes and flip-flops may be affected. Subthreshold leakage and gate current are not the only issues that we have to deal with at a functional level, but also the power management of chips for high-performance circuits such as microprocessors, digital signal processors, and graphics processing units. Power management is also a challenge in mobile applications. Furthermore, optical lithography will be stretched to the limit even when en- hanced resolution extension technologies (RETs) are employed. These techniques Nano-CMOS Circuit and Physical Design, by Ban P. Wong, Anurag Mittal, Yu Cao, and Greg Starr ISBN 0-471-46610-7 Copyright © 2005 John Wiley & Sons, Inc. -
3D Massively Parallel Processor with Stacked Memory)
112 IEEE TRANSACTIONS ON COMPUTERS, VOL. 64, NO. 1, JANUARY 2015 Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim Abstract—This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 μ -diameter, 6 μ -height through-silicon vias (TSVs) and μ -diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks. Index Terms—3D Multiprocessor-memory stacked systems, 3D integrated circuits, Computer-aided design, RTL implementation and simulation 1INTRODUCTION HREE-DIMENSIONAL integrated circuits (3D ICs) are ex- circuit components built with different technologies can be Tpected to provide numerous benefits. -
Moore's Law at 40
Moore-Chap-07.qxd 7/28/2006 11:07 AM Page 67 C H A P T E R 7 MOORE’S LAW AT 40 Gordon E. Moore ollowing a paper that I wrote in 1965 and a speech that I gave in F1975, the term “Moore’s law” was coined as a name for a type of prediction that I had made. Over time, the term was used much more broadly, referring to almost any phenomenon related to the semiconductor industry that when plotted on semilog graph paper approximates a straight line. In more recent years, Moore’s law has been connected to nearly any exponential change in technology. I hesitate to focus on the history of my predictions, for by so doing I might restrict the definition of Moore’s law. Nevertheless, in my discussion, I will review the background to my predictions, the reasoning behind them, how these pre- dictions aligned with actual industry performance, and why they did. I will close with a look forward at the future prospects for the prediction. OVERVIEW Moore’s law is really about economics. My prediction was about the future direction of the semiconductor industry, and I have found that the industry is best understood through some of its underlying economics. To form an overall view of the industry, it is useful to consider a plot of revenue versus time. As Figure 1 indicates, the semicon- ductor industry has been a strong growth industry: it has grown a hundredfold dur- ing Intel’s existence. However, from my point of view, this plot of revenue growth really underestimates the true rate of growth for the industry. -
Introduction to System IC Design Flow
Introduction to System IC and Design Flow Outline System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) IC Industry and Chip Production Flow System IC Design Flow Chip Debugging Tools and Reliability Issues 2 SoC Concept Analog Memory PCB ASIC CPU Chip System on a Board Analog IP Memory IP Chip IP IP CPU System on a Chip 3 Soc Advantages Minimize System Cost PCB, passive components Assembling Testing Compact System Size Board layout vs. chip layout Reduce System Power Consumption I/O, passive components, current levels Increase System Performance Interconnecting delay High speed parallel bus 4 Years 2002 – 2008 Worldwide Communication SoC Market Values Unit: Million U.S. Dollars Product 2002 2003 2004 2005 2006 2007 2008 Digital Cellular 7,480 9,463 12,560 15,210 15,855 17,202 19,013 LAN Wireless 138 333 492 662 777 938 1,134 Mobile Infrastructure 325 344 418 537 511 479 481 Other Mobile Comms. 378 520 673 859 1,077 1,215 1,440 LAN 140 184 248 316 348 392 446 Premises and CO Line Card 167 161 188 201 199 204 219 Broadband Remote Access 918 1,313 1,617 1,793 1,717 1,837 1,978 Public Infrastructure 304 360 481 607 667 810 934 Other Wired Comms. 428 568 811 1,128 1,175 1,365 1,515 Total Communications 10,278 13,246 17,488 21,313 22,326 24,442 27,160 Source: Dataquest (2004/06) 5 Example1: Siemens C35i Phone 13 1. Infineon E-GOLD PMB2851E, GSM Baseband controller and DSP. -
Intel(R) Pentium(R) 4 Processor on 90 Nm Process Datasheet
Intel® Pentium® 4 Processor on 90 nm Process Datasheet 2.80 GHz – 3.40 GHz Frequencies Supporting Hyper-Threading Technology1 for All Frequencies with 800 MHz Front Side Bus February 2005 Document Number: 300561-003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Pentium® 4 processor on 90 nm process may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 1Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. -
Increasing Business Agility Through Digital Transformation
Increasing Business Agility Through Digital Transformation VMware IT Performance Annual Report 2019 At VMware, we have a deep and long-standing commitment to helping shape tech as a force for ‘‘ good in the world. That begins with good engineering, and one of the best examples of world-class engineering is our own IT department. VMware IT puts all VMware products to work PAT GELSINGER within our own operations—testing, scaling and CHIEF EXECUTIVE OFFICER VMWARE validating for a demanding customer base of VMware engineers and users. VMware IT is then able to actively engage with customers about the reality of operations in a complex, large- scale, enterprise environment, while ensuring ‘‘ that everything also meets productivity, agility, security and resiliency requirements. I couldn’t be prouder of these efforts and VMware IT. Table of Contents Welcome from the CIO 2 Embracing New Ways of Operating 5 Creating an Agile Enterprise Through App Modernization 19 Building on an Infrastructure Primed for Transformation 24 Transforming Business Through IT Innovation 29 Contact Us 30 1 | ANNUAL REPORT 2019 Welcome from the CIO I write this annual letter with a sense of pride about our company and our thousands of employees in the IT organization around the world driving our transformation. At VMware, our core philosophy is around people and process first, followed by technology. We’re creating a workplace of the future that makes it easier for colleagues to access the tools they need to be productive. We’re employing new technologies and launching innovative initiatives designed to enhance efficiency, boost productivity, improve engagement with business partners and customers, and increase business agility.