IEEE/CPMT

Intel's 90 nm Logic Technology

Mark Bohr

Intel Senior Fellow Director of Process Architecture & Integration

® March 25, 2003 Outline

y Logic Technology Evolution

y 90 nm Logic Technology

y Package Technology

® Page 2 CPU Trend 1 billion transistor CPU by 2007 1,000,000,000 ® 2 CPU 100,000,000 Pentium® 4 CPU Pentium® III CPU 10,000,000 Pentium® II CPU Pentium® CPU TM 1,000,000 486 CPU 386TM CPU

100,000 286

8086 10,000 8080 8008 4004 1,000 1970 1980 1990 2000 2010

® Page 3 CPU MHz Trend 10 GHz CPU by 2007 10,000

Pentium® 4 CPU

1,000 Pentium® III CPU Pentium® II CPU Pentium® CPU

MHz 100 486TM CPU 386TM CPU 286 10 8086 8080

1 1970 1980 1990 2000 2010

® Page 4 Feature Size Trend 10 10000

3.0um 2.0um 1.5um 1.0um 1 .8um Feature 1000 .5um .35um Size .25um Nanometer Micron .18um .13um 90nm 0.1 100

0.01 10 1970 1980 1990 2000 2010 2020

New technology generation introduced every 2 years

® Page 5 Feature Size Trend 10 10000

3.0um 2.0um 1.5um 1.0um 1 .8um Feature 1000 .5um .35um Size .25um Nanometer Micron .18um .13um 90nm 0.1 100 Gate Length 50nm

0.01 10 1970 1980 1990 2000 2010 2020

Transistor gate length scaling faster for improved performance

® Page 6 Logic Technology Evolution

Each new technology generation provides:

~ 0.7x minimum feature size scaling

~ 2.0x increase in transistor density

~ 1.5x faster transistor switching speed

Reduced chip power

Reduced chip cost

® Page 7 Outline

y Logic Technology Evolution

y 90 nm Logic Technology

y Package Technology

® Page 8 Key 90 nm Process Features

y High Speed, Low Power Transistors – 1.2 nm gate oxide – 50 nm gate length – Strained technology y Faster, Denser Interconnects – 7 copper layers – New low-k dielectric y Lower Chip Cost –1.0 µm2 SRAM memory size – 300 mm wafers

® Page 9 90 nm Generation Transistor

Silicide Layer

Silicon Gate Electrode 50nm

1.2 nm SiO2 Gate Oxide

Strained Silicon

® Page 10 90 nm Generation Gate Oxide

Polysilicon Gate Electrode

1.2 nm SiO2

Silicon Substrate

Gate oxide is less than 5 atomic layers thick Nanotechnology is here!

® Page 11 Strained Silicon Transistors

Current Flow

Normal Faster electron electron flow flow Normal Silicon Lattice Strained Silicon Lattice 10-20% drive current increase

® Page 12 Transistor Performance Trend

1.4 10 90nm 1.2

1.0

Drive 0.8 Supply Current NMOS Voltage (mA/um) 0.6 (V)

0.4 PMOS 0.2

0.0 1 1990 1995 2000 2005 Increased drive current for performance Reduced voltage for power and reliability

® Page 13 90 nm Generation Interconnects

7 layers of copper interconnect – 1 more layer than 0.13 µm generation – Extra layer provides cost effective improvement in logic density

New low-k dielectric introduced to reduce wire-wire capacitance – Carbon-doped oxide (CDO) dielectric reduces capacitance by 18% compared to SiOF dielectric used on 0.13 µm – Reduced capacitance speeds up intra-chip communication and reduces chip power

® Page 14 90 nm Generation Interconnects

M7

M6 Low-k CDO Dielectric M5

Copper M4 Interconnects M3 M2 M1

Coarse pitch at upper layers for low resistance Fine pitch at lower layers for high density

® Page 15 6-T SRAM Cell

y SRAM cell has area of 1.0 µm2 y Same process as high performance logic y Small memory cell enables cost effective increase in CPU performance by adding more on-die cache memory

1 µm

® Page 16 6-T SRAM Cell Size Trend

100

10 Cell Area 2 .71x (um ) per year 1

90 nm

0.1 1990 1995 2000 2005 90 nm cell is ~ half the area of 130 nm generation cell

® Page 17 52 Mbit SRAM on 90 nm Process 10.1 mm

10.8 mm

• 330 million transistors on single chip • Perfect chips made with all 52 Mbits working • Initial 90 nm process certification vehicle • Same process as for CPU products

® Page 18 Same Process for Logic and SRAM

• Microprocessors use same Logic transistors and interconnects for Logic and SRAM

• On-die SRAM cache transistor count increasing for improved performance SRAM

0.18 µm Itanium® 2 Processor 144M SRAM, 220M Total

® Page 19 52 Mbit SRAM Chips on 300 mm Wafer

120 billion transistors on one wafer!

® Page 20 Outline

y Logic Technology Evolution

y 90 nm Logic Technology

y Package Technology

® Page 21 Package Technology Requirements

I/O routing • High density • Low impedance Power routing • Low resistance/inductance • High decoupling capacitance Pitch transformation • ~200 µm die side pitch • ~1250 µm board side pitch Low die-package stress • CTE mismatch between silicon and organic package • Compliant/reliable solder bumps • Mechanically weak low-k dielectric materials on silicon Low thermal impedance to heat sink Low cost

® Page 22 CPU Package

Heat Sink Integrated Heat Spreader Silicon Die C4 Bumps Organic Package Bumps or Pins

Pentium® 4 Organic CPU with Package C4 bumps

® Page 23 NewNew PackagingPackaging TechnologyTechnology INT3 everyevery SiSi ProcessProcess TechnologyTechnology INT2 Generation Slot M Generation ULAR INT1 MOD

Slot 2

Slot 1

FCxGA4 ANIC ORG FCxGA2 HIP CMCM LE C FCxGA1 SING CPGA OLGA CPGA PLGA

AMIC PPGA CER

ANIC ORG Complexity / Performance Complexity / 25 MHz 3.0+ GHZ

Intel 486TM Pentium® Pentium® Pro Pentium® II Pentium® III Itanium® Pentium® 4 Processor Processor Processor Processor Processor Processor Processor Ceramic Wire-bond Advanced substrates ® To Organic To Flip Chip Power mgmt. Page 24 Performance Desktop Solutions

BGA Package with Integrated Heat Smaller outline Flip Chip PGA Package Spreader (IHS) mounted on an Interposer with Integrated Heat Spreader (IHS)

Pin side caps

100 mils pin pitch 50 mils pin pitch

Current Interposer New FC-PGA Technology Technology

® Page 25 Mobile Solutions

Land side caps Solder balls instead of pins

Ball Grid Array for direct SMT to the motherboard

® Page 26 iA32 Workstation/Server Solutions

BGA Package with Integrated Heat Spreader (IHS) mounted on an Interposer

Pin side caps

Current MCM New Interposer Technology Technology

® Page 27 iA64 Workstation/Server Solutions

BGA Package with Integrated Heat Spreader (IHS) mounted on an Interposer

Smaller Card Outline

Current MCM New Interposer Technology Technology

® Page 28 For further information on Intel's silicon technology,

please visit the Silicon Showcase at

www.intel.com/research/silicon

® Page 29