The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors
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Intel's Breakthrough in High-K Gate Dielectric Drives Moore's Law Well
January 2004 Magazine Page 1 Technology @Intel Intel’s Breakthrough in High-K Gate Dielectric Drives Moore’s Law Well into the Future Robert S. Chau Intel Fellow, Technology and Manufacturing Group Director, Transistor Research Intel Corporation Copyright © Intel Corporation 2004. *Third-party brands and names are the property of their respective owners. 1 January 2004 Magazine Page 2 Technology @Intel Table of Contents (Click on page number to jump to sections) INTEL’S BREAKTHROUGH IN HIGH-K GATE DIELECTRIC DRIVES MOORE’S LAW WELL INTO THE FUTURE................................................................... 3 OVERVIEW .......................................................................................................... 3 RUNNING OUT OF ATOMS ....................................................................................... 3 SEARCH FOR NEW MATERIALS ................................................................................ 4 RECORD PERFORMANCE ........................................................................................ 5 CAN-DO SPIRIT.................................................................................................... 6 SUMMARY ........................................................................................................... 6 MORE INFO ......................................................................................................... 7 AUTHOR BIO........................................................................................................ 7 DISCLAIMER: THE MATERIALS -
Resonance-Enhanced Waveguide-Coupled Silicon-Germanium Detector L
Resonance-enhanced waveguide-coupled silicon-germanium detector L. Alloatti and R. J. Ram Citation: Applied Physics Letters 108, 071105 (2016); doi: 10.1063/1.4941995 View online: http://dx.doi.org/10.1063/1.4941995 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/108/7?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Waveguide-coupled detector in zero-change complementary metal–oxide–semiconductor Appl. Phys. Lett. 107, 041104 (2015); 10.1063/1.4927393 Efficient evanescent wave coupling conditions for waveguide-integrated thin-film Si/Ge photodetectors on silicon- on-insulator/germanium-on-insulator substrates J. Appl. Phys. 110, 083115 (2011); 10.1063/1.3642943 Metal-semiconductor-metal Ge photodetectors integrated in silicon waveguides Appl. Phys. Lett. 92, 151114 (2008); 10.1063/1.2909590 Guided-wave near-infrared detector in polycrystalline germanium on silicon Appl. Phys. Lett. 87, 203507 (2005); 10.1063/1.2131175 Back-side-illuminated high-speed Ge photodetector fabricated on Si substrate using thin SiGe buffer layers Appl. Phys. Lett. 85, 3286 (2004); 10.1063/1.1805706 Reuse of AIP Publishing content is subject to the terms at: https://publishing.aip.org/authors/rights-and-permissions. IP: 18.62.22.131 On: Mon, 07 Mar 2016 17:12:57 APPLIED PHYSICS LETTERS 108, 071105 (2016) Resonance-enhanced waveguide-coupled silicon-germanium detector L. Alloattia),b) and R. J. Ram Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA (Received 5 January 2016; accepted 3 February 2016; published online 16 February 2016) A photodiode with 0.55 6 0.1 A/W responsivity at a wavelength of 1176.9 nm has been fabricated in a 45 nm microelectronics silicon-on-insulator foundry process. -
Nanoelectronics the Original Positronic Brain?
Nanoelectronics the Original Positronic Brain? Dan Hammerstrom Department of Electrical and Computer Engineering Portland State University Maseeh College of Engineering 12/13/08 1 and Computer Science Wikipedia: “A positronic brain is a fictional technological device, originally conceived by science fiction writer Isaac Asimov “Its role is to serve as a central computer for a robot, and, in some unspecified way, to provide it with a form of consciousness recognizable to humans” How close are we? You can judge the algorithms, in this talk I will focus on hardware and what the future might hold Maseeh College of Engineering 12/13/08 Hammerstrom 2 and Computer Science Moore’s Law: The number of transistors doubles every 18-24 months No discussion of computing is complete without addressing Moore’s law The semiconductor industry has been following it for almost 30 years It is not really a physical law, but one of faith The fruits of a hyper-competitive $300 billion global industry Then there is Moore’s lesser known 2nd law st The 1 law requires exponentially increasing investment And what I call Moore’s 3rd law st The 1 law results in exponentially increasing design errata Maseeh College of Engineering 12/13/08 Hammerstrom 3 and Computer Science Intel is now manufacturing in their new, innovative 45 nm process Effective gate lengths of 37 nm (HkMG) And they recently announced a 32 nm scaling of the 45 nm process Transistors of this size are no longer acting like ideal switches And there are other problems … 45 nm Transistor -
Which Is the Best Dual-Port SRAM in 45-Nm Process Technology? – 8T, 10T Single End, and 10T Differential –
Which is the Best Dual-Port SRAM in 45-nm Process Technology? – 8T, 10T Single End, and 10T Differential – Hiroki Noguchi†, Shunsuke Okumura†, Yusuke Iguchi†, Hidehiro Fujiwara†, Yasuhiro Morita†, Koji Nii†,††, Hiroshi Kawaguchi†, and Masahiko Yoshimoto† † Kobe University, Kobe, 657-8501 Japan. †† Renesas Technology Corporation, Itami, 664-0005 Japan. Phone: +81-78-803-6234, E-mail: [email protected] read ports. The next section describes their cell topologies. Abstract— This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T II. CELL TOPOLOGIES single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area A. 8T SRAM efficient. However, the readout power becomes large and the (a) cycle time increases due to peripheral circuits. The 10T Precharge Precharge circuit single-end SRAM is our proposed SRAM, in which a dedicated signal MC inverter and transmission gate are appended as a single-end read Bitline leakage port. The readout power of the 10T single-end SRAM is reduced by 75% and the operating frequency is increased by 95%, over the 8T SRAM. On the other hand the 10T differential SRAM can MC Memory cell (MC) operate fastest, because its small differential voltage of 50 mV RWL achieves the high-speed operation. In terms of the power WWL Readout current efficiency, however, the sense amplifier and precharge circuits lead to the power overhead. As a result, the 10T single-end P1 P2 Bitline keeper SRAM always consumes lowest readout power compared to the 8T and the 10T differential SRAM. -
Technology Roadmap for 22Nm CMOS and Beyond
Technology Roadmap for 22nm CMOS and beyond June 1, 2009 IEDST 2009@IIT-Bombay Hiroshi Iwai Tokyo Institute of Technology 1 Outline 1. Scaling 2. ITRS Roadmap 3. Voltage Scaling/ Low Power and Leakage 4. SRAM Cell Scaling 5.Roadmap for further future as a personal view 2 1. Scaling 3 Scaling Method: by R. Dennard in 1974 1 Wdep: Space Charge Region (or Depletion Region) Width 1 1 SDWdep has to be suppressed 1 Otherwise, large leakage Wdep between S and D I Leakage current Potential in space charge region is high, and thus, electrons in source are 0 attracted to the space charge region. 0 V 1 K=0.7 X , Y, Z :K, V :K, Na : 1/K for By the scaling, Wdep is suppressed in proportion, example and thus, leakage can be suppressed. K Good scaled I-V characteristics K K Wdep V/Na K Wdep I I : K : K 0 0K V 4 Downscaling merit: Beautiful! Geometry & L , W g g K Scaling K : K=0.7 for example Supply voltage Tox, Vdd Id = vsatWgCo (Vg‐Vth) Co: gate C per unit area Drive current I d K –1 ‐1 ‐1 in saturation Wg (tox )(Vg‐Vth)= Wgtox (Vg‐Vth)= KK K=K Id per unit Wg Id/µm 1 Id per unit Wg = Id / Wg= 1 Gate capacitance Cg K Cg = εoεoxLgWg/tox KK/K = K Switching speed τ K τ= CgVdd/Id KK/K= K Clock frequency f 1/K f = 1/τ = 1/K Chip area Achip α α: Scaling factor In the past, α>1 for most cases Integration (# of Tr) N α/K2 N α/K2 = 1/K2 , when α=1 Power per chip P α fNCV2/2 K‐1(αK‐2)K (K1 )2= α = 1, when α=1 5 k= 0.7 and α =1 k= 0.72 =0.5 and α =1 Single MOFET Vdd 0.7 Vdd 0.5 Lg 0.7 Lg 0.5 Id 0.7 Id 0.5 Cg 0.7 Cg 0.5 P (Power)/Clock P (Power)/Clock 0.73 = 0.34 0.53 = 0.125 τ (Switching time) 0.7 τ (Switching time) 0.5 Chip N (# of Tr) 1/0.72 = 2 N (# of Tr) 1/0.52 = 4 f (Clock) 1/0.7 = 1.4 f (Clock) 1/0.5 = 2 P (Power) 1 P (Power) 1 6 - The concerns for limits of down-scaling have been announced for every generation. -
Moore's Law at 40
Moore-Chap-07.qxd 7/28/2006 11:07 AM Page 67 C H A P T E R 7 MOORE’S LAW AT 40 Gordon E. Moore ollowing a paper that I wrote in 1965 and a speech that I gave in F1975, the term “Moore’s law” was coined as a name for a type of prediction that I had made. Over time, the term was used much more broadly, referring to almost any phenomenon related to the semiconductor industry that when plotted on semilog graph paper approximates a straight line. In more recent years, Moore’s law has been connected to nearly any exponential change in technology. I hesitate to focus on the history of my predictions, for by so doing I might restrict the definition of Moore’s law. Nevertheless, in my discussion, I will review the background to my predictions, the reasoning behind them, how these pre- dictions aligned with actual industry performance, and why they did. I will close with a look forward at the future prospects for the prediction. OVERVIEW Moore’s law is really about economics. My prediction was about the future direction of the semiconductor industry, and I have found that the industry is best understood through some of its underlying economics. To form an overall view of the industry, it is useful to consider a plot of revenue versus time. As Figure 1 indicates, the semicon- ductor industry has been a strong growth industry: it has grown a hundredfold dur- ing Intel’s existence. However, from my point of view, this plot of revenue growth really underestimates the true rate of growth for the industry. -
Intel(R) Pentium(R) 4 Processor on 90 Nm Process Datasheet
Intel® Pentium® 4 Processor on 90 nm Process Datasheet 2.80 GHz – 3.40 GHz Frequencies Supporting Hyper-Threading Technology1 for All Frequencies with 800 MHz Front Side Bus February 2005 Document Number: 300561-003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Pentium® 4 processor on 90 nm process may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 1Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. -
A Study of the Foundry Industry Dynamics
A Study of the Foundry Industry Dynamics by Sang Jin Oh B.S. Industrial Engineering Seoul National University, 2003 SUBMITTED TO THE MIT SLOAN SCHOOL OF MANAGEMENT IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN MANAGEMENT STUDIES AT THE MASSACHUSETTS INSTITUTE OF TECHNOLOGY ARCHVES JUNE 2010 MASSACHUSETTS INSTiUTE OF TECHNOLOGY © 2010 Sang Jin Oh. All Rights Reserved. The author hereby grants MIT permission to reproduce JUN 082010 and to distribute publicly paper and electronic LIBRARIES copies of this thesis document in whole or in part in any medium now known and hereafter created. Signature of Author Sang Jin Oh Master of Science in Management Studies May 7, 2010 Certified by (7 Michael A. Cusumano SMR Distinguished Professor of Management Thesis Supervisor Accepted by (I Michael A. Cusumano Faculty Director, M.S. in Management Studies Program MIT Sloan School of Management A Study of the Foundry Industry Dynamics By Sang Jin Oh Submitted to the MIT Sloan School of Management On May 7, 2010 In Partial Fulfillment of the Requirements for the Degree of Master of Science in Management Studies Abstract In the process of industrial evolution, it is a general tendency that companies which specialize in a specific value chain have emerged. These companies should construct a business eco-system based on their own platform to compete successfully with vertically integrated companies and other specialized companies. They continue to sustain their competitive advantage only when they share their ability to create value with other eco-system partners. The thesis analyzes the dynamics of the foundry industry. -
Intel's 90 Nm Logic Technology
IEEE/CPMT Intel's 90 nm Logic Technology Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration ® March 25, 2003 Outline y Logic Technology Evolution y 90 nm Logic Technology y Package Technology ® Page 2 CPU Transistor Count Trend 1 billion transistor CPU by 2007 1,000,000,000 Itanium® 2 CPU 100,000,000 Pentium® 4 CPU Pentium® III CPU 10,000,000 Pentium® II CPU Pentium® CPU TM 1,000,000 486 CPU 386TM CPU 100,000 286 8086 10,000 8080 8008 4004 1,000 1970 1980 1990 2000 2010 ® Page 3 CPU MHz Trend 10 GHz CPU by 2007 10,000 Pentium® 4 CPU 1,000 Pentium® III CPU Pentium® II CPU Pentium® CPU MHz 100 486TM CPU 386TM CPU 286 10 8086 8080 1 1970 1980 1990 2000 2010 ® Page 4 Feature Size Trend 10 10000 3.0um 2.0um 1.5um 1.0um 1 .8um Feature 1000 .5um .35um Size .25um Nanometer Micron .18um .13um 90nm 0.1 100 0.01 10 1970 1980 1990 2000 2010 2020 New technology generation introduced every 2 years ® Page 5 Feature Size Trend 10 10000 3.0um 2.0um 1.5um 1.0um 1 .8um Feature 1000 .5um .35um Size .25um Nanometer Micron .18um .13um 90nm 0.1 100 Gate Length 50nm 0.01 10 1970 1980 1990 2000 2010 2020 Transistor gate length scaling faster for improved performance ® Page 6 Logic Technology Evolution Each new technology generation provides: ~ 0.7x minimum feature size scaling ~ 2.0x increase in transistor density ~ 1.5x faster transistor switching speed Reduced chip power Reduced chip cost ® Page 7 Outline y Logic Technology Evolution y 90 nm Logic Technology y Package Technology ® Page 8 Key 90 nm Process Features y High Speed, Low -
A 65 Nm 2-Billion Transistor Quad-Core Itanium Processor
18 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 A 65 nm 2-Billion Transistor Quad-Core Itanium Processor Blaine Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul Gronowski, Dan Krueger, Charles Morganti, and Steve Troyer Abstract—This paper describes an Itanium processor imple- mented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105 C. High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s. Index Terms—65-nm process technology, circuit design, clock distribution, computer architecture, microprocessor, on-die cache, voltage domains. I. OVERVIEW Fig. 1. Die photo. HE next generation in the Intel Itanium processor family T code named Tukwila is described. The 21.5 mm by 32.5 mm die contains 2.05 billion transistors, making it the first two billion transistor microprocessor ever reported. Tukwila combines four ported Itanium cores with a new system interface and high speed serial interconnects to deliver greater than 2X performance relative to the Montecito and Montvale family of processors [1], [2]. Tukwila is manufactured in a 65 nm process with 8 layers of copper interconnect as shown in the die photo in Fig. 1. The Tukwila die is enclosed in a 66 mm 66 mm FR4 laminate package with 1248 total landed pins as shown in Fig. -
AN-Introducing 45Nm Technology in Microwind
Introducing 45 nm technology in Microwind3 MICROWIND APPLICATION NOTE Introducing 45 nm technology in Microwind3 Etienne SICARD Syed Mahfuzul Aziz Professor School of Electrical & Information Engineering INSA-Dgei, 135 Av de Rangueil University of South Australia 31077 Toulouse – France Mawson Lakes, SA 5095, Australia www.microwind.org www.unisa.edu.au email: [email protected] email: [email protected] This paper describes the improvements related to the CMOS 45 nm technology and the implementation of this technology in Microwind3. The main novelties related to the 45 nm technology such as the high-k gate oxide, metal- gate and very low-K interconnect dielectric is described. The performances of a ring oscillator layout and a 6- transistor RAM memory layout are also analyzed. 1. Recent trends in CMOS technology Firstly, we give an overview of the evolution of important parameters such as the integrated circuit (IC) complexity, gate length, switching delay and supply voltage with a prospective vision down to the 22 nm CMOS technology. The trend of CMOS technology improvement continues to be driven by the need to integrate more functions within a given silicon area. Table 1 gives an overview of the key parameters for technological nodes from 180 nm, introduced in 1999, down to 22 nm, which is supposed to be in production around 2011. Demonstration chips using 45-nm technology have been reported starting in 2004. Mass market manufacturing with this technology is scheduled for late 2007. Technology node 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm First production 2001 2003 2005 2007 2009 2011 Effective gate 70 nm 50 nm 35 nm 25 nm 17 nm 12 nm length Gate material Poly Poly Poly Metal Metal Metal Gate dielectric SiO2 SiO2 SiON High K High K High K Kgates/mm2 240 480 900 1500 2800 4500 Memory point (2) 2.4 1.3 0.6 0.3 0.15 0.08 Table 1: Technological evolution and forecast up to 2011 The gate material has long been polysilicon, with silicon dioxide (SiO2) as the insulator between the gate and the channel (Fig. -
Intel® Pentium® 4 Processor on 90 Nm Process Specification Update
R Intel® Pentium® 4 Processor on 90 nm Process Specification Update September 2006 Notice: The Intel® Pentium® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update. Document Number: 302352-031 R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Pentium® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 1Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system.