Intel Outlines 90Nm Sige Process Plans Triquint Revises Loss Forecast
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Markets & Business Intel outlines 90nm SiGe process plans Intel plans to add communica- germanium and our most Intel’s 90nm communications tions capabilities to its 90- advanced CMOS manufacturing manufacturing process shares nanometer manufacturing process will bring the benefits the basic foundation of the process by using silicon-germa- of Moore’s Law to communica- company’s 90nm logic process, nium transistors and mixed-sig- tions silicon and help keep including high-performance, nal circuitry, aimed at bringing Intel at least a generation low-power digital CMOS transis- about a new wave of faster, ahead of the competition.” tors using strained silicon tech- highly-integrated, cheaper nology, seven copper intercon- The new manufacturing communications chips. Intel nect layers with a new low-k process combines Intel’s 90-nm says the move could lead to dielectric and one-square- logic process with advance- single-chip, hand-held devices micron SRAM memory cells. In ments in mixed-signal technol- that offer cell-phone, wireless- addition to silicon-germanium ogy. Intel will integrate some data-network and the evolving heterojunction bipolar transis- critical analogue components personal-area-network tors, new features of the 90.nm directly onto silicon and services, as well as smaller, process for communications change how some functions lower-cost network-infrastruc- include high-voltage RF ana- are implemented so they can ture equipment. logue CMOS transistors, preci- be integrated into the logic sion capacitors and resistors for “This integration of computing portion of the chip.The chip analogue circuits, and high-Q and communications technolo- giant says this will mean com- inductors and varactors. gies will enable us to create munications chips will now microchips that are twice as Intel will manufacture all of its benefit from Moore’s Law in fast, contain 2.5 times more 90-nm communications chips performance, power, integra- transistors and are substantially on 300~millimeter wafers, tion and cost terms. less expensive than anything enabling high-volume produc- that exists today,” said Sean Silicon-germanium and CMOS tion and a substantial reduction Maloney, Intel executive vice transistor circuitry on Intel’s 90- in manufacturing costsThe first president and general manager nm process could cut the num- communications chips based of the Intel Communications ber of chips and processes used on the new 90-nm process are Group. “The combination to create an optical subsystem scheduled for introduction of mixed-signal, silicon in half, adds the company. next year. TriQuint revises loss forecast downwards TriQuint Semiconductor has and development associated $12 million may be required forecasted revenues for the with two recent acquisitions. which would result in an addi- quarter ending September 30, This is down from an earlier tional loss of approximately 2002, in the range of $69 mil- estimate of $10 million, a $0.06 per share for the quar- lion to $74 million and operat- write off of approximately ter.The company expects to ing income before special $5 million for two equity continue to have positive cash charges near break even for investments. flow from operations for the the quarter.The company also third quarter.TriQuint also pro- re-iterated its guidance for the The company expects its third vided a preliminary estimate of quarter for a gain of $3.7 mil- quarter results to be a loss of revenue for the fourth quarter lion on the retirement of a por- $0.05 to $0.06 per share, com- of 2002 stating that it expects tion of its debt; a charge of pared to a previous estimate of revenue to be flat to up slight- approximately $1 million for a loss of $0.07 per share and ly over the third quarter of severance related costs; and a also stated that it is reviewing 2002 and that earnings per charge of approximately $9 certain fixed assets for impair- share are expected to be in the million for the write off of ment and that a non-cash range of breakeven to positive acquired in process research impairment charge of up to $0.01. Markets & Business Alcatel warns of 50% drop in 43 revenues Alcatel Optronics says that manufacturing facility focusing market conditions improve but In the U.S., the company continuing recession and per- on active components, our by that time all rightsizing intends to enter into a non- sistent inventories at the cus- Livingston (Scotland) plant on actions should be completed, binding agreement with an tomers’ level could result in passives, and both units com- our financial profile should be industrial partner, whereby revenue for the third quarter bining forces in a joint effort restored and we should be in a this partner would acquire declining up to 50% sequen- towards hybrids. From 1,550 better position to benefit from the majority of the Alcatel tially.The drop should have a staff today, we expect to reach a new market up-cycle.” Optronics Plano (Texas) limited impact on profits, says approximately 1,000 before business and assets.The The company’s plan will mean the company, due to the year-end, and ultimately below deal is expected to close that, in France, headcount at the effects of previously imple- 500 end-2003 .This decrease in before the end of 2002. In Nozay site will drop to approxi- mented cost saving measures. fixed costs should results in an Canada, all Fiber Bragg mately 300 employees, through estimated Euro 40 Million Grating (FBG) activities will “Given a further deterioration a combination of different meas- quarterly sales break-even be discontinued and the of the markets, we feel that it ures including, but not limited point by end 2003. R&D function transferred is mandatory to intensify to, industrial outsourcing, pool- to Livingston where restructuring actions and “Despite these measures, ing of resources with partners, manufacturing has already launch a Strategic Refocus Alcatel Optronics has the spin-offs and individual rede- been relocated. Plan” said Jean-Christophe technology, skill-set and geo- ployments.Alcatel plans talks Giroux, CEO. “We want to graphical presence that will with unions and employees’ The company warns that its reach as soon as possible a make it an undisputed industry representatives to look at possi- operations ‘will continue to be streamlined business model, leader for tomorrow’s market. ble solutions and their practical sized to reflect ongoing busi- with our Nozay (France) It may be a while before implementation. ness conditions’ - - Intel debuts 3D transistors Intel researchers have devel- Gerald Marcyk, director of the Intel’s tri-gate transistor employs approach for extending the oped a three-dimensional tri- Components Research Lab at a 3D structure, like a raised, flat TeraHertz transistor architecture gate transistor design promising Intel. “The tri-gate transistor plateau with vertical sides, Intel announced in December higher performance with design will allow Intel to build which allows signals to be sent 2001.The t&gate is built on an greater power efficiency than ultra-small transistors that along the top of the transistor ultra-thin layer of fully depleted traditional planar transistors. achieve high performance with and along both vertical sidewalls silicon for reduced current leak- The development offers a way low power and continue driv- as welLThis effectively triples age.This allows the transistor to for the semiconductor industry ing the pace of Moore’s Law.” the area available for electrical turn on and off faster, while dra- to maintain the pace of Moore’s signals to travel. Besides operat- matically reducing power con- Law beyond this decade, says Traditional planar transistors, in ing more efficiently at nanome- sumption. It also incorporates a the chip giant. use since the 196Os, struggle as ter-sized geometries, the tri-gate raised source and drain struc- transistors shrink to less than transistor runs faster, delivering ture for low resistance, which “Our research shows that 30 nanometers, the increase in 20 percent more drive current allows the transistor to be driv- below 30 nanometers, the basic current leakage means that than a planar design of compara- en with less powetThe design physics of the flat, single-gate transistors require increasingly ble gate size. is also compatible with the planar transistor leaks too more power to function cor- future introduction of a high K much power to meet our future rectly, which generates unac- The company says the tri-gate gate dielectric for even lower performance goals,” said Dr. ceptable levels of heat. structure is a promising leakage. Nakamura loses Nichia patent claim Shuji Nakamura has lost his Last August, Nakamura claimed undecided reward for the paid Y20,OOO and had failed to claim against Nichia, in which ownership of the patent involv- patent. raise any objections in the ten he maintained he should be ing MOCVD technology and Under Japanese law, an employ- years following the patent recognised as the owner of a demanded Y2 billion compensa- ee retains the rights to any being granted. patent filed in 1991 while he tion.Although the court dis- patents filed, but the court Nakamura’s legal team said an was employed by the Japanese missed the claim, it ruled that threw out the claim because appeal against the ruling would LED maker. he was entitled to an as-yet Nakamura had already been be made. Markets & Business Bede wins fourth Queen’s Award... its workforce. Bede has always been a truly innovative and . and inks global company, and interna- tional trade and technology new Japan are two of the most important factors in the business. agreement “The company sells primarily Bede has also appointed into a highly competitive Tokyo Electron Ltd (TEL), as industry - semiconductors where technology changes at a sole distributor for Bede products in Japan.TEL will fast pace and suppliers to the market, sell, install and main- industry need to be one step ahead of their competitors.