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Assembly and Packaging INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2011 EDITION ASSEMBLY AND PACKAGING THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT. TABLE OF CONTENTS 1. Scope .............................................................................................................................. 1 2. Difficult Challenges ......................................................................................................... 1 3. Single Chip Packaging .................................................................................................... 4 Overall Requirements ...................................................................................................................... 4 Electrical Requirements ................................................................................................................... 5 Cross Talk .................................................................................................................................................... 5 Power Integrity ............................................................................................................................................. 6 Thermal Requirements ................................................................................................................................. 6 Hot Spots ...................................................................................................................................................... 6 Mechanical Requirements ............................................................................................................... 6 Mechanical Modeling and Simulation .............................................................................................. 7 Cost ................................................................................................................................................. 7 Reliability ......................................................................................................................................... 8 Chip to Package Substrate ............................................................................................................ 10 Interconnect Technologies for Single Chip Package ..................................................................... 10 Wire Bonding .............................................................................................................................................. 11 Flip Chip ..................................................................................................................................................... 13 Molding ....................................................................................................................................................... 14 Package Substrate to Board Interconnect ..................................................................................... 15 Lead Frames .............................................................................................................................................. 15 High Density Connections .......................................................................................................................... 15 Package Substrates....................................................................................................................... 15 For Low-Cost Applications—Laminate for PBGA ...................................................................................... 15 Hand-Held Applications—Fine Laminate for FBGA ................................................................................... 16 Mobile Applications—Build-Up Substrate for SiP ...................................................................................... 16 Cost Performance Applications—Build-Up Substrate for FCBGA ............................................................. 16 High Performance—Low κ Dielectric Substrate for FCBGA ...................................................................... 17 4. Wafer Level Packaging ................................................................................................. 18 5. Wafer Level Package Developments and Trends ......................................................... 20 Future Trends for Wafer Level Packaging ..................................................................................... 21 Difficult Challenges for WLP .......................................................................................................... 21 Examples for Emerging Wafer Level Package Technologies ........................................................ 22 Wafer Level Through Silicon Via (TSV) for 3D Integration ........................................................................ 22 Fan Out WLP Using Reconfigured Wafer Level Technologies .................................................................. 23 6. System Level Integration in Package ............................................................................ 23 Definition of SiP ............................................................................................................................. 24 SiP versus SoC.............................................................................................................................. 25 SiP-Level System Design versus Board-Level System Design ..................................................... 25 Difficult Challenges for SiP ............................................................................................................ 26 Thermal Management ................................................................................................................................ 26 Thermal Challenge of Hot Spots in SiP ...................................................................................................... 26 Cooling Solution Design Requirements for SiP ......................................................................................... 27 Thermal Challenges of Processor and Memory Die SiP ............................................................................ 27 Thermal Management of 3D Technology with TSV Interconnect ............................................................. 28 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2011 Power Delivery/Power Integrity .................................................................................................................. 29 Testing of SiP ................................................................................................................................ 29 Test Access ................................................................................................................................................ 29 Contacts ..................................................................................................................................................... 29 Mechanical and Thermal Testing ............................................................................................................... 30 Cost of Test ................................................................................................................................................ 30 SiP for Tera-Scale Computing ....................................................................................................... 31 Diversification and Management of Complexity ............................................................................. 32 The Need for Coherent Chip-Package-System Codesign ............................................................. 32 Collaboration, Cost and Time to Market ..................................................................................................... 34 Importance of Reliability for SiP ................................................................................................................. 35 Need for a Systematic Approach ............................................................................................................... 35 Need for Co-Design Tool Development ..................................................................................................... 35 Generic Chip-Package-System Co-Design Tool Development Requirements .......................................... 35 Co-Simulation of RF, Analog/Mixed Signal, DSP, EM, and Digital ............................................................ 36 7. 3D Integration ............................................................................................................... 36 Scope ............................................................................................................................................ 36 Difficult Challenges ........................................................................................................................ 37 Technology Requirements ............................................................................................................. 38 Interposers ..................................................................................................................................... 38 2.5D Issues ................................................................................................................................................ 39 3D Issues ................................................................................................................................................... 39
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