Quilt Packaging: a Novel High Speed Chip-To-Chip
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QUILT PACKAGING: A NOVEL HIGH SPEED CHIP-TO-CHIP COMMUNICATION PARADIGM FOR SYSTEM-IN-PACKAGE A Dissertation Submitted to the Graduate School of the University of Notre Dame in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Qing Liu, B.E., M.E., M.S.E.E. Gary H. Bernstein, Director Graduate Program in Electrical Engineering Notre Dame, Indiana December 2007 © Copyright by QING LIU 2007 All Rights Reserved QUILT PACKAGING: A NOVEL HIGH SPEED CHIP-TO-CHIP COMMUNICATION PARADIGM FOR SYSTEM-IN-PACKAGE Abstract by Qing Liu As state-of-the-art transistor features continue to shrink and the incorporation of high-k, low-k isolation dielectric materials and strained and SiGe layers on silicon becomes common, chip density and performance are improved. However, system performance has not kept up with the pace especially at multi-GHz clock rates. The bottleneck is packaging. Conventional packaging techniques require high driving current and large in-die area for bonding pads, and provide limited bandwidth. As a result, several technologies, such as system-on-chip, system-in-packaging and system-on-packaging, have been actively pursed to meet the demands of low power, high I/O counts and fast chip-to-chip communication. Here, we present a novel packaging technique, Quilt Packaging (QP), for system-in-package. QP uses microelectromechanical systems (MEMS) inspired fabrication techniques to form Qing Liu contacts along the vertical edge facets of the integrated circuits (ICs) during the back-end-of-line process, enabling the ICs to be interconnected by butting them against each other. A shorter path between chips is established compared with other system-in-packaging techniques pursued by industry, which leads to shorter delay, less power consumption and better signal integrity. The contacts are formed by copper nodules embedded inside the silicon substrate. Nodules are made of trenches into the silicon substrate by deep reactive ion etch (DRIE), which are filled by electrolytic copper plating followed by chemical-mechanical polishing (CMP). Different QP structures are fabricated with nodule depth of 20 µm and widths from 10 µm to 100 µm. To further improve the transmission performance, tapered nodules, which provide better impedance matching to on-chip interconnects, are designed and fabricated. QP is a novel packaging technique for ultra-fast and low-power chip-to-chip communications. The fabrication process of QP can be easily integrated into standard IC process with an extra two masks, one for the nodules and the other for the separation of the chips. The system performance by implementing QP can be dramatically improved along with the improvement of the ICs trends. to my parents… ii CONTENTS FIGURES…………………………………………………………………………….vii TABLES……………………………………………………………………………..xiv ACKNOWLEDGMENT……………………………………………………………..xv CHAPTER 1 INTRODUCTION……………………………………………………...1 1.1 Motivation…………………………………………………………………..1 1.2 Organization………………………………………………………………...6 CHAPTER 2 REVIEW OF PACKAGING TECHNIQUES…………………………..7 2.1 Through-Hole Technology………………………………………………….7 2.2 Surface-Mount Technology…………………………………………………8 2.3 Multichip Modules………………………………………………………….9 2.4 Chip Bonding Techniques…………………………………………………13 2.5 Proximity Communication………………………………………………...15 2.6 Neo-Stack Technology…………………………………………………….17 2.7 Transfer & Join Technology……………………………………………….18 2.8 Off-the-Top Chip-to-Chip Interconnection………………………………..20 iii CHAPTER 3 QUILT-PACKAGING: INTRODUCTION, THEORY AND SIMULATION ……………………………………………………23 3.1 Introduction to Quilt-Packaging…………………………………………...23 3.2 Signal Integrity Characteristics……………………………………………27 3.2.1 Delay……………………………………………………………...27 3.2.2 Reflection…………………………………………………………28 3.2.3 Crosstalk………………………………………………………….28 3.2.4 Ground Bounce…………………………………………………...29 3.3 Electrical Modeling of Interconnects……………………………………...30 3.3.1 On-Chip Interconnection…………………………………………...30 3.3.2 Modeling of On-Chip Interconnects at Intermediate Frequency…...33 3.3.3 Transmission Line Effects………………………………………….39 3.3.4 Modeling of Conventional Packages……………………………….47 3.3.5 Modeling of Quilt-Packaging………………………………………50 CHAPTER 4 QUILT-PACKAGING: FABRICATION PROCESS………………….81 4.1 Calibration of DRIE……………………………………………………….82 4.2 Copper Plating……………………………………………………………..88 4.2.1 Electroless Copper Plating…………………………………………89 4.2.2 Electrolytic Copper Plating………………………………………...92 4.3 Chemical Mechanical Polishing………………………………………….98 iv 4.3.1 Theory…………………………………………………………….101 4.4 Experiments on Quilt-Packaging Fabrication with Electroless Plating….103 4.5 Experiments on Quilt-Packaging Fabrication with Electrolytic Plating…111 4.6 Final Fabrication Process of Quilt-Packaging……………………………121 CHAPTER 5 MICROWAVE MEASUREMENTS OF QUILT PACKAGING…….141 5.1 Review of de-embedding techniques for on-wafer measurements………141 5.1.1 Open………………………………………………………………142 5.1.2 Open and Short……………………………………………………143 5.1.3 Open, Short and Thru……………………………………………..145 5.1.4 Two-port Network with a Thru……………………………………147 5.1.5 Three-step with Two Shorts, Open and Thru……………………..148 5.1.6 Four-step with Two Shorts and Two Opens………………………151 5.1.7 Two-port Network with One Open and Two Thrus……………….153 5.1.8 Two-port Network with One Open and One Thru………………...156 5.2 Microwave Measurements of QP………………………………………...159 CHAPTER 6 CONCLUSIONS AND FUTURE WORK…………………………...170 6.1 Conclusions………………………………………………………………170 6.2 Future Work………………………………………………………………173 v REFERENCES……………………………………………………………………...182 Chapter 1 References…………………………………………………………182 Chapter 2 References…………………………………………………………184 Chapter 3 References…………………………………………………………186 Chapter 4 References…………………………………………………………189 Chapter 5 References…………………………………………………………192 Chapter 6 References…………………………………………………………194 vi FIGURES 1.1 A system-on-chip where different function blocks are integrated into one chip, and complexity is decreased by re-using IP (intellectual property) from different design houses………………………………………………............2 1.2 SiP (a) 2-D assembly and (b) 3-D assembly…………………………………4 1.3 SiP example based on 3-D assembly…………………………………………4 1.4 SoP concept for system integration of thin film components………………...5 1.5 Conceptual diagram of Quilt-Packaging……………………………………..6 2.1 Schematic of a dual-in-line plated through-hole package……………………7 2.2 (a) A schematic of the surface-mount technology and (b) a closer look at surface-mount package………………………………………………………8 2.3 A typical multichip module………………………………………………….9 2.4 (a) MCM-L, (b) MCM-C, and (c) MCM-D………………………………..10 2.5 Fabrication process of MCM-C…………………………………………….12 2.6 Cross section of MCM-D with a flip-chip solder bump……………………13 2.7 Chip bonding techniques: (a) wire bonding, (b) tape automated bonding, and (c) flip-chip bonding………………………………………………………..14 2.8 Cross section of inter-chip interconnection………………………………...15 2.9 Circuit diagram of transmitter and receiver………………………………..15 2.10 Chip photograph……………………………………………………………16 2.11 A close look of aligned chip………………………………………………..16 2.12 Neo-stack process sequence………………………………………………..17 2.13 A flash memory module……………………………………………………18 2.14 Schematic graph of (a) normal MCM and (b) T & J……………………….19 2.15 T & J technology for (a) 2-D SiP, (b) 3-D SiP with thermal problem, and (c) 3-D SiP offering thermal dissipation……………………………………….20 2.16 Conventional and the new off-the-top interconnection between two chips..21 2.17 20 Gbps/channel chip-to-chip interconnection……………………………..21 2.18 High bandwidth interconnection using off-the-top………………………...22 3.1 Conceptual diagram of Quilt-Packaging…………………………………...23 3.2 Cartoon representation of: (a) a simple two-chip QP connection and (b) a three-chip QP system……………………………………………………….25 3.3 Quilt-packaging applications in (a) optical communications, (b) RF communications, and (c) high speed digital processors……………………26 3.4 Ground bounce setup and voltages…………………………………………29 vii 3.5 The trends of smallest transistor gate length and minimum width of interconnects………………………………………………………………..31 3.6 A typical chip cross-section………………………………………………...31 3.7 Cross-section of SEM picture of 90 nm CMOS interconnects and their key design rules…………………………………………………………………32 3.8 (a) Lumped model and (b) distributed model………………………………33 3.9 Repeater insertion to reduce RC delay……………………………………..34 3.10 Schematic of uniformly repeated line with initial cascade stage…………..37 3.11 Eliminating buffer stage in (a) by resizing logic stages and repeaters……..37 3.12 Delay comparison…………………………………………………………..38 3.13 Delay and power comparison………………………………………………38 3.14 Simulation models for distributed RC lines: (a) π model, (b) t model, (c) π2 model, (d) t2 model, (e) π3 model and (f) t3 model………………………..39 3.15 (a) Schematic of transmission line and (b) distributed RLGC model……...40 3.16 Distributed LC model for lossless transmission line……………………….41 3.17 Schematic of combined skin effect and proximity effect…………………..44 3.18 Transmission line circuit with load and generator…………………………45 3.19 A schematic top view of an open classic IC package……………………...47 3.20 A partial package model for 3 leads………………………………………..48 3.21 Main parasitics in package…………………………………………………48 3.22 Typical ground bond and grounded lead for a floating paddle package…...49 3.23 Side view of a typical two chip interconnection through quilt-packaging…50 3.24 Cross sections of (a) conventional CPW, (b) conductor-backed CPW, and (c) CPW with finite ground planes…………………………………………….51 3.25 Schematic of a two-port transmission line…………………………………56 3.26 HFSS