Transformative Power Technologies to Impact 21st Century Energy Economy, and Space and Defense Electronics

Krishna Shenai, PhD Professor Electrical Engineering and Computer Science University of Toledo

Birck Nanotechnology Center Purdue University West Lafayette, IN

July 8, 2010 Our Research

Material Technologies

The Interface

Advanced Systems Today’s AC Power Grid

Step Up Voltage Transformer Step Down Voltage 3 Phase 155,000 to 765,000 Volts Transmission Loss AC Power Transformer (7,200 Volts) Electro Mechanical Switches

7,200 volts Power Generator Transmission Substation Generation Loss High Voltage Distribution Transmission Lines Substation Distribution Loss Transformer 120 volts AC 60 Hz

Residential Industrial Consumer Consumer Commercial Consumer Reference: www.epri.com Electricity Technology Roadmap EnergyEnergy EfficiencyEfficiency

End Use Utilization

Incandescent Bulb 12% Efficient Light Generation Transmission & Distribution Electricity ~ 4 Units 35 % Efficient 93% Efficient

~ 32 Units Coal Electricity ~ 32 Units Compact Fluorescent Lamp 100 Units ~ 35 Units 22% Efficient

Light Energy Loss From Generation through End-Use ~ 7 Units

Reference: www.epri.com Energy Efficiency: A Renewed Imperative LightLight EmittingEmitting DiodeDiode (LED)(LED)

 New energy law approved by US Congress to ban incandescent bulbs by 2014.

 Replace existing incandescent with Compact Fluorescent Lamp (CFL) and LED beginning 2012. IncandescentIncandescent LightLight BulbBulb

LED CFL Incandescent

Life Span 50,000 hours 8,000 hours 1,200 hours

Compact Fluorescent Lamp Power 6 - 8 watts 13-15 watts 60 watts Consumed

Annual $42.16/year $84.32/year $361.35/year Operating Light Emitting bulb Cost*

* Usage of 30 bulbs 5 hours a day Reference - www.mrbeams.com/index.asp?PageAction=Custom&ID=2 www.worldnetdaily.com/news/article.asp?ARTICLE_ID=59298 What is the problem? Cost Efficiency Reliability Security Environmental Impact Utilization Generation The Opportunity

• The greatest technical achievement of the 20th century is the electrification - Thomas Edison

• will reconfigure today’s fragile electric power grid just the same way as it did the information infrastructure of the 20th century - Morgan Stanley

• Information-quality power is the greatest business opportunity of our time – George Gilder

• A perfect power system is the one that has plentiful of energy and never fails its customers - Bob Galvin Perfect Power System

20th Century Wireless Information Technology

Perfect Power System - Plentiful green energy, secure and reliable

21st Century Green Energy & Power Technologies Utilization of Distributed Renewable Energy Generators (DREGs)

• Chip-Scale Power – up to few hundred Watts

• Medium Power – from few hundred Watts to few hundred kilo Watts

• Utility-Scale Power – more than a few hundred kilo Watts Solar-Powered Data Center

Why Solar-Powered Data Centers? Features of PV DC/DC Converter:

• 1.5% of US electricity used • 98% efficient SiC Boost Converter • $4.5B annual electricity bill • Integrated smart PPT • > 2X increase in electricity need by 2011 • Smart load balancing • Efficient PV integration into DC system • Wireless smart control • 4% - 6% efficiency improvement • Dramatic cost reduction for DC system over existing AC • Significant improvement in reliability

Sponsor - NSF Power Supply Tradeoffs – an Example

• IBM eServer 900 • 30% volume taken by PS • 10% volume by cooling ROADBLOCK !

Lossy Components and Packaging! 10 kW Power Supply P. Singh, et.al., IBM J. Res. & Dev., Nov. 2002 50 kHz to 75 kHz = 50% reduction in size and 50% reduction in cooling 12 90 100 4 .) 8 85 10 2 a.u Cost (¢/W) Cost MTBF (

4 80 (%) Efficiency 1 1

Si (a.u.) Cost Cooling

50 100 150 1 2 3 Frequency (kHz) Power Density (a.u.) Power Switching Fundamentals A A A A VSUP

iL Load R L L Diode B

Power D Switch C B B B Typical Loads Power Switching Circuit

D

RG G

VGS S VGS

0 Ton T time Typical Power Switch and Control Power MOSFET Switching

V SUP 2 PC = IDS RON ON-state Loss OFF-state Loss ILOAD = IDS LOAD POFF = ILKVSUP

2 PSW = CINV GSf Energy Recoverable

Current Source PL = ILOADVSUP Energy IC I Supplied GS VOUT T = 1/f D VIN VGS CIN VGS

Time

Figure of Merit (FOM) = RONCIN; RONQGS

K. Shenai, IEEE TED, vol. 37, no. 4, pp. 1141-1153, April 1990 HARD vs. SOFT Switching HARD SOFT

1000 100 1000 100 di/dt di/dt (+ ve) (+ ve) dv/dt dv/dt ZVS Turn-on (- ve) (- ve) Turn-on Voltage (V) Voltage (A) Current (V) Voltage (A) Current

5 10 15 5 10 15 Time (μsec) Time (μsec)

1000 100 1000 100 di/dt dv/dt dv/dt (+ ve) di/dt (- ve) (- ve) (+ ve) ZCS Turn-off Turn-off Voltage (V) Voltage (V) Voltage Current (A) Current (A) Current

5 10 15 5 10 15 Time (μsec) Time (μsec) Current High-End Computer Power Supply

Simplify Bulky HV Driver New Power MOSFET

New Power MOSFET New Power MOSFET High-End Computer Power Supply

Current Industry Standard

90%, High Current 48V Bus 92%, $0.2-$0.5/W 82%, Multiple Output VRM 2kW 2.65kW 2.44kW 12V 2.95kW POL PFC BULK ISOLATED 110-220VAC 48V 12V 5V DC-DC DC-DC BUCK POL DC-DC 3.3V BUCK POL DC-DC 1.xV BUCK POL DC-DC

Overall: 68% Efficient, 950W Power Loss, $1020 Cost and MTBF of ~ 200,000 Hours.

Current Power System Cost, Energy Efficiency, and Reliability are Dictated by Power Semiconductor Switch Loss. More Integrated Solution

New IC with Simple HV Driver New Power MOSFET

New New Power SR IC MOSFET

New Power MOSFET

Replace with Efficient Power Switches and IC, Eliminate HV Driver Increase Overall Efficiency to 90%, Reduce Cost by 60% High-End Server Power Supply

Quantum Leap in System Performance & Reliability

95%, Low Current 380V Bus 95%, Multiple Output VRM 2kW

2.2kW 2.1kW 12V POL PFC BULK 110-220VAC 12V 5V DC-DC BUCK POL DC-DC 3.3V BUCK POL DC-DC 1.xV BUCK POL DC-DC

Goal: 90% Efficient, 200W Power Loss, $400 Cost and MTBF ~ 500,000 Hours. 60% Savings in System Cost 80% Savings in Power Loss Improved Field Reliability Field-Reliability Paradigm

Need “End-of-Life” SOA that accounts for sustained dynamic application stresses

K. Shenai, IEEE Spectrum, pp. 50-55, July 2000 Field-Failure of Power MOSFETs

K. Shenai, 12th Ann. Automotive Reliability Workshop, Nashville, TN, 2007 (invited) Field MTBF Improvement – an Example

Vendor

K. Shenai et al., IECEC Conference, pp. 1480-1490, 2000 Monolithic Mobile Platform

Digital (1–3.6 V) RF/Analog (2.5–12V) – Processor – Filters and mixers – Memory Power – VCO – RF baseband I I – LNA and opamp – Control N N – Sensors – PA T T E Digital E Physical R A/D Signal D/A R Input F Processing F Video A A Display C C E Communication E Power (1–12 V) Mixed-Signal (1.5–5 V) – Converter – DSP Electrical – Regulator – Multimedia Optical – On-chip power supply – Signal converters

● Present Solution: multiple, cascaded, independent DC-DC power converters. inefficient, narrow band PA with poor S/N performance. ● Need: Integrate DC-DC converters and broadband PA into a single power management chip; develop single-chip mobile platform. Battery and Power Management Evolution

3G’s next step B 3G E A N T E T R E G R D Y Y LI P H R M A SOC R U Power N NiMh Management V Integrated LDO Gas Smaller E LDO T Gauge Circuit S µLDO T I Dc/Dc Size M I LDO Converter High E Battery N Regulator Efficiency Lower Discrete G DC Converters Charger Noise Regulator

1990 1993 1996 2000 2002 2004 OEM Loads and SMPS Specifications

4 – 28V LDO, Hybrid DISPLAY 10 – 200mA 50% - 92% Low speed (ms) $0.3 - $3 Li-ion Cell Boost (2.7 - 4.2V)

0.4 – 3.4V LDO, Hybrid RFPA 10mA – 2A 30% - 92% Low speed (ms) $0.3 - $1.5

2.5 – 3.2V - Boost Hybrid RADIO,FLASH 1 – 20mA 70% - 92% Medium speed $0.8 - $1.2

(ms - µs) Buck

0.8 – 2.5V Hybrid CPU,DSP 1 – 800mA 70% - 92% High speed $1 - $1.5 (µs- ns) Slow Buck Chip-Scale DC-DC Power Conversion Techniques

Concept Power Range Efficiency Speed Profile

Charge Pump ~ few 100 mA 70% - 90% Slow Single Chip/Hybrid

Switch Capacitor ~ few 100 mA 70% - 90% Slow Single Chip/Hybrid

LDO ~ several Amps 50% Slow Single Chip

Note: All of the above techniques are RC time limited to a response time of several µsecs., and generally deliver very low power (few hundred mW).

Switch Mode (SMPS) ~ several Amps 70% - 95% Slow Hybrid

Note: To obtain high power conversion efficiency, switch-mode power conversion is performed mostly at < 3 MHz; it is slow and in hybrid circuitry form. High-Current Charge Pumps

5 • Wide input range Patents Pending - Down to 0.5 V 4 - As high as 3 V • Variable output 3 - Voltage doubling - Voltage tuning (± 5%) 2 • Performance - Over 90% efficiency OUTPUT CURRENT (A) CURRENT OUTPUT - Under 1% ripple 1 - Under 100-kHz clock • Uses standard CMOS 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 • Ideal for constant-load INPUT VOLTAGE (V) applications Cell Phone Application

2 1 PA 10 – 20% Driver 60 – 70% High Power External LDO, SMPS Hybrid SMPS

Backlight Driver High Voltage Low Current 4 10 – 20% 3 Integrated LDO, SC, CP Hybrid SMPS Battery Baseband Charger (DSP, Arm, Audio Low Voltage amp, …) High Current High Speed Switch Mode (SMPS) Converter in Handheld Devices

Maxim 8506-8508 in a Cell Phone Maxim 1582 in a Notebook PA Power Supply White LED Power Supply

Large External Passives

High-frequency (@ > 1 MHz) switch- mode power conversion facilitates on- chip integration of passive elements. Efficiency vs. Load Current – Maxim 8506-8508 used for Cell Phone RFPA power supply

VIN = 2.5V 100

90

80 PWM

Mode VOUT = 1.2V 70 Efficiency (%) Efficiency

VOUT = 2.5V

50 1 10 100 1000 Load Current (mA) Circuit Size and Height

RF PA SMPS Inductor Size: 6 x 6 X 2.0 mm Our Power Management Chip Hybrid inductor size is 10x our chip Size: 3 x 3 x .84 mm Chip Scale Power Inductor

60 nH 1.6 mm x 1.6 mm; W=40 µm, S=35 µm

Q 40

500 µm air gap 35 Patents Pending |Eqn| 30 Q_sample3 300 µm air gap |Eqn| Q_sample4

25 0.1 0.2 0.3 0.4 0 Radiation Boundary on Top Surface with Air Fr equency ( GHz) Dielectric 50 μm Polyimide Tape f=_FREQ Extracted Model from HFSS Simulation. k=179.9 Rac=k*1e-6*(sqrt(f)) CAP ID= C1 Rac: { 1.799,2.544,3.116,3.598,4.023 } C= 0 pF

PORT PORT Air gap below P= 1 RES IND RES P= 2 Z= 50 Ohm ID= R1 ID= L1 ID= R2 Z= 50 Ohm R= 0.5023 Ohm L= 53.45 nH R= Rac Ohm inductor varied 300 to CAP CAP ID= C2 ID= C3 C= 0.1747 pF C= 0.07287 pF 500 μm. RES ID= R3 R= 2.835e7 Ohm ADC with Embedded Power Management

• Specifications - High resolution (high Area is proportional to ADC power dissipation

sensitivity at low VDD), 10-bit or better ADC Power Dissipation (mW) Our work - Low power, <500 mW 16 - High sample rate, >50 MSPS 14

12 1999 • Target markets 1998 1997 - Multimedia 10 1996 - Wireless telephony 1995 1994 8

- Digital photography (bits)BitResolution 1993 - Analog and digital video cameras 6

4 US 6,608,503 – Hybrid Comparator 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 and Method Sample Rate (Sa/sec) Adaptive Intelligent Power Management (AIPM)

• Activity level is determined by - Voice, data, streaming multimedia and static web contents access - Links to peripherals, e.g. display, keypad etc.

• Impact of activity on power dissipation - Some components frequently idle - Some components require constant alertness - Active components have power profile that is proportional to “activity” level

• Present solution: power regulation is unresponsive to activity levels • Innovative solution: dynamic power minimization based on user activity levels - Increase effective battery lifetime by 2x to 5x AIPM Concept

US 5,959,439 – Monolithic DC-DC Converter

US 6,791,341 – Current Derivative Sensor

US 6,714,049 – Logic State Transition Sensor

• Generate multiple supply voltages • Scale V per logic block or cluster • Use more slices for fast multiplexing DD • Permit tuning of power vs. 1• Produce rapid tuning of supply voltage 3 performance per logic block or cluster • Develop single chip power supply • Provide continuous execution in low- technology power modes • Develop analog building blocks • Provide real-time statistics on activity of 4 2 amenable to variable-VDD operation logic blocks or clusters MAX2291 PA with Variable Vcc from MAX8506 switching regulator – Measured PAE and Gain vs. Output Power

2x battery life

Dynamic Power Management Example.

Pout is function of closeness to Base station Chip Scale Power Integration

PoL Power PoN Power

D2D D2D

Power Source

D2D

D2D D2D

• Cell Phone • Microprocessor • PDA • DSP • Laptop • Data Converter • PA for Handheld OEM GaN Power FETs and DC-DC Converters

T. McDonald, Electronics in Motion and Conversion, vol. 11, pp. 2-42, April 2009 Heterogeneous Chip-Scale Power Integration

Vin Q1 CMOS VG1 Synchronous Control Buck Converter IC L +

VG2 Q2 D C RL Vo

-

+ C V Vin Q 1 - dr Q1 Gate Drive for 3

“Normally On” FET Q4

D1

K. Shenai, IEEE Electron Device Letters, vol. 11, pp. 520-522, 1990 Advanced GaN HEMT Structures E-mode D-mode Key innovations: Selectively thermally oxidized AlInN G S G D/S G D G (a) E-mode

GaN (b) Vbr/Ron tunability (G-D region) AlGaN back barrier (c) Gate leakage reduction Selectively oxidized InAlN InAlN/AlN Novel interleaved cell layout (a) Reduced parasitics (b) Reduced power loss

Collaborator: Dr. Xuili (Grace) Xing G2 (Top view) G1 University of Notre Dame

M2 ILD M1 Metal 1 S2 D2/S1 D1 ILD S2 G2 OutputS G1 D 1 G2 G1 Substrate Advanced Si MOS Power Diode Structures p+ n+ n+ Metal Poly p Oxide n n

I I PN IMOS SB IMOS n+ n+

K K (a) (b) Notre Dame “Quilt Packaging”

a) Concept a) b) Nodules

c) Proposed inductor

c) b)

Collaborator: Dr. G. H. Bernstein University of Notre Dame QP Allows World-Record Chip-to-Chip Bandwidth

• De-embedded insertion loss compared with recent papers on wire bonds, , Quilt Packaging MS-to-CPW RF-via, . • 0.25 dB lower than coaxial flip-chip via at 40 GHz • 1.7 dB lower than standard flip-chip at 110 GHz • 0.8 dB lower than RF-via at 70 GHz

Courtesy: Dr. G. H. Bernstein University of Notre Dame Electro Osmotic DC Micro Cooling

Pump outlet EO pump structure: Water from at the top Top - Cathode/wire electrode heat rejector Middle - Porous membrane (e.g. grit filter) Pump inlet at Bottom: Anode/wire electrode the bottom Water being Water into pumped up MCHS Heat Pump Rejector Water to MCHS heat rejector Quilt Converter quilt

Collaborator: Dr. Jie (Jayne) Wu University of Tennessee at Knoxville Performance of 12V/1V, 10W Synchronous Buck Converter 95 90 85 80 75 Best Commercial Silicon MOSFET 70 Best Commercial GaN HEMT

Efficiency (%) Efficiency 65 Proposed GaN HEMT 60 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 Frequency (MHz) 250 0.5 200 Capacitor 0.4 Inductor 150 0.3 µF

100 0.2 µH 50 0.1 0 0 0.5 2.5 4.5 6.5 8.5 10 Frequency (MHz) Transmitters with Amplitude-Modulated Signals

HIGH-LEVEL LINEAR AMPLIFIER AMPLITUDE MODULATION

Patent Pending

Collaborator: Dr. Frederick H. Raab Green Mountain Radio Research Company, VT Electronically Tuned Power Amplifier (ETPA)

Patent Pending Patent Pending

PA PA

BIAS/CONTROL BIAS/CONTROL Antenna Tuner Plasma Generator

Load Impedance Varies with: Frequency Ground Proximity Time (heating) Power (plasma) Prototype Electronically Tuned PA ETPA - Tuning Performance

POWER OUTPUT EFFICIENCY

OPERATING FREQUENCY RANGE Fixed conventional: 23.0 - 25.5 MHz (1.11:1) Electronic: 18.75 - 31.5 MHz (1.68:1) Load -Modulated Class-E PA Measured Efficiency

INSTANTANEOUS EFFICIENCY AVERAGE EFFICIENCY

• Only one bias (T network) varied • Average efficiency x 2.7 for 10-dB peak-to-average ratio Load-Modulated Class-E PA Efficiency

INSTANTANEOUS EFFICIENCY AVERAGE EFFICIENCY

Only one element (T- network capacitor) varied Average efficiency 87% for 10-dB peak-to-average ratio Our Vision for RF Power Module

Power Source

SOI GaN SMPS Control IC Power FET

L C

GaN GaN RF GaN IMN Power FET OMN

SiC Substrate Utilization of DC Power

PV Supplemented Resistive Loads PV Supplemented Adjustable Speed Motor Drives

Conventional Conventional AC Power Input PV Array (< AC Power Input PV Array (utility) 10kW) (utility)

Drive DC Level DC Level Rectifier Converter Rectifier Converter Unit

DC Bus (250-600V) DC Bus (250-600V)

Adjustable Speed Drive Inverter Resistive Heat Element

EPRI White Paper Overall ASD Unit Edison Grid @

COM & Energy SMART Lighting HVAC AC Grid WIRELESS COMP Storage DIGITAL CONTROLLER

Energy Conversion & DC BUS Power Management Other Renewable Fuel Cells Sources

Wind Solar 10 kW Distributed Smart DC Solar Microgrid Major Goal:

Increase < 86% (current) efficiency to >93% with direct DC distribution and utilization.

Achieve 50% cost reduction Collaborator: in power electronics. Nextek Power Systems Micrel Medium Power Integration

>95%

>97% High-Penetration of DC Microgrid

High penetration of DC microgrid could potentially lead to > 22% gain in energy efficiency in residential, commercial, manufacturing and data centers in the US. Impact of DC Microgrid on US National Economy

Sector Potential Potential Potential Reduction TWh Saved Efficiency Gain (%) in US Load (%) Residential 121 25 3 Commercial 123 19 3 Manufacturing 77 20 1.9 Data Centers 15 28 0.4 Total 337 22 8.3

P. Savage et al, Yale School of Forestry and Environmental Studies, pp. 51-66, June 2010. High-Power Technology

Expand the speed x power envelope

Hubert Mills Digital Power Report High-Power Converters

• 5.8kV Si IGBT module • Integrated current sensor C • ZCTS topology • PEBB packaging B

Collaborators: ABB, AdTranz & Hitachi E M. Trivedi and K. Shenai, APEC Digest, 2001

150 kW DC-DC Converter

New

• 1.2kV, 100A Si IGBT module • 1.2 kV SiC Schottky Diode • Hard Switching • Liquid Cooling

100 kW Inverter (DOE) Collaborator: RMS Power Systems Thermal Management

Heat Exchanger Flow Channel Approach Perfect Semiconductor Power Switch

20th Century Technology 21st Century Technology

S S Metal Co Sio2 Oxide N+ N+ N+ C G G D P Base P Base N+ N+ P P G P+ G N- Drift region N

- S P+ P Substrate E N+ Substrate Meta D K Si MOSFET Si IGBT SiC IGBT SiC MCT

Shenai et al, IEEE TED, vol. 36, no. 9, pp. 1811-1823, Sept. 1989 MOS-Controlled Thyristor – The “Holy Grail” of Power Switch

Lowest On-State Power Loss

Turn-off Failure

V. Temple, EPRI Technical Report # TR – 106991, Nov. 1996 Why (SiC) ?

Si 4H SiC 3C SiC Silicon for Power Band Gap (eV) 1.12 3.2 2.2 High Temp Electron Mobility 1400 800 750 Has hit a brick wall (cm2/Vs) High Speed Breakdown Field 0.25 3.0 2.2 (MV/cm) High Voltage Thermal 1.5 3.5 3.5 Conductivity Reduced (W/cm.K) Cooling -2 12 13 11 Qss (cm ) 10 -10 10 Blocking Voltage (< 8 kV) Lower VT Current Density -Thermal Limits (< 100 A/cm2) Silicon Carbide Offers SBD MOSFET • Higher Switching Frequency & SBD  Compact Power Converter • Higher Voltage Devices  High Power Operation • High Temperature Operation  Energy and Cost Savings

 Harsh Environmental Operation

The Roadblock to SiC adoption has been: Reliability Cost

SiC Schottky vs SiC PiN Diode Silicon Carbide (SiC) Power Converter Application: 2 kV, 7 kW PS-ZVS FB DC-DC Converter

Parameter SiC Si Frequency (kHz) 500 50

Filter Capacitance (μF) 10 100 50,000 cm3 Filter Inductance (mH) 0.6 6 18 kg Transformer Volume (cm3) 63 215

Efficiency (%) 95 @ 22C 92 @ 22C Silicon Power Switch 89 @ 150C No 85 @ 300C No Shenai’s Figure of Merit -

QF 2 = λσ AEM Power Density (W/cm3) 8 4 2400x improvement Collaboration NASA Glenn Research Center 4,500 cm3 K. Shenai et al, IECEC Conference Digest, pp. 30-36, 2000 0.2 kg SiC Power Switch K. Shenai et al, IEEE TED, pp. 1811-1823, 1989 Poor Turn-Off dv/dt of SiC Schottky Diode SW2 SiC Schottky Diode : 6A/600V; PD2 Si PiN Diode : 8A/600V SW1 SiC Schottky Diode : 10A/300V; SD1 Si Schottky Diode : 12A/200V 600V Devices 200/300V Devices 6 3 SW2 Voltage = 600V SW1 Voltage = 200V PD2 SD1 4.5 2.25 Failure Instant Failure Instant 3 1.5

TC = 25 C TC = 25 C 1.5 0.75 Peak Diode Current Diode (A) Current Peak Peak Diode Current Diode (A) Current Peak

0 0 0 15 30 45 60 0 15 30 45 60 dv/dt 1 dv/dt1 • SiC Schottky diode fails at dv/dt = 57 V/ns • No failure observed even at dv/dt = 70V/ns for silicon diode of similar rating • ActivationDiodes of SiCare defects leaky at high and dv/dt NOTcauses avalanche high current and rated failure, failure may be related to poor edge termination K. Acharya and K. Shenai, Proc. PET Conference, pp. 672-677, Oct. 2002 Schottky Junction ON and OFF States

ON OFF ON 1.1V 1000V 1.5V Metal Metal Metal Junction Junction Depletion Region Depletion Region dv/dt dv/dt P+ (+ ve) (- ve) Depletion Region

N N

di/dt di/dt N N (- ve) (+ ve)

100A 250 µA 100A Low E-field High E-field Low E-field

Need high τSC dv/dt failure is due to excess charge generation in the depletion region SiC PN Diode Closed Core Screw Dislocation Study Courtesy of Dr. Phil Neudeck, NASA GRC

- Increased reverse leakage. X-Ray Topograph - Softened breakdown I-V knee (repeatable). - Local microplasma breakdown. Reverse I-V Properties

10 -3 With 1c Screw Dislocation(s) Closed Core (1c) -4 Without 10 Screw Dislocations 10 -5

10 -6 100 µm

Current (A) 10 -7

10 -8

-9 Breakdown 10 -100 -80 -60 -40 -20 0 Microplasmas Voltage (V) Optical Photo (No Metal) PN Junction Failure at Micropipe Courtesy of Dr. Phil Neudeck, NASA GRC Micropipe propagates through & epilayer normal to wafer surface.

Microscope Causes large reduction in breakdown voltage, localized junction failure.

Micropipe P-type N 6H P 6H - - SiC SiC 1 mm 1 failure microplasma

Lightsource micropipes + - N-type VR Localized Currents in SiC Power Devices Courtesy of Dr. Phil Neudeck, NASA GRC

OBIC* of “Good” Diode OBIC* of “Bad” Diode

λ = 313 nm λ = 313 nm Vbias = 500 V Vbias = 300 V

a) b)

Figures from Frischholz et. al., MRS Symp. Proc. 512, p. 157 (1998) Localized leakage, breakdown, and hot-spot formation is undesired in power devices. - Device’s ability to withstand dynamic circuit faults is reduced. - Lowers device avalanche energy rating. - Decreases power device reliability. *OBIC = Optical Beam Induced Current SiC PN Diode Performance vs. Area

Kimoto et. al., IEEE Trans. Electron Devices, vol. 46 (3), p. 471, 1999

Extracted defect density 1000 - 2000 per square cm. Type-1 Images at 1.0 A Before and After Current Stressing

6.0 V @ 1.0 A 6.9 V @ 1.0 A

Lower current capacity in dark areas

Courtesy of Dr. Robert Stahlbush, NRL PN Junction ON and OFF States ON OFF ON 1.5V 1000V 1.5V

P+ + P+ dv/dt dv/dt P (+ ve) (- ve)

Depletion Region Junction Junction Depletion Region

Depletion Region N di/dt di/dt N (- ve) (+ ve) N 100A 250 µA 100A Low E-field Low E-field High E-field Need high τn0 and τp0 Need high τn0 and τp0 Need high τSC Need low τn0 and τp0 Silicon Carbide (SiC) – Potential Benefits & Status

• For more than TWO decades, it has been recognized that Silicon Carbide (SiC) can provide major advantages over silicon in high-power and harsh environmental electronics [1].

Because of superior electrical, thermal, mechanical, and chemical properties, SiC power devices promise dramatic improvements in energy efficiency at significantly reduced cost. • Much of the research and funding on SiC material in the past has been directed at eliminating the bulk micropipes [2].

Several wafer manufacturers including Cree and Dow Corning are marketing Zero Micropipe (ZMP) 4 inch diameter SiC wafers at reasonable cost. However, these wafers typically contain ~104 cm-2 total dislocation defects (screw dislocations, basal plane dislocations, edge dislocations, etc.). • However, broad based commercial and military benefits of SiC have not yet been realized due to high density of bulk defects [3].

Researchers world-wide have conclusively demonstrated that high density of bulk defects prevent the manufacturing and application of high-voltage and high-current SiC power devices, cause poor field-reliability of power converters, and result in prohibitively high die cost.

[1] K. Shenai et al, IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1811-1823, Sept. 1989. [2] M. Skowronski and S. Ha, J. Appl. Phys., vol. 99, pp. 011101-1 – 011101-24, 2006. [3] K. Shenai, IEEE Spectrum, vol. 37, no. 7, pp. 50-55, July 2000 (invited paper). Silicon Carbide (SiC) – What is Needed?

• Existing SiC wafer production is inherently flawed in that a high density of screw dislocations (SDs) is necessary to achieve commercially viable SiC boule growth rates (the order of 0.5 mm/h) [1].

Current state-of-the-art wide bandgap crystal growth techniques yield more than 103 screw dislocation defects per cm2 for SiC material and more than 107 per cm2 defects for GaN semiconductor. A defect-free SiC substrate is also crucial to manufacture high-quality of III-Nitride used for solar cell and LED applications. • Our contention is that a NEW approach is needed for SiC bulk crystal growth in order to achieve its widespread use in power electronics, photovoltaics, light emitting , energy harvesting and other energy conversion devices [2].

Must reduce total wafer dislocation density by 100 to 1000 fold compared to the current state-of-the-art.

[1] J. A. Lely, US Patent # 2,854,364, issued on Sept. 30, 1958. [2] J. A. Powell et al, US Patent # 7,449,065 B1, issued on Nov. 11, 2008. Existing SiC Wafer Growth Approach (Sublimation growth or High Temperature CVD)

C-axis (vertical) growth proceeds from top surface of large-area seed crystal via thousands of screw dislocations.

Vertical growth rate would not be commercially viable (i.e., would not be high enough) without high density (> 100 cm-2) of screw dislocations.

Crystal enlargement is vertical (up c-axis). Negligible lateral enlargement.

Thermal gradient driven growth at T > 2200 °C High thermal stress/strain

Fundamental Flaw: Abundant screw dislocation defects are needed for present SiC wafer growth approach, yet these same defects harm SiC power device yield and performance (cause blocking voltage de-rating, leakage, etc.). - High thermal stress also generates dislocation defects. Future: Game Changer - Large Tapered Crystal (LTC) Growth (US Patent 7,449,065 Owned by OAI, Sest, Inc., with NASA Rights)

Vertical Growth Process: Small-diameter c-axis fiber Fiber-like growth of small- from single screw dislocation at diameter columnar tip region mm/hour rate. (from single screw dislocation)

Lateral Growth Process: MOST of crystal grown via CVD growth enlargement epitaxy process on laterally on sidewalls to produce expanding taper at large-diameter boule significantly lower growth (T = 1500 - 2000 °C) temperature (lower thermal stress) and growth rate.

Completed boule section Large diameter wafers Ready for slicing into wafers yielded at mm/hour (wafers/hour) growth rate!

Tapered portion is then re-loaded into growth system as seed for subsequent boule growth cycle. “Game Changing” Technology

Best 0.2 x 0.2 mm SD-free 3C mesa (oxidized to map polytype and defects)

4H-SiC Diode Etched to Show Defects Defect-free SiC Need Commercialization Each Small Black Dot is a Crystal Defect 100’s of Defects in < 10 Amp device

• 4 in. dia. low-cost, low defect-density commercial wafers • Robust high-performance devices • Low-cost manufacturing • 250C packaging and 300C sensors LTC Game Changing Technology

LTC Vision: Dramatically improved SiC wafer quality realized at higher volumes and lower production cost.

Present-Day SiC Wafer LTC SiC Wafer

~100-10,000 screw dislocations/cm2 < 1 screw dislocation/cm2 < 0.5 wafers per hour > 1 wafer per hour Cost: > $2000/4-inch wafer Cost: < $500 /6-inch wafer Commercial Power Devices Commercial Power Devices Limited to < 50 A, ~1 kV 100-1000 A, > 10kV Drastic wafer improvement sufficient to unlock full SiC power device potential. (Approach also applicable to 3C-SiC, GaN, Diamond, and other semiconductors)

Collaborators: Mike Dudley (SUNY - SB) Phil Neudeck, Andy Trunek, and A. Powell (NASA – GRC) Hot-Wall SiC CVD Reactor

Inlet

Outlet

Inlet Inlet

Inlet Inlet Temperature gradients Gas flow Deposition pattern pattern What is Needed ?

DC-DC Converter Inverter

POUT = 100 kW P = 1 MW @ 100 kHz OUT TAMB < 200 C Target Specs. TAMB < 200 C η > 98% η > 96%

Reliability Criteria Cost Size Weight

Reliable Efficient Semiconductor Power Switch High-Temperature Control IC High-Temperature, Low-Loss Magnetic and Passive Components Novel Sensors Compact Thermal Management Thanks

July 8, 2010 Purdue BNC Seminar