DOCSLIB.ORG

Transformative Power Semiconductor Technologies to Impact 21St Century Energy Economy, and Space and Defense Electronics

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Transformative Power Semiconductor Technologies to Impact 21St Century Energy Economy, and Space and Defense Electronics Transformative Power Semiconductor Technologies to Impact 21st Century Energy Economy, and Space and Defense Electronics Krishna Shenai, PhD Professor Electrical Engineering and Computer Science University of Toledo Birck Nanotechnology Center Purdue University West Lafayette, IN July 8, 2010 Our Research Material Technologies The Interface Advanced Systems Today’s AC Power Grid Step Up Voltage Transformer Step Down Voltage 3 Phase 155,000 to 765,000 Volts Transmission Loss AC Power Transformer (7,200 Volts) Electro Mechanical Switches 7,200 volts Power Generator Transmission Substation Generation Loss High Voltage Distribution Transmission Lines Substation Distribution Loss Transformer 120 volts AC 60 Hz Residential Industrial Consumer Consumer Commercial Consumer Reference: www.epri.com Electricity Technology Roadmap EnergyEnergy EfficiencyEfficiency End Use Utilization Incandescent Bulb 12% Efficient Light Generation Transmission & Distribution Electricity ~ 4 Units 35 % Efficient 93% Efficient ~ 32 Units Coal Electricity ~ 32 Units Compact Fluorescent Lamp 100 Units ~ 35 Units 22% Efficient Light Energy Loss From Generation through End-Use ~ 7 Units Reference: www.epri.com Energy Efficiency: A Renewed Imperative LightLight EmittingEmitting DiodeDiode (LED)(LED) New energy law approved by US Congress to ban incandescent bulbs by 2014. Replace existing incandescent with Compact Fluorescent Lamp (CFL) and LED beginning 2012. IncandescentIncandescent LightLight BulbBulb LED CFL Incandescent Life Span 50,000 hours 8,000 hours 1,200 hours Compact Fluorescent Lamp Power 6 - 8 watts 13-15 watts 60 watts Consumed Annual $42.16/year $84.32/year $361.35/year Operating Light Emitting Diode bulb Cost* * Usage of 30 bulbs 5 hours a day Reference - www.mrbeams.com/index.asp?PageAction=Custom&ID=2 www.worldnetdaily.com/news/article.asp?ARTICLE_ID=59298 What is the problem? Cost Efficiency Reliability Security Environmental Impact Utilization Generation The Opportunity • The greatest technical achievement of the 20th century is the electrification - Thomas Edison • Silicon will reconfigure today’s fragile electric power grid just the same way as it did the information infrastructure of the 20th century - Morgan Stanley • Information-quality power is the greatest business opportunity of our time – George Gilder • A perfect power system is the one that has plentiful of energy and never fails its customers - Bob Galvin Perfect Power System 20th Century Wireless Information Technology Perfect Power System - Plentiful green energy, secure and reliable 21st Century Green Energy & Power Technologies Utilization of Distributed Renewable Energy Generators (DREGs) • Chip-Scale Power – up to few hundred Watts • Medium Power – from few hundred Watts to few hundred kilo Watts • Utility-Scale Power – more than a few hundred kilo Watts Solar-Powered Data Center Why Solar-Powered Data Centers? Features of PV DC/DC Converter: • 1.5% of US electricity used • 98% efficient SiC Boost Converter • $4.5B annual electricity bill • Integrated smart PPT • > 2X increase in electricity need by 2011 • Smart load balancing • Efficient PV integration into DC system • Wireless smart control • 4% - 6% efficiency improvement • Dramatic cost reduction for DC system over existing AC • Significant improvement in reliability Sponsor - NSF Power Supply Tradeoffs – an Example • IBM eServer 900 • 30% volume taken by PS • 10% volume by cooling ROADBLOCK ! Lossy Components and Packaging! 10 kW Power Supply P. Singh, et.al., IBM J. Res. & Dev., Nov. 2002 50 kHz to 75 kHz = 50% reduction in size and 50% reduction in cooling 12 90 100 4 .) 8 85 10 2 a.u Cost (¢/W) Cost MTBF ( 4 80 (%) Efficiency 1 1 Si (a.u.) Cost Cooling 50 100 150 1 2 3 Frequency (kHz) Power Density (a.u.) Power Switching Fundamentals A A A A VSUP iL Load R L L Diode B Power D Switch C B B B Typical Loads Power Switching Circuit D RG G VGS S VGS 0 Ton T time Typical Power Switch and Control Power MOSFET Switching V SUP 2 PC = IDS RON ON-state Loss OFF-state Loss ILOAD = IDS LOAD POFF = ILKVSUP 2 PSW = CINV GSf Energy Recoverable Current Source PL = ILOADVSUP Energy IC I Supplied GS VOUT T = 1/f D VIN VGS CIN VGS Time Figure of Merit (FOM) = RONCIN; RONQGS K. Shenai, IEEE TED, vol. 37, no. 4, pp. 1141-1153, April 1990 HARD vs. SOFT Switching HARD SOFT 1000 100 1000 100 di/dt di/dt (+ ve) (+ ve) dv/dt dv/dt ZVS Turn-on (- ve) (- ve) Turn-on Voltage (V) Voltage (A) Current (V) Voltage (A) Current 5 10 15 5 10 15 Time (μsec) Time (μsec) 1000 100 1000 100 di/dt dv/dt dv/dt (+ ve) di/dt (- ve) (- ve) (+ ve) ZCS Turn-off Turn-off Voltage (V) Voltage (V) Voltage Current (A) Current (A) Current 5 10 15 5 10 15 Time (μsec) Time (μsec) Current High-End Computer Power Supply Simplify Bulky HV Driver New Power MOSFET New Power MOSFET New Power MOSFET High-End Computer Power Supply Current Industry Standard 90%, High Current 48V Bus 92%, $0.2-$0.5/W 82%, Multiple Output VRM 2kW 2.65kW 2.44kW 12V 2.95kW POL PFC BULK ISOLATED 110-220VAC 48V 12V 5V DC-DC DC-DC BUCK POL DC-DC 3.3V BUCK POL DC-DC 1.xV BUCK POL DC-DC Overall: 68% Efficient, 950W Power Loss, $1020 Cost and MTBF of ~ 200,000 Hours. Current Power System Cost, Energy Efficiency, and Reliability are Dictated by Power Semiconductor Switch Loss. More Integrated Solution New IC with Simple HV Driver New Power MOSFET New New Power SR IC MOSFET New Power MOSFET Replace with Efficient Power Switches and IC, Eliminate HV Driver Increase Overall Efficiency to 90%, Reduce Cost by 60% High-End Server Power Supply Quantum Leap in System Performance & Reliability 95%, Low Current 380V Bus 95%, Multiple Output VRM 2kW 2.2kW 2.1kW 12V POL PFC BULK 110-220VAC 12V 5V DC-DC BUCK POL DC-DC 3.3V BUCK POL DC-DC 1.xV BUCK POL DC-DC Goal: 90% Efficient, 200W Power Loss, $400 Cost and MTBF ~ 500,000 Hours. 60% Savings in System Cost 80% Savings in Power Loss Improved Field Reliability Field-Reliability Paradigm Need “End-of-Life” SOA that accounts for sustained dynamic application stresses K. Shenai, IEEE Spectrum, pp. 50-55, July 2000 Field-Failure of Power MOSFETs K. Shenai, 12th Ann. Automotive Reliability Workshop, Nashville, TN, 2007 (invited) Field MTBF Improvement – an Example Vendor K. Shenai et al., IECEC Conference, pp. 1480-1490, 2000 Monolithic Mobile Platform Digital (1–3.6 V) RF/Analog (2.5–12V) – Processor – Filters and mixers – Memory Power – VCO – RF baseband I I – LNA and opamp – Control N N – Sensors – PA T T E Digital E Physical R A/D Signal D/A R Input F Processing F Video A A Display C C E Communication E Power (1–12 V) Mixed-Signal (1.5–5 V) – Converter – DSP Electrical – Regulator – Multimedia Optical – On-chip power supply – Signal converters ● Present Solution: multiple, cascaded, independent DC-DC power converters. inefficient, narrow band PA with poor S/N performance. ● Need: Integrate DC-DC converters and broadband PA into a single power management chip; develop single-chip mobile platform. Battery and Power Management Evolution 3G’s next step B 3G E A N T E T R E G R D Y Y LI P H R M A SOC R U Power N NiMh Management V Integrated LDO Gas Smaller E LDO T Gauge Circuit S µLDO T I Dc/Dc Size M I LDO Converter High E Battery N Regulator Efficiency Lower Discrete G DC Converters Charger Noise Regulator 1990 1993 1996 2000 2002 2004 OEM Loads and SMPS Specifications 4 – 28V LDO, Hybrid DISPLAY 10 – 200mA 50% - 92% Low speed (ms) $0.3 - $3 Li-ion Cell Boost (2.7 - 4.2V) 0.4 – 3.4V LDO, Hybrid RFPA 10mA – 2A 30% - 92% Low speed (ms) $0.3 - $1.5 Boost 2.5 – 3.2V - Hybrid RADIO,FLASH 1 – 20mA 70% - 92% Medium speed $0.8 - $1.2 (ms - µs) Buck 0.8 – 2.5V Hybrid CPU,DSP 1 – 800mA 70% - 92% High speed $1 - $1.5 (µs- ns) Slow Buck Chip-Scale DC-DC Power Conversion Techniques Concept Power Range Efficiency Speed Profile Charge Pump ~ few 100 mA 70% - 90% Slow Single Chip/Hybrid Switch Capacitor ~ few 100 mA 70% - 90% Slow Single Chip/Hybrid LDO ~ several Amps 50% Slow Single Chip Note: All of the above techniques are RC time limited to a response time of several µsecs., and generally deliver very low power (few hundred mW). Switch Mode (SMPS) ~ several Amps 70% - 95% Slow Hybrid Note: To obtain high power conversion efficiency, switch-mode power conversion is performed mostly at < 3 MHz; it is slow and in hybrid circuitry form. High-Current Charge Pumps 5 • Wide input range Patents Pending - Down to 0.5 V 4 - As high as 3 V • Variable output 3 - Voltage doubling - Voltage tuning (± 5%) 2 • Performance - Over 90% efficiency OUTPUT CURRENT (A) CURRENT OUTPUT - Under 1% ripple 1 - Under 100-kHz clock • Uses standard CMOS 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 • Ideal for constant-load INPUT VOLTAGE (V) applications Cell Phone Application 2 1 PA 10 – 20% Driver 60 – 70% High Power External LDO, SMPS Hybrid SMPS Backlight Driver High Voltage Low Current 4 10 – 20% 3 Integrated LDO, SC, CP Hybrid SMPS Battery Baseband Charger (DSP, Arm, Audio Low Voltage amp, …) High Current High Speed Switch Mode (SMPS) Converter in Handheld Devices Maxim 8506-8508 in a Cell Phone Maxim 1582 in a Notebook PA Power Supply White LED Power Supply Large External Passives High-frequency (@ > 1 MHz) switch- mode power conversion facilitates on- chip integration of passive elements. Efficiency vs. Load Current – Maxim 8506-8508 used for Cell Phone RFPA power supply VIN = 2.5V 100 90 80 PWM Mode VOUT = 1.2V 70 Efficiency (%) Efficiency VOUT = 2.5V 50 1 10 100 1000 Load Current (mA) Circuit Size and Height RF PA SMPS Inductor Size: 6 x 6 X 2.0 mm Our Power Management Chip Hybrid inductor size is 10x our chip Size: 3 x 3 x .84 mm Chip Scale Power Inductor 60 nH 1.6 mm x 1.6 mm; W=40 µm, S=35 µm Q 40 500 µm air gap 35 Patents Pending |Eqn| 30 Q_sample3 300 µm air gap |Eqn| Q_sample4 25 0.1 0.2 0.3 0.4 0 Radiation Boundary on Top Surface with Air Fr equency ( GHz) Dielectric 50 μm Polyimide Tape f=_FREQ Extracted Model from HFSS Simulation.
Load more

Recommended publications
  • Development of 3-D Printed Hybrid Packaging for Gaas-MEMS
    University of South Florida Scholar Commons Graduate Theses and Dissertations Graduate School June 2018 Development of 3-D Printed Hybrid Packaging for GaAs-MEMS Oscillators based on Piezoelectrically-Transduced ZnO-on-SOI Micromechanical Resonators Di Lan University of South Florida, [email protected] Follow this and additional works at: https://scholarcommons.usf.edu/etd Part of the Electrical and Computer Engineering Commons Scholar Commons Citation Lan, Di, "Development of 3-D Printed Hybrid Packaging for GaAs-MEMS Oscillators based on Piezoelectrically-Transduced ZnO- on-SOI Micromechanical Resonators" (2018). Graduate Theses and Dissertations. https://scholarcommons.usf.edu/etd/7690 This Dissertation is brought to you for free and open access by the Graduate School at Scholar Commons. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Scholar Commons. For more information, please contact [email protected]. Development of 3-D Printed Hybrid Packaging for GaAs-MEMS Oscillators based on Piezoelectrically-Transduced ZnO-on-SOI Micromechanical Resonators by Di Lan A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Jing Wang, Ph.D. Thomas M. Weller, Ph.D. Arash Takshi, Ph.D. Rasim Guldiken, Ph.D. Shengqian Ma, Ph.D. Date of Approval: June 14, 2018 Keywords: Microelectromechanical Systems, Additive Manufacturing, MMIC, Microfabrication Copyright © 2018, Di Lan DEDICATION To my wife, my parents, my advisors, my friends ACKNOWLEDGMENTS First, I would like to state my greatest appreciation to my major advisor and Professor Dr.
    [Show full text]
  • Advanced Ic Packaging Technologies, Materials, and Markets 2015 Edition
    ADVANCED IC PACKAGING TECHNOLOGIES, MATERIALS, AND MARKETS 2015 EDITION A Strategic Report Covering the Latest Technologies in IC Packaging, Enabling Portable and Other Electronics Report Coverage Report Highlights Stacked Packages Industry Outlook System-in-Packages Market Analysis and Forecasts, Interconnection Technologies 2013–2019 Through-Silicon-Vias (TSV) Multichip Packaging 2.5D and 3D Integration Technology Trends Multi-row QFNs Key Application Forecasts Fan-out WLPs Company Profiles New Venture Research A Technology Market Research Company 337 Clay St., Suite 101 [email protected]/ Nevada City, CA 95959 www.newventureresearch.com/ Tel: (530) 265-2004 Fax: (530) 265-1998 Advanced IC Packaging Technologies, Materials, and Markets, 2015 Edition Synopsis The demand for consumer electronics and mobile QFNs and WLPs), as well as advanced communications devices that keep us connected is multicomponent packages (PoPs, PiPs, and MCMs). driving electronics manufacturers to deliver ever-more Forecasts include multichip IC packaging units, compact and portable electronic systems. Today's revenue, prices, die usage and applications. users ask for products with more functionality, added performance, higher speed, and smaller form factors. Chapter 6: System in Package (SiP) Solutions & Advances in IC packaging technologies are providing Substrate Materials, presents a more in-depth look at solutions to meet these demands through a variety of the evolving multicomponent packages, and presents techniques that result in ICs that are more powerful and key market trends alongside forecasts of units and provide greater functionality, while fitting into ever revenue. This chapter also examines the substrate smaller and more highly integrated form factors. materials and embedded components used in SiP Multichip packages are on the leading edge of silicon assembly.
    [Show full text]
  • Integrating MEMS and Ics
    OPEN Microsystems & Nanoengineering (2015) 1, 15005; doi:10.1038/micronano.2015.5 © 2015 IECAS All rights reserved 2055-7434/15 www.nature.com/micronano Review Article Integrating MEMS and ICs Andreas C. Fischer, Fredrik Forsberg, Martin Lapisa, Simon J. Bleiker, Göran Stemme, Niclas Roxhed and Frank Niklaus The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the ‘More-Than- Moore’ paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated.
    [Show full text]
  • 2006 Technical Program
    International Microelectronics Assembly and Packaging Society New England Chapter 43rd Annual Symposium Technical Sessions - May 3, 2016 Symposium’s Technical Chairs Welcome Letter We’d like to welcome everyone to the 43nd Annual New England iMAPS Symposium! Thanks to all the Session Chairs we’ve compiled an engaging program of technical talks on many of today’s hot topics that will peak the interest of every Attendee. We hope you take full advantage of the opportunity to interact with the speakers and each other in a learning environment that’s only available at this unique one day symposium. Below is a brief summary to help you on your way and don’t forget to spend time in the exhibit hall, because after all without the support of the exhibitors this day wouldn’t be possible. Enjoy!!! Dmitry Marchenko Dr. Parshant Kumar RF and Microwave - Innovations and Emerging Technologies: This session is all about the innovations and emerging technologies that are driving RF and microwave packaging industry. Returning by popular demand and includes talks from industry leaders such as CST, Ametek and Draper. The topics cover issues like EM coupling between buck converters and antennas, Low Loss Additive Materials and design challenges of millimeter-wave semiconductor packaging. 3D and Beyond: This session covers the latest advancements in 2.5/3D technology. A Novel way to produce 3D chip assemblies called Quilt will be presented by IIC. Presentation by Tufts will describe liquid metal interconnects use in studies of animals and soft robots. You will learn about the latest Draper work on Printed transceivers.
    [Show full text]
  • Assembly and Packaging
    INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION ASSEMBLY AND PACKAGING THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009 TABLE OF CONTENTS Scope....................................................................................................................................1 Difficult Challenges................................................................................................................2 Single Chip Packaging ..........................................................................................................2 Overall Requirements......................................................................................................................2 Electrical Requirements ...............................................................................................................................3 Cross Talk ....................................................................................................................................................3 Power Integrity .............................................................................................................................................3 Thermal Requirements.................................................................................................................................3 Hot spots ......................................................................................................................................................4 Mechanical Requirements............................................................................................................................4
    [Show full text]
  • Quilt Packaging: a Novel High Speed Chip-To-Chip
    QUILT PACKAGING: A NOVEL HIGH SPEED CHIP-TO-CHIP COMMUNICATION PARADIGM FOR SYSTEM-IN-PACKAGE A Dissertation Submitted to the Graduate School of the University of Notre Dame in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Qing Liu, B.E., M.E., M.S.E.E. Gary H. Bernstein, Director Graduate Program in Electrical Engineering Notre Dame, Indiana December 2007 © Copyright by QING LIU 2007 All Rights Reserved QUILT PACKAGING: A NOVEL HIGH SPEED CHIP-TO-CHIP COMMUNICATION PARADIGM FOR SYSTEM-IN-PACKAGE Abstract by Qing Liu As state-of-the-art transistor features continue to shrink and the incorporation of high-k, low-k isolation dielectric materials and strained and SiGe layers on silicon becomes common, chip density and performance are improved. However, system performance has not kept up with the pace especially at multi-GHz clock rates. The bottleneck is packaging. Conventional packaging techniques require high driving current and large in-die area for bonding pads, and provide limited bandwidth. As a result, several technologies, such as system-on-chip, system-in-packaging and system-on-packaging, have been actively pursed to meet the demands of low power, high I/O counts and fast chip-to-chip communication. Here, we present a novel packaging technique, Quilt Packaging (QP), for system-in-package. QP uses microelectromechanical systems (MEMS) inspired fabrication techniques to form Qing Liu contacts along the vertical edge facets of the integrated circuits (ICs) during the back-end-of-line process, enabling the ICs to be interconnected by butting them against each other.
    [Show full text]
  • Nanoelectronics, Nanophotonics, and Nanomagnetics Report of the National Nanotechnology Initiative Workshop February 11–13, 2004, Arlington, VA
    National Science and Technology Council Committee on Technology Nanoelectronics, Subcommittee on Nanoscale Science, Nanophotonics, and Nanomagnetics Engineering, and Technology National Nanotechnology Report of the National Nanotechnology Initiative Workshop Coordination Office February 11–13, 2004 4201 Wilson Blvd. Stafford II, Rm. 405 Arlington, VA 22230 703-292-8626 phone 703-292-9312 fax www.nano.gov About the Nanoscale Science, Engineering, and Technology Subcommittee The Nanoscale Science, Engineering, and Technology (NSET) Subcommittee is the interagency body responsible for coordinating, planning, implementing, and reviewing the National Nanotechnology Initiative (NNI). The NSET is a subcommittee of the Committee on Technology of the National Science and Technology Council (NSTC), which is one of the principal means by which the President coordinates science and technology policies across the Federal Government. The National Nanotechnology Coordination Office (NNCO) provides technical and administrative support to the NSET Subcommittee and supports the subcommittee in the preparation of multi- agency planning, budget, and assessment documents, including this report. For more information on NSET, see http://www.nano.gov/html/about/nsetmembers.html . For more information on NSTC, see http://www.ostp.gov/cs/nstc . For more information on NNI, NSET and NNCO, see http://www.nano.gov . About this document This document is the report of a workshop held under the auspices of the NSET Subcommittee on February 11–13, 2004, in Arlington, Virginia. The primary purpose of the workshop was to examine trends and opportunities in nanoscale science and engineering as applied to electronic, photonic, and magnetic technologies. About the cover Cover design by Affordable Creative Services, Inc., Kathy Tresnak of Koncept, Inc., and NNCO staff.
    [Show full text]
  • Curriculum Vitæ of Gary H. Bernstein
    CURRICULUM VITÆ OF GARY H. BERNSTEIN Department of Electrical Engineering 275 Fitzpatrick Hall University of Notre Dame Notre Dame, IN 46556 (574) 631-6269 (office) (574) 277-0752 (home) [email protected] fax: (574) 631-4393 Education Ph.D. Arizona State University, Tempe, AZ. July 1987 (Advisor – David K. Ferry). M.S.E.E. Purdue University, West Lafayette, IN. May 1981. B.S.E.E. University of Connecticut, Storrs, CT. May 1979 (Honors Scholar). Experience Associate Director of the Center for Nano Science and Technology, University of Notre Dame (5/13). Frank M. Freimann Professor of Electrical Engineering (7/10). Co-Founder, Indiana Integrated Circuits, LLC (7/09). (www.indianaic.com). Professor, Department of Electrical Engineering, University of Notre Dame (5/98). Associate Chair, Department of Electrical Engineering, University of Notre Dame (1/99 to 8/06). Associate Professor, Department of Electrical Engineering, University of Notre Dame (5/93). Founding Director of the Notre Dame Nanofabrication Facility, Department of Electrical Engineering, University of Notre Dame (8/88 to 8/98). Assistant Professor, Department of Electrical Engineering, University of Notre Dame (8/88). Postdoctoral Fellow, Center for Solid State Electronics Research, Arizona State University (8/87 to 5/88). Research Associate, Arizona State University (11/83 to 8/87). Research Assistant, Motorola Semiconductor Research and Development Laboratories, Phoenix, AZ (5/83 to 8/83). Research Assistant, Los Alamos National Laboratory, Los Alamos, NM. Employment included DOE security clearance (Summers 79-80). Areas of Interest Nanofabrication using electron beam lithography, molecular electronics, microelectromechanical systems for integrated circuit packaging, and nanomagnetics. Honors and Awards 21.
    [Show full text]
  • Introduction from the Ieee 69Th Ectc Program Chair Nancy Stoffel
    INTRODUCTION FROM THE IEEE 69TH ECTC PROGRAM CHAIR NANCY STOFFEL The 69th Electronic Components and Technology Conference (ECTC) The Cosmopolitan of Las Vegas, Las Vegas, NV USA • May 28 - May 31, 2019 On behalf of the Program and Executive address the challenges and demands for sensors and packages for Committees, it is my pleasure to invite you autonomous driving along the value chain. On Thursday, May 30 to IEEE’s 69th Electronic Components and at 8 p.m., the IEEE EPS Seminar entitled “Roadmap of IC Packaging Technology Conference (ECTC), which will Materials to Meet Next-Generation Smartphone Performance be held at The Cosmopolitan, Las Vegas, Requirements” will be moderated by Yasumitsu Orii and Sheigenori Nevada, USA from May 28 - 31, 2019. This Aoki. premier international annual conference, Supplementing the technical program, ECTC also offers Professional sponsored by the IEEE Electronics Development Courses (PDCs) and Technology Corner exhibits. Packaging Society (EPS), brings together key Co-located with the IEEE ITherm Conference this year, the 69th stakeholders of the global microelectronic ECTC will offer eighteen PDCs, organized by the PDC Committee packaging industry, such as semiconductor companies, foundry chaired by Kitty Pearsall and Jeffrey Suhling. The PDCs will take place and OSAT service providers, equipment manufacturers, material on Tuesday, May 28 and are taught by distinguished experts in their suppliers, research institutions and universities, all under one roof. respective fields. The Technology Corner exhibits will showcase More than 1,400 people have attended ECTC in each of the last the latest technologies and products offered by leading companies three years. in the electronic components, materials, packaging, and services fields.
    [Show full text]
  • From the Mayor, City of Las Vegas, Nevada
    WELCOME FROM THE MAYOR, CITY OF LAS VEGAS, NEVADA From the Office of Mayor Carolyn G. Goodman CAROLYN G. GOODMAN MAYOR ECTC 2019 ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE LAS VEGAS, NEVADA MAY 28-31, 2019 Greetings: As Mayor, I am very pleased to welcome you to America’s most dynamic, entertaining, and intriguing city! You could not have chosen a better locale. I am convinced that once you get a taste of what the city has to offer, you will never want to leave. Las Vegas continues to capture the world's imagination as the city where anything is possible. With world-class hotels, award-winning restaurants, luxurious spas, fantastic shopping, the finest golf courses, and spectacular entertainment, Las Vegas remains one of the most electrifying destinations in the world. At its heart Las Vegas is all about making sure residents and visitors are well taken care of, treated courteously, and shown a great time. Beyond the neon of the fabulous Strip and the Fremont Street Experience, there is another Las Vegas--one in which we are building a world-class city featuring the best in arts, culture, sporting opportunities, and quality medical care. The Smith Center for the Performing Arts has set a high standard for art and culture in our city, and I encourage everyone to take in a concert or Broadway show at this magnificent venue. Regardless of your age, a must-visit spot is the children’s interactive Discover Museum adjacent to the Smith Center. Buzzing with excitement is the Fremont East Entertainment District, a place with an energy and enthusiasm through its taverns, restaurants, and music venues.
    [Show full text]
  • ABSTRACT KE, HAOTAO, 3-D Prismatic Packaging Methodologies
    ABSTRACT KE, HAOTAO, 3-D Prismatic Packaging Methodologies for Wide Band Gap Power electron- ics Modules (Under the direction of Dr. Douglas C. Hopkins) With the development of advanced Wide Band Gap (WBG) devices, power electronic sys- tems with higher frequency, temperature, and voltage are becoming the trend due to their higher efficiency and potentially lower system cost than Si counterpart. To fully utilized the advantage of WBG power devices for the application, improvement are greatly needed for power packaging mechanism. Efforts have been made by researchers in improving traditional power module layout and building new double sided power module. In this work, investigation into 3D methodology for power packaging is carried out. New 3D prismatic packaging concept is proposed for WBG power device, in which the devices are mounted vertically on the side wall of the module with 3D interconnect inside to achieve ele- vated electrical/thermal/mechanical performance. For validation of the 3D prismatic packaging methodology, different Additive Manufactur- ing (AM) processes have been evaluated for the compatibility with power electronic packag- ing. A 1200V/50A SiC half bridge power module is fabricated and tested. The result has been analyzed with simulation and discussed, together with possible future work in the area. © Copyright 2017 Haotao Ke All Rights Reserved 3-D Prismatic Packaging Methodologies for Wide Band Gap Power electronics Modules by Haotao Ke A dissertation submitted to the Graduate Faculty of North Carolina State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy Electrical Engineering Raleigh, North Carolina 2017 APPROVED BY: _______________________________ _______________________________ Douglas Hopkins Ola Harrysson Chair of Advisory Committee _______________________________ _______________________________ Jayant Baliga Subhashish Bhattacharya DEDICATION I dedicate this dissertation work to my beloved parents, for their guidance throughout my life.
    [Show full text]
  • Design and Experimental Evaluation of Compensated Bondwire
    International Journal of Microwave and Wireless Technologies, 2015, 7(3/4), 261–270. # Cambridge University Press and the European Microwave Association, 2015 This is an Open Access article, distributed under the terms of the Creative Commons Attribution licence (http://creativecommons.org/licenses/by/3.0/), which permits unrestricted re-use, distribution, and reproduction in any medium, provided the original work is properly cited. doi:10.1017/S1759078715000070 research paper Design and experimental evaluation of compensated bondwire interconnects above 100 GHz va’ clav valenta1, thomas spreng2, shuai yuan1, wolfgang winkler3, volker ziegler2, dragos dancila4, anders rydberg4 and hermann schumacher1 Different types of bondwire interconnect for differential chip-to-antenna and single-ended chip-to-chip interfaces are inves- tigated. Two differential compensation structures for various lengths of interconnects are designed and experimentally eval- uated using dedicated transmit and receive radar modules operating across a 110–156 GHz band. Measurement results demonstrate that a fractional bandwidth of 7.5% and a minimum insertion loss of 0.2 dB can be achieved for differential interconnects as long as 0.8 mm. Design and measurement results of an extremely wideband low-loss single-ended chip-to-chip bondwire interconnect that features 1.5 dB bandwidth from DC to 170 GHz and insertion loss of less than 1 dB at 140 GHz are presented as well. The results show that the well-established wire-bonding techniques are still an attract- ive solution even beyond 100 GHz. Reproducibility and scalability of the proposed solutions are assessed as well. Keywords: Hybrid and multi-chip modules, Circuit design and applications Received 27 October 2014; Revised 7 January 2015; Accepted 11 January 2015; first published online 30 March 2015 I.
    [Show full text]