DOCSLIB.ORG

Heterogeneous Integration Roadmap Update- INTEGRATED POWER ELECTRONICS (IPE) Technical Working Group

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Heterogeneous Integration Roadmap Update- INTEGRATED POWER ELECTRONICS (IPE) Technical Working Group Heterogeneous Integration Roadmap Update- INTEGRATED POWER ELECTRONICS (IPE) Technical Working Group MOVING HETEROGENEOUS POWER INTEGRATION FORWARD The IEEE Societies, and companies are sponsoring a new Roadmap focused on the critical packaging technologies that can maintain the pace of “More’s Law.” cpmt.ieee.org/technology/heterogeneous-integration-roadmap.html www.semi.org/en/heterogeneous-integration-roadmap Excerpts from presentation at IEEE Heterogeneous Integration Roadmap Symposium ECTC 2018 Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University Integrated Power Electronics (IPE) Co-Chair: Prof Douglas C Hopkins, Ph.D. North Carolina State University Dr Hopkins is engaged in research involving very high frequency, high density power electronics, organic-based circuits for power and energy systems, and true 3D electronic packaging. Co-Chair: Prof Patrick McClusky, Ph.D. University of Maryland Dr McClusky in engaged in research in high temperature and high power electronics packaging, materials, and reliability, and is General Chair of the 2018 3D-Power Electronics Integration and Manufacturing Symposium. Heterogeneous Integration Roadmap 2 Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University PERSPECTIVE Micro- Electronics Heterogeneous Power Integration Power Electronics Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University Profound Philosophical Distinction Processing Information Processing Energy “ETHEREAL” PROCESSING “PHYSICAL” PROCESSING Tremendous collaboration on Companies compete on the physical the physical requirements to “Energies”, i.e. electrical, mechanical, support competition in the thermal, chemical; in the forms of reliability, “Ethereal” world energy efficiency, size, weight, etc. HOW DO WE INTEGRATE POWER INTO THE NEW WORLD OF “SYSTEM IN PACKAGE” AND “HETEROGENEOUS INTEGRATION”? Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University Evolution in Microelectronics Packaging Courtesy of John Hunt ASE Group 19Sep’16 Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University Cell Phones Evolved……. Consumers wanted smaller devices Courtesy of John Hunt ASE Group 19Sep’16 Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University Advanced Packaging for Mobility Drivers Small, Thin for mobile applications Low cost for Consumer Products Good Electrical performance Size Cost Low power Integration of Functionality Solutions Wafer Level Chip Scale Package Performance Fan Out Wafer Level Package Fan Out System in Package (SiP) Courtesy of John Hunt ASE Group 19Sep’16 Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University Driver for Wafer Level Packages & Fanout iPhone Evolution 3013 13 12 12 25 11 11 20 10 10 15 WLCSPs 9 9 Thickness (mm) Thickness Thickness (mm) Thickness 10 8 8 5 7 7 06 6 1 /2007 3GS /2009 4S /2011 5 /2012 5S /2013 6 /2014 6+ /2014 iPhone Model/year WLPsThicknessThickness iPhone 1 iPhone 3GS iPhone 4S iPhone 5 iPhone 5S iPhone 6 iPhone 6 Plus 2007 2009 2011 2013 2013 2014 2014 2 WLPs 4 WLPs 7 WLPs 11+ WLPs 22 WLPs 26+ WLPs 26+ WLPs Shown to scale Source: TechSearch International, Inc., adapted from TPSS. Courtesy of John Hunt ASE Group 19Sep’16 Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University Revolution in Packaging Packaging Technologies ~ 2000 0 £ Mechanical Processes £ + Chemical Processes l Grinding l Wafer Processing l l Sawing Sputtering l Plating l Die Bonding l Etching l Wire Bonding l Photo Processing l Molding u Photoresists l Singulation u Polymers l Plasma Courtesy of John Hunt ASE Group 19Sep’16 Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University State of Art in Power Planar 2D power packaging technology Flex circuit structure POL package, SKiN package, etc. Embedded structure AT&S GaNPX, PCB embedded, etc. Sandwiched structure Planar Bond All package, etc. ABB Stacked DBC [1] Planar Bond All[8] GaNPX package[7] Power Overlay SKiN module [5] PCB embedded module[6] package [4] Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University State of Art in Power 3D power packaging technology Device level Quilt dies, stacked / vertical dies Module level 3D CSP, Power chip on chip, 3D power circuit . Quilt packaging[9] Inner post SiC MOSFET & Diodes 3D Power module[10] Orthogonal DBC Substrate Stacked device[13] 3D CSP module[12] Excerpt from Dissertation of Dr Haotao Key, 2018 Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University But, Power Needs a Change And needs to take more cues from microelectronics Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University Limitation of level-0 packaging Source: Mark Papermaster, AMD CTO. GSA Europe, April 6, 2017 Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University Limitation… Cost is raising for digital Source: Mark Papermaster, AMD CTO. GSA Europe, April 6, 2017 “For the past 50 years, the cheapest and easiest way to increase complexity was to shrink the feature size and grow the wafer diameter.(That was he classic Moore’s Law) Now there is a tradeoff. We will do the things that are most economic for the capabilities we want. Some of those will keep us going with smaller and smaller feature sizes almost forever. But the most economical tradeoff is likely to be a combination of better system engineering, multi chip packaging, and a whole variety of other techniques to keep advancing the capabilities in the most cost effective way.” Wally Rhines, Chairman Mentor Graphics. Source: Semiconductor Engineering, Ed Sperling, April 20 2017 - - Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University DEFINITION Heterogeneous Integration The integration of separately manufactured components into a higher level assembly (SiP) that in the aggregate provides enhanced functionality and improved operating characteristics. SiP through Heterogeneous Integration Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University SYSTEM in PACKAGE (SiP) through HI Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University DEFINITION Heterogeneous Integration of Power (HIP) HIP is defined as the integration of separately manufactured power electronic components and subsystems into higher-level assemblies (SiP, PCB/Substrate- embedded systems) that in the aggregate provide enhanced functionality and improved operating characteristics. Power passives High current Inductors Low profile passives Power distribution planes Advanced materials PMU Heat spreaders, heat sinks Active cooling systems Power semiconductors SiP through Heterogeneous EMI shielding Integration Unique design architectures Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University How Do We Integrate Heterogeneous Power ? 1 2 3 0 Power Distribution On-Chip Peripheral On-Chip Distributed uses SiP Pkg & Mfg Power Distribution Power Conversion Discrete Power is technologies being mapped uses “Component” Pkg uses “Component” Pkg & through the PSMA in to distribute power & Mfg technologies Mfg technologies their “Embedded from Discrete Power to create power to create distributed Component Study.” converters conversion at the power conversion within interface with the SiP the Component Power Conv Conv Power Conv Power Conv Power Power Conv Power Conv Conv Power Power Conv Not the HIR-IPE focus, but will benefit from our technologies Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University Complimentary Technologies HIP PSiP HIP SiP Heat sink INDUCTOR RE-DISTRIBUTION LAYER SUBSTRATE Technology EXCHANGE 1mm SiP Substrate Discrete Power Integrated Power Integration challenge will be in “planarization” of power Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University What has “Power” been looking at? Heterogeneous Power Integration (HPI) has begun Heterogeneous Integration Roadmap Technical Working Group – Integrated Power Electronics [email protected] North Carolina State University The PSMA 2015 Tech Report (334 pp) 1. Embedding in PCBs & Inorganic Substrates 2. High Temp Die-Attach & High-Lead Solder 3. Thermal Management TECHNOLOGY REPORT 4. Packaging Technologies Current Developments in 3D Packaging 5. Interposers With Focus on Embedded Substrate Technologies
Load more

Recommended publications
  • Fenwick Employment Brief
    Fenwick Employment Brief December 10, 2008 Victor Schachter Editor 650.335.7905 Mary Wang Contributor 650.335.7154 planning a workforce reduction: a brief checklist In current economic times, more and more companies are turning to “reductions in force” or “RIFs.” While RIFs can provide both short and long-term economic benefits, they are also among the most difficult events an attorney or human resources professional must oversee because of the emotional and economic impact they will have on employees, the myriad of complex laws that must be observed, and the enormous amount of work that is usually required in a very short amount of time. Thoughtful and careful planning is important not only to ensure compliance with legal requirements, but also help to minimize the adverse effects of a workforce reduction, further reducing the risk of lawsuits. The following checklist provides some practical guidance to assist employers in implementing a reduction in force and to minimize legal risks. This checklist does not address all the possible issues arising from a RIF and we encourage you to consult with counsel as part of your planning and implementation of a RIF. planning and construction of a layoff n Identify triggering events for layoff n Identify possible layoff alternatives (e.g., pay cuts, schedule reductions, temporary shutdowns and vacation/PTO drawdown, reduction of contractor headcount) n Identify affected sites and estimate number of affected employees for WARN and other analyses n Establish the RIF management team: Identify the individuals
    [Show full text]
  • Preliminary Injunctions in Non-Compete Cases
    G THE B IN EN V C R H E S A N 8 8 D 8 B 1 AR SINCE WWW. NYLJ.COM ©2009 INCISIVE MEDIA US PROPERTIES, LLC VOLUME 242—NO. 65 THURSDAY, OCTOBER 1, 2009 SOUTHERN DISTRICT CIVIL PRACTICE ROUNDUP Expert Analysis Preliminary Injunctions In Non-Compete Cases or employees who possess confiden- The Second Circuit has not yet sought to tial business information, the threat re-tool the longstanding standard operative of a preliminary injunction can make in this circuit for entry of a preliminary Fchanging jobs a highrisk proposition. injunction,7 and we do not read Winter as To prevent, or at least forestall, the loss of overruling the Second Circuit’s approach. confidential information to the competi- We do note, however, that Winter could be tion, employers occasionally seek prelimi- read to require consideration of the private nary injunctions, regarded as “one of the By ByAnd equities as well as the public interest in most drastic tools in the arsenal of judicial HowardEdward M.B. TheodoreJudith L. A. every case, including where the plaintiff remedies,”1 to enjoin departing employees EpsteinSpiro KeyesMogul has established both irreparable injury from working for competitors. The decision and a likelihood of success on the merits. whether to grant such relief generally turns A party must demonstrate either (1) a likeli- Many cases already consider these factors, on resolution of the tension between pro- hood of success on the merits of its claim or and thus, as a practical matter, Winter is tecting proprietary business information (2) “sufficiently serious” questions making unlikely to result in a significant change in on the one hand, and the strong public the merits “fair ground for litigation” plus Second Circuit law.
    [Show full text]
  • PART I: People & Strategy
    By Ken Luskin [email protected] October 28, 2014 PART I: People & Strategy The Brilliance of Steve Jobs was in building a team of geniuses Virtually everyone in the world knows that Steve Jobs was the driving force behind the success of Apple. Unfortunately, few of them understand that without the team of technical gurus Jobs assembled, his visions would not have become reality. Without a Microprocessor Brain, the iPhone would not exist Inside every “smart” computing device is a microprocessor, considered the brains of the device. When Jobs was creating what is now known as the iPhone, he needed a special microprocessor, which could make it through the day without draining the battery. Jobs first approached Intel, the company that was supplying the microprocessors for the entire MAC line. Intel was not interested in supplying a relatively low cost mobile chip, because the bean counters and FAB guys had no vision. So, Jobs built a team of top mobile microproprocessor engineers, licensed the ARM architecture, and created a chip that became the brains of the iPhone and iPad. Apple buys P.A. Semiconductor in 2008 to keep Apple’s microprocessors on the cutting edge With this acquisition Apple received a group of highly innovative engineers, including ex AMD employee Jim Keller. From a VentureBeat article: “Keller spearheaded the development of Apple’s custom mobile processors — including the A4 in the iPhone 4, the A5 in the iPhone 4S and iPad 2, and the A5X in the new iPad — all of which have managed to keep Apple’s mobile devices on the cutting edge.
    [Show full text]
  • Development of 3-D Printed Hybrid Packaging for Gaas-MEMS
    University of South Florida Scholar Commons Graduate Theses and Dissertations Graduate School June 2018 Development of 3-D Printed Hybrid Packaging for GaAs-MEMS Oscillators based on Piezoelectrically-Transduced ZnO-on-SOI Micromechanical Resonators Di Lan University of South Florida, [email protected] Follow this and additional works at: https://scholarcommons.usf.edu/etd Part of the Electrical and Computer Engineering Commons Scholar Commons Citation Lan, Di, "Development of 3-D Printed Hybrid Packaging for GaAs-MEMS Oscillators based on Piezoelectrically-Transduced ZnO- on-SOI Micromechanical Resonators" (2018). Graduate Theses and Dissertations. https://scholarcommons.usf.edu/etd/7690 This Dissertation is brought to you for free and open access by the Graduate School at Scholar Commons. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Scholar Commons. For more information, please contact [email protected]. Development of 3-D Printed Hybrid Packaging for GaAs-MEMS Oscillators based on Piezoelectrically-Transduced ZnO-on-SOI Micromechanical Resonators by Di Lan A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Jing Wang, Ph.D. Thomas M. Weller, Ph.D. Arash Takshi, Ph.D. Rasim Guldiken, Ph.D. Shengqian Ma, Ph.D. Date of Approval: June 14, 2018 Keywords: Microelectromechanical Systems, Additive Manufacturing, MMIC, Microfabrication Copyright © 2018, Di Lan DEDICATION To my wife, my parents, my advisors, my friends ACKNOWLEDGMENTS First, I would like to state my greatest appreciation to my major advisor and Professor Dr.
    [Show full text]
  • Apple: Iphone 4´S Antennagate
    Corporate Communication Master of International Trade, Transport and Communication University of Cantabria Apple: iPhone 4´s Antennagate The launch of the new iPhone 4 from Apple caused a huge stir all over the world, particularly in the United States in June 2010. The features improvement of the new smartphone went into the background when signal problems were detected. The simple answer that the company gave to their clients only increased the controversy. Finally, Apple had to apologize in public and compensate their customers. Apple Inc. Apple Inc. is an American multinational corporation headquartered in Cupertino, California, that designs, develops, and sells consumer electronics, computer software and personal computers. The company was founded on April 1, 1976, by Steve Jobs, Steve Wozniak and Ronald Wayne to sell a personal computer kit called Apple I, a computer unassisted designed by Wozniak. Since then, Apple has suffered many changes and currently it is the world's second-largest information technology company by revenue after Samsung Electronics and the world's third-largest mobile phone maker after Samsung and Nokia1. Fortune magazine named Apple the most admired company in the United States in 2008, and in the world from 2008 to 2012. Apple's marketing strategy is powerful and has made them the success story they are. They use unique marketing techniques as understanding and serving the customer better than anyone else, making sure every little thing serves always and everywhere. Apple is not limited to cover only the need of customers, they also are capable of creating demand with innovating products that does not exist on market.
    [Show full text]
  • Advanced Ic Packaging Technologies, Materials, and Markets 2015 Edition
    ADVANCED IC PACKAGING TECHNOLOGIES, MATERIALS, AND MARKETS 2015 EDITION A Strategic Report Covering the Latest Technologies in IC Packaging, Enabling Portable and Other Electronics Report Coverage Report Highlights Stacked Packages Industry Outlook System-in-Packages Market Analysis and Forecasts, Interconnection Technologies 2013–2019 Through-Silicon-Vias (TSV) Multichip Packaging 2.5D and 3D Integration Technology Trends Multi-row QFNs Key Application Forecasts Fan-out WLPs Company Profiles New Venture Research A Technology Market Research Company 337 Clay St., Suite 101 [email protected]/ Nevada City, CA 95959 www.newventureresearch.com/ Tel: (530) 265-2004 Fax: (530) 265-1998 Advanced IC Packaging Technologies, Materials, and Markets, 2015 Edition Synopsis The demand for consumer electronics and mobile QFNs and WLPs), as well as advanced communications devices that keep us connected is multicomponent packages (PoPs, PiPs, and MCMs). driving electronics manufacturers to deliver ever-more Forecasts include multichip IC packaging units, compact and portable electronic systems. Today's revenue, prices, die usage and applications. users ask for products with more functionality, added performance, higher speed, and smaller form factors. Chapter 6: System in Package (SiP) Solutions & Advances in IC packaging technologies are providing Substrate Materials, presents a more in-depth look at solutions to meet these demands through a variety of the evolving multicomponent packages, and presents techniques that result in ICs that are more powerful and key market trends alongside forecasts of units and provide greater functionality, while fitting into ever revenue. This chapter also examines the substrate smaller and more highly integrated form factors. materials and embedded components used in SiP Multichip packages are on the leading edge of silicon assembly.
    [Show full text]
  • Integrating MEMS and Ics
    OPEN Microsystems & Nanoengineering (2015) 1, 15005; doi:10.1038/micronano.2015.5 © 2015 IECAS All rights reserved 2055-7434/15 www.nature.com/micronano Review Article Integrating MEMS and ICs Andreas C. Fischer, Fredrik Forsberg, Martin Lapisa, Simon J. Bleiker, Göran Stemme, Niclas Roxhed and Frank Niklaus The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the ‘More-Than- Moore’ paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated.
    [Show full text]
  • 2006 Technical Program
    International Microelectronics Assembly and Packaging Society New England Chapter 43rd Annual Symposium Technical Sessions - May 3, 2016 Symposium’s Technical Chairs Welcome Letter We’d like to welcome everyone to the 43nd Annual New England iMAPS Symposium! Thanks to all the Session Chairs we’ve compiled an engaging program of technical talks on many of today’s hot topics that will peak the interest of every Attendee. We hope you take full advantage of the opportunity to interact with the speakers and each other in a learning environment that’s only available at this unique one day symposium. Below is a brief summary to help you on your way and don’t forget to spend time in the exhibit hall, because after all without the support of the exhibitors this day wouldn’t be possible. Enjoy!!! Dmitry Marchenko Dr. Parshant Kumar RF and Microwave - Innovations and Emerging Technologies: This session is all about the innovations and emerging technologies that are driving RF and microwave packaging industry. Returning by popular demand and includes talks from industry leaders such as CST, Ametek and Draper. The topics cover issues like EM coupling between buck converters and antennas, Low Loss Additive Materials and design challenges of millimeter-wave semiconductor packaging. 3D and Beyond: This session covers the latest advancements in 2.5/3D technology. A Novel way to produce 3D chip assemblies called Quilt will be presented by IIC. Presentation by Tufts will describe liquid metal interconnects use in studies of animals and soft robots. You will learn about the latest Draper work on Printed transceivers.
    [Show full text]
  • Ilounge 2010 Buyers' Guide
    ©2012 SwitchEasy Limited, All Rights Reserved. U.S. and International Patents pending. iPhone5 is registered trademarks of Apple Computer Inc. 2013 Welcome to the Guide. IPHONE + IPOD BUYERS’ GUIDE After a slow and uneven 2011, Apple roared back in 2012, launching a wide array of significantly redesigned devices. The iPod, iPhone, and iPad families all saw major screen revisions, including two taller iPods, one elongated iPhone, and a quadrupled-resolution iPad. Then, just before the holidays, Apple debuted the 7.9” iPad mini, and replaced the 9.7” iPad again - just because it could. Going into 2013, the lineup looks almost completely different than it did a year earlier, except for three iPods that have been left largely untouched. If you’re reading this Guide, you’re probably looking for buying advice, and that’s why we’re here - to give you an impartial and honest look at the world of Apple devices, accessories, apps, and games. Following our tradition, iLounge’s editors have spent the past year testing hundreds of new products, selecting the best and most noteworthy ones for our new 2013 iPhone + iPod Buyers Guide. Independently assembled, our Guide is a sight to behold. We hope you enjoy it. The 2013 iPhone + iPod Buyers’ Guide is published by iLounge, Inc. and is Copyright © 2004-2012. All rights reserved. No part of this guide may be reproduced, sold, rented, or transmitted in any form, or by any means whatsoever, without the prior written consent of the publisher. Unauthorized sale of this guide is prohibited, and by accessing this guide, you agree not to violate these restrictions.
    [Show full text]
  • Assembly and Packaging
    INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION ASSEMBLY AND PACKAGING THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009 TABLE OF CONTENTS Scope....................................................................................................................................1 Difficult Challenges................................................................................................................2 Single Chip Packaging ..........................................................................................................2 Overall Requirements......................................................................................................................2 Electrical Requirements ...............................................................................................................................3 Cross Talk ....................................................................................................................................................3 Power Integrity .............................................................................................................................................3 Thermal Requirements.................................................................................................................................3 Hot spots ......................................................................................................................................................4 Mechanical Requirements............................................................................................................................4
    [Show full text]
  • Quilt Packaging: a Novel High Speed Chip-To-Chip
    QUILT PACKAGING: A NOVEL HIGH SPEED CHIP-TO-CHIP COMMUNICATION PARADIGM FOR SYSTEM-IN-PACKAGE A Dissertation Submitted to the Graduate School of the University of Notre Dame in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Qing Liu, B.E., M.E., M.S.E.E. Gary H. Bernstein, Director Graduate Program in Electrical Engineering Notre Dame, Indiana December 2007 © Copyright by QING LIU 2007 All Rights Reserved QUILT PACKAGING: A NOVEL HIGH SPEED CHIP-TO-CHIP COMMUNICATION PARADIGM FOR SYSTEM-IN-PACKAGE Abstract by Qing Liu As state-of-the-art transistor features continue to shrink and the incorporation of high-k, low-k isolation dielectric materials and strained and SiGe layers on silicon becomes common, chip density and performance are improved. However, system performance has not kept up with the pace especially at multi-GHz clock rates. The bottleneck is packaging. Conventional packaging techniques require high driving current and large in-die area for bonding pads, and provide limited bandwidth. As a result, several technologies, such as system-on-chip, system-in-packaging and system-on-packaging, have been actively pursed to meet the demands of low power, high I/O counts and fast chip-to-chip communication. Here, we present a novel packaging technique, Quilt Packaging (QP), for system-in-package. QP uses microelectromechanical systems (MEMS) inspired fabrication techniques to form Qing Liu contacts along the vertical edge facets of the integrated circuits (ICs) during the back-end-of-line process, enabling the ICs to be interconnected by butting them against each other.
    [Show full text]
  • Nanoelectronics, Nanophotonics, and Nanomagnetics Report of the National Nanotechnology Initiative Workshop February 11–13, 2004, Arlington, VA
    National Science and Technology Council Committee on Technology Nanoelectronics, Subcommittee on Nanoscale Science, Nanophotonics, and Nanomagnetics Engineering, and Technology National Nanotechnology Report of the National Nanotechnology Initiative Workshop Coordination Office February 11–13, 2004 4201 Wilson Blvd. Stafford II, Rm. 405 Arlington, VA 22230 703-292-8626 phone 703-292-9312 fax www.nano.gov About the Nanoscale Science, Engineering, and Technology Subcommittee The Nanoscale Science, Engineering, and Technology (NSET) Subcommittee is the interagency body responsible for coordinating, planning, implementing, and reviewing the National Nanotechnology Initiative (NNI). The NSET is a subcommittee of the Committee on Technology of the National Science and Technology Council (NSTC), which is one of the principal means by which the President coordinates science and technology policies across the Federal Government. The National Nanotechnology Coordination Office (NNCO) provides technical and administrative support to the NSET Subcommittee and supports the subcommittee in the preparation of multi- agency planning, budget, and assessment documents, including this report. For more information on NSET, see http://www.nano.gov/html/about/nsetmembers.html . For more information on NSTC, see http://www.ostp.gov/cs/nstc . For more information on NNI, NSET and NNCO, see http://www.nano.gov . About this document This document is the report of a workshop held under the auspices of the NSET Subcommittee on February 11–13, 2004, in Arlington, Virginia. The primary purpose of the workshop was to examine trends and opportunities in nanoscale science and engineering as applied to electronic, photonic, and magnetic technologies. About the cover Cover design by Affordable Creative Services, Inc., Kathy Tresnak of Koncept, Inc., and NNCO staff.
    [Show full text]