INTRODUCTION FROM THE IEEE 69TH ECTC PROGRAM CHAIR NANCY STOFFEL

The 69th Electronic Components and Technology Conference (ECTC) The Cosmopolitan of Las Vegas, Las Vegas, NV USA • May 28 - May 31, 2019

On behalf of the Program and Executive address the challenges and demands for sensors and packages for Committees, it is my pleasure to invite you autonomous driving along the value chain. On Thursday, May 30 to IEEE’s 69th Electronic Components and at 8 p.m., the IEEE EPS Seminar entitled “Roadmap of IC Packaging Technology Conference (ECTC), which will Materials to Meet Next-Generation Smartphone Performance be held at The Cosmopolitan, Las Vegas, Requirements” will be moderated by Yasumitsu Orii and Sheigenori Nevada, USA from May 28 - 31, 2019. This Aoki. premier international annual conference, Supplementing the technical program, ECTC also offers Professional sponsored by the IEEE Electronics Development Courses (PDCs) and Technology Corner exhibits. Packaging Society (EPS), brings together key Co-located with the IEEE ITherm Conference this year, the 69th stakeholders of the global microelectronic ECTC will offer eighteen PDCs, organized by the PDC Committee packaging industry, such as companies, foundry chaired by Kitty Pearsall and Jeffrey Suhling. The PDCs will take place and OSAT service providers, equipment manufacturers, material on Tuesday, May 28 and are taught by distinguished experts in their suppliers, research institutions and universities, all under one roof. respective fields. The Technology Corner exhibits will showcase More than 1,400 people have attended ECTC in each of the last the latest technologies and products offered by leading companies three years. in the electronic components, materials, packaging, and services fields. More than one hundred Technology Corner exhibits will be At the 69th ECTC, more than 360 technical papers are scheduled open Wednesday and Thursday starting at 9 a.m. ECTC also offers to be presented in thirty-six oral sessions and five interactive attendees numerous opportunities for networking and discussion presentation sessions, including one interactive presentation session with colleagues during coffee breaks, daily luncheons, and nightly exclusively featuring papers by student authors. The oral sessions will receptions. feature selected papers on key topics such as -level and fan-out Whether you are an engineer, a manager, a student, or an executive, packaging, 2.5D, 3D and heterogeneous integration, interposers, ECTC offers something unique for everyone in the microelectronics advanced substrate, assembly, materials modeling, reliability, packaging packaging and components industry. I invite you to make your plans for harsh conditions, power packaging, interconnections, packaging now to join us for the 69th ECTC and be a part of all the exciting for high speed and high bandwidth, photonics, flexible and printed technical and professional opportunities. I also take this opportunity electronics. Interactive presentation sessions will showcase papers to thank our sponsors, exhibitors, authors, speakers, PDC instructors, in a format that encourages more in-depth discussion and interaction session chairs, and program committee members, as well as all the with authors about their work. Authors from over twenty countries volunteers who help make the 69th ECTC a success. I look forward are expected to present their work at the 69th ECTC, covering to meeting you in Las Vegas, Nevada May 28 –31, 2019. ongoing technology development within established disciplines Nancy Stoffel or emerging topics of interest for our industry such as additive 69th ECTC Program Chair manufacturing, heterogeneous integration, flexible and wearable General Electric Research electronics. Email: [email protected] ECTC will also feature six special sessions with invited industry experts covering several important and emerging topic areas. On Tuesday, May 28 at 10 a.m., W. Hong Yeo and Mikel Miller will chair Index ECTC Registration ...... 3, 32, 33 a special session covering “Transient Electronics: A Green Revolution General Information ...... 3 for Packaging.” On the same day at 2 p.m., Rena Huang and Soon Hotel Information ...... 3, 32 Jang will chair a session titled “Photonics on the Cutting-Edge of Conference Overview ...... 4 Technology Evolution.” Tuesday evening will also include the ECTC 2019 Photonics Special Session ...... 5 Panel Session at 7:30 p.m. chaired by IEEE EPS President Avi Bar- 2019 ECTC Special Session ...... 5 Cohen and Karlheinz Bock, where young researchers will share their 2019 ECTC Panel Session...... 5 visions of future packaging technologies and participate in discussions 2019 ECTC Plenary Session ...... 5 with experts in the field. ECTC/ITherm Young Professionals Panel & Reception ...... 5 ECTC Luncheon Keynote Speaker...... 6 This conference will feature a Women’s Panel and Reception, jointly 2019 IEEE EPS Seminar...... 6 organized by ECTC and ITherm, on Wednesday, May 29, 2019 at 2019 ECTC/ITherm Women’s Panel and Reception...... 6 6:30pm. This year, panelists will share their perspectives on effective ECTC Luncheon Keynote Speaker...... 7 programs and strategies to enhance the participation of women in Luncheons and Receptions ...... 7 engineering throughout career progression, from the university to the Executive and Program Committees ...... 8-9 executive suite. The panel will be chaired by Kristina Young-Fisher Professional Development Courses ...... 10-15 and Cristina Amon. On the same day at 7:30 p.m., Tanja Braun Area Attractions ...... 15 will chair the ECTC Plenary Session titled “Sensors and Packaging Program Sessions ...... 16-31 for Autonomous Driving.” In this plenary session, experts will 2019 Technology Corner Exhibits ...... 32

2 69th ECTC ADVANCE REGISTRATION

Advance Registration Hotel Accommodations Online registration is available at www.ectc.net. For Rooms for ECTC attendees have been reserved at The more information on registration rates, terms, and Cosmopolitan of Las Vegas. The special conference rate for a single/ conditions see page 32. double occupancy room is: Register early … save US$100 or more! All registrations received US$166.00 per night after May 2, 2019 will be considered Door Registrations. Those who register in advance can pick up their registration packets at the ECTC This price includes single or double occupancy in one room. There Registration Desk on the 4th floor in the Belmont Commons. will be an upcharge of $30 per person if occupancy includes more than two individuals. On-Site Registration Schedule Please note these rooms are on a first come, first served basis. If the Registration will be held on the 4th floor in the Belmont Commons. conference rate is no longer available, attendees will be offered the next best price available. Monday, May 27, 2019 3:00 p.m. – 5:00 p.m. Tuesday, May 28, 2019 6:45 a.m. – 5:00 p.m.* Room reservations must be made through our website at http:// *6:45 a.m. – 8:00 a.m.: Morning PDCs & morning ECTC Special Session only www.ectc.net/location/index.cfm or directly with the hotel. The Wednesday, May 29, 2019 6:45 a.m. – 4:00 p.m. conference rate of $166.00/night is available until April 26, 2019, or Thursday, May 30, 2019 7:30 a.m. – 4:00 p.m. until the room block runs out, whichever comes first. All reservations Friday, May 31, 2019 7:30 a.m. – 12:00 Noon made after the cutoff date of April 26, 2019 at 5 p.m. Pacific Time, or after the room block is filled, will be accepted on a space and The above schedule for Tuesday will be rigorously enforced to rate availability basis. If you need to cancel a reservation, prevent students from being late for their courses. please do so AT LEAST 5 days before arrival for a full refund. Each hotel guest is subject to all hotel rules and regulations. Check-in time: 3 p.m. & check-out time: 12 noon local time. General Information Conference organizers reserve the right to cancel or change the Note about Hotel Rooms program without prior notice. The meeting spaces within the Attendees should note that only reputable sites should be used to Cosmopolitan of Las Vegas, as well as the ECTC, are both smoke- book a hotel room for ECTC. Be advised that you may receive free environments. emails about booking a hotel room for ECTC from third-party companies. These emails and sites are not to be trusted. The only Loss Due to Theft formal communication ECTC will convey about hotel rooms will Conference management is not responsible for loss or theft of come in the form of ECTC e-blasts or ECTC emails from our personal belongings. Security for each individual’s belongings is the Executive Committee. ECTC’s only authorized site for reserving a individual’s responsibility. room is through our website (www.ectc.net). You may, however, use other trusted sites that you have personally used in the past to ITherm 2019 book travel. Please be advised, there are scam artists out there, and ITherm will be co-located with ECTC 2019 at The Cosmopolitan if it’s too good to be true, it likely is. Should you have any questions of Las Vegas. For more information on ITherm conference details, about booking a hotel room, please contact ECTC staff at: lrenzi@ please visit their website at: https://www.ieee-itherm.net/itherm/ renziandco.com conference/home Transportation Services ECTC Sponsors There is no complimentary transportation to and from the airport to The Cosmopolitan of Las Vegas. Please check with the service desk With 68 years of history and experience behind us, ECTC is at the airport on the various forms of transportation including taxis, recognized as the premier semiconductor packaging conference buses, and private car services. and offers an unparalleled opportunity to build relationships with more than 1,500 individuals and organizations committed to driving innovation in semiconductor packaging. We have a limited number of sponsorship opportunities in a variety of packages to help get your message out to attendees. These include Platinum, Gold, Silver, Program, and several other sponsorship options that can be customized to your company’s interest. If you would like to enhance your presence at ECTC and increase your impact with a sponsorship, please take a look at our sponsorship brochure on the website www.ectc.net under “Sponsors.” To sign-up for sponsorship or to get more details, please contact Wolfgang Sauter at [email protected] or +1-802-922-3083.

3 CONFERENCE OVERVIEW

May 28, 2019 “Future (Visions) of Electronics ECTC/ITHERM Women’s IEEE EPS Seminar Morning Professional Packaging” Panel and Reception 8:00 p.m. - 9:30 p.m. Development Courses 6:30 p.m. - 7:30 p.m. “Roadmap of IC Packaging 8:00 a.m. - 12:00 p.m. May 29, 2019 “Unleashing the Power of Materials to Meet Next- 1. Achieving High Reliability of Lead- Technical Sessions Diversity in our Workforce” Generation Smartphone Free Solder Joints - Materials Performance Requirements” Considerations 8:00 a.m. - 11:40 a.m. ECTC Plenary Session 2. Introduction to Fan-Out Wafer 1. Wafer Level Fan-Out Process 7:30 p.m. - 9:00 p.m. May 31, 2019 Level Packaging Integration “Sensors and Packaging for Technical Sessions Autonomous Driving” 3. Fundamentals of Glass Technology 2. Next Generation Wirebonding 8:00 a.m. - 11:40 a.m. and Applications for Advanced 25. Wafer Level Packaging Fan- Semiconductor Packaging and Die Attach/Sintering May 30, 2019 4. Moore’s Law for Packaging to 3. Re-Distribution Layer and Technical Sessions In-Fan-Out Structure and Materials replace Moore’s Law for ICs Additive Manufacturing 8:00 a.m. - 11:40 a.m. 5. Polymers and Nanocomposites for 13. Technologies Enabling 3D and 26. High-Speed Signaling for HPC 4. Advancements in Automotive Electronic and Photonic Packaging Heterogeneous Integration and Memory 6. Fundamentals of RF Design and and Power Devices 14, Fine Pitch Solder-Free Bonded 27. Advanced Biosensors and Fabrication Processes of Fan-Out 5. Bonding Manufacturing Interconnects Bioelectronics Wafer/Panel Level Packages and Technologies 15. High-Bandwidth Packaging 28. Embedded Substrates and Interposers 16. Advanced Materials for High- Integrated Technologies 7. Solving Package Failure 6. Emerging Flexible Hybrid Speed Electronics Electronics 29. Electromigration and Mechanisms for Improved 17. Materials and Design for Innovative Reliability Test Reliability Reliability of Next Generation Methods 8. Characterization of Advanced Interactive Presentation Packages EMCs for FO-WLP, Sessions 37 & 38 18. Warpage and Material 30. Assembly and Process Heterogeneous Integration, and Performance Modeling Automotive Electronics 9:00 a.m. - 11:00 a.m. 9. Integrated Thermal Packaging and 2:00 p.m. - 4:00 p.m. Interactive Presentation Student Interactive Reliability of Power Electronics Sessions 39 & 40 Presentations Session 41 Technical Sessions 8:30 a.m. - 10:30 a.m. Afternoon Professional 9:00 a.m. - 11:00 a.m. Development Courses 1:30 p.m. - 5:10 p.m. 2:00 p.m. - 4:00 p.m. Technical Sessions 7. Advances in 1:15 p.m. - 5:15 p.m. Technical Sessions 1:30 p.m. - 5:10 p.m. 10. Flip Chip Technologies Technology 11. Wafer-Level Chip- 1:30 p.m. - 5:10 p.m. 31. Automotive and Power 8. Material and Process Trends in 19. MEMS, Sensors, & IoT Scale Packaging (WCSP) Packaging 20. Fanout and Heterogeneous Fundamentals FOWLP & PLP 32. Power and Panel Assembly Integration 12. Flexible Hybrid Technologies - 9. Wearables and Thin Package 33. Thermal-mechanical Simulation 21. 5G, mm-Wave and Antenna- Manufacturing and Reliability for Fan-Out, Flip Chip, and Reliability & CPI in-Package 13. Fan-Out Wafer/Panel 10. Dicing and Encapsulation WLCSP Level Packaging and 3D IC 22. Advanced Substrates and Technologies Interconnect Technology 34. Emerging Materials and Heterogeneous Integration Processing 14. Polymers for Wafer Level 11. Automotive and Harsh 23. High Bandwidth 3D & Photonics Integration 35. New Interconnects for Packaging Environment Reliability 24. Advancements in Solder Joint Package Scaling 15. Reliability Mechanics and 12. Advanced Photonic Devices & Modeling for IC Packaging - Characterization and Reliability 36. RF & Power Components and Theory, Implementation, and Packaging Evaluation Modules Practices 16. Robust Electronics for Automotive Applications Session Summary by Interest Area Including Autonomous Driving 17. From Wafer to Panel Level 3D/TSV Topics High-Speed, Wireless & Components Packaging S13, S23 S15, S21, S26, S36 18. Electronics Cooling Interconnections Technologies for Handheld Fan-Out Topics Devices, Computing, and High S1, S8, S20, S25, S33 S2, S14, S20, S23, S35 Power Electronics Materials & Processing Packaging Technologies ECTC Special Session S1, S3, S7, S13, S19, S25, S31 S4, S8, S16, S22, S34 9:30 a.m. - 11:30 a.m. Thermal/Mechanical Simulation & “Transient Electronics: A Green Applied Reliability Characterization Revolution for Packaging?” S11, S17, S24, S29, S34 S9, S18, S30, S33 Photonics Special Session Assembly & Manufacturing Technology Photonics 2:00 p.m. - 3:30 p.m. S5, S10, S28, D32 “Photonics on the Cutting-Edge of S12, S23 Technology Evolution” Emerging Technologies Interactive Presentations ECTC Panel Session S3, S6, S27 S37, S38, S39, S40, S41 7:45 p.m. - 9:15 p.m.

4 2019 Special Session 2019 Young Professional Networking Panel Transient Electronics: A Green Revolution for Tuesday, May 28,2019, 7:00 p.m. - 7:45 p.m. Packaging? Chair: Yan Liu, Medtronic Tuesday, May 28, 2019, 9:00 a.m. – 11:30 a.m. Panelists: EPS Board of Governors members: Avi Bar-Cohen, Chris Bailey, Karlheinz Bock, Alan Huffman, Sam Karikalan, Beth Keser, Chairs: W. Hong Yeo - Georgia Institute of Technology Ravi Mahajan, Toni Mattila, David McCann, Kitty Pearsall, Eric and Mikel Miller - EMD Performance Materials Perfecto, Jeff Suhling, Andrew Tay, and Pat Thompson Novel materials, processes, and packaging This event is designed just for you – young technologies are being developed to realize a professionals (including current graduate new class of sensors and electronics that can students). In this active event, we will pair you degrade or vanish on command (either through with senior EPS members and professionals externally triggered wireless signals or by “natural” through a series of active and engaging degradation informed by the material properties activities. You will have opportunities to learn and component designs). These innovations more about packaging-related topics, ask are paving the way for new applications such as career questions, and meet some professional in-situ monitoring of acute medical events (e.g., colleagues. bone regeneration) or stealth sensors that can be physically eliminated after use. These smart materials and design approaches can also be used to tackle the exponentially increasing issue of electronic waste. In this session, a panel of global 2019 ECTC Panel Session experts will describe the innovative materials, system integration, and packaging technologies Future (Visions) of Electronics Packaging developed to fabricate these sensors and control Tuesday, May 28, 2019, 7:45 p.m. – 9:15 p.m. their degradation properties. They will also Chairs: Avi Bar-Cohen, EPS President - Raytheon present their views on impacted applications. and Karlheinz Bock - TU Dresden 1. John Rogers – Northwestern University The EPS President’s Panel at this year’s ECTC 2. Matthew MacEwan – Washington explores the future path of packaging science and University technology and proposes possible scenarios for 3. Paul Kohl – Georgia Institute of Technology 2025. Visions of future packaging technologies 4. Mihai Irimia-Vladu – Joanneum Research will be presented and discussed with invited Forschungsgesellschaft, mbH experts in the field of electronics packaging. The authors of the best selected submissions of the EPS packaging technology vision conquest will also join the discussion panel The involvement of our young professionals will bring fresh perspectives and new ways of thinking. The intention of this panel is to identify significant future packaging technologies in order to best serve IEEE and the electronics community 2019 Photonics Special Session Photonics on the Cutting-Edge of Technology Evolution Tuesday, May 28, 2019, 2:00 p.m. – 4:30 p.m. Chairs: Rena Huang - Rensselaer Polytechnic Institute and Soon Jang - ficonTEC (USA) Corporation The special session aims to capture the latest technology advancements in the fast evolving photonics areas that have wide interest to industry, academia and government laboratories worldwide. Invited speakers will discuss topics of 2019 ECTC Plenary Session optical neuromorphic computing, Si photonics Sensors and Packaging for Autonomous Driving for optical quantum computing, heterogeneous Wednesday, May 29, 2019, 7:30 p.m. – 9:00 p.m. integration, advanced LiDARs for autonomous Chair: Tanja Braun, Fraunhofer Institute for Reliability and vehicles, and optical time domain reflectometer (OTDR) integration into fiber optic transceivers. Microintegration (IZM) The invited technical leaders will share their The future of individual, safe, and flexible visions on the technology advancement and transportation is widely seen as driverless. Already future trends. todays’ sensor systems in combination with intelligent algorithms are providing essential support 1. Bert Offrein – IBM Research GmbH-Zurich for human drivers. The rise of AI and a growth 2. Mark Thompson – PsiQuantum of a surrounding infrastructure enhancing car to x 3. Roy Meade, VP Manufacturing – Ayar Labs communication will enable various scenarios for 4. Charles Kuznia – Ultra Communications, Inc. autonomous driving. During the plenary session key 5. Jason Eichenholz – LuminarTechnologies, Inc. experts from industry will discuss the challenges and demands for sensors and packages for autonomous driving along the value chain. 1. Scott Chen – Advanced Semiconductor Engineerng, Inc. 2. Przemyslaw Jakub Gromala – Robert Bosch GmbH 3. Dr. Veer Dhandapani – NXP 4. Dragos Maciuca - Ford These sessions are open to all conference attendees. 5 2019 ECTC/ITherm Women’s Panel 2019 IEEE EPS Seminar and Reception Roadmap of IC Packaging Materials to Meet Next-Generation Smartphone Performance Unleashing the Power of Diversity in our Workforce Requirements Wednesday, May 29, 2019, 6:30 p.m. – 7:30 p.m. Thursday, May 30, 2019, 8:00 p.m. – 9:30 p.m. Chairs: Kristina Young-Fisher - GLOBALFOUNDRIES Chairs: Yasumitsu Orii - Nagase, and Cristina Amon – University of Toronto and Sheigenori Aoki - Fujitsu IEEE EPS Society President Avi Bar-Cohen and 69th This panel will outline the product requirements ECTC Junior Past General Chair Sam Karikalan for the smartphone for 2025-2030 in the cordially invite all ECTC attendees to attend our fifth Women’s Panel and Reception. The panelists will speak era of 5G and 6G. Subsequently, these on Unleashing the Power of Diversity in the Workforce. product requirements will be translated into Discussion will include the power of diversity in a high- packaging material challenges and approaches. performing workplace, strategies to build a diverse Representatives of materials companies will workforce, and tools for inclusion and engagement. share their approaches to meet the projected Panelists will discuss the creation of policies and smartphone system requirements including programs to increase representation along with metrics materials for fan-out wafer-level and panel- to assess progress throughout career progression. The level packaging, molding materials, high-speed panelists will share both successes and challenges to substrates, and low-loss substrates. achieving these goals. To show the product requirements: 1. Monica Jackson – GE Aviation 1. Toshihiko Nishio – SBR Technology Company 2. Rolf Aschenbrenner – Fraunhofer IZM Representatives from materials companies: 3. Dereje Agaonafer- University of Texas at Arlington 2. Eiichi Nomura – Nagase ChemteX 4. Jean Trewhella- GLOBALFOUNDRIES 3. Koichi Hasegawa – JSR 4. Kenji Nishiguchi – Risho Kogyo 5. Mike Sakaguchi – Tatsuta Electric Wire & Cable 6. Yoshio Nishimura – Ajinomoto Fine Technology Co.

6 ECTC Luncheon Keynote Luncheons Soft Electronic and Microfluidic Systems for the Skin Wednesday, May 29, 2019 Tuesday PDC Luncheon John A. Rogers All individuals attending a PDC are invited to join us for Director of Center for Bio-Integrated Electronics, lunch. Proctors and instructors are welcome, too! Northwestern University Wednesday Conference Luncheon Recent advances in materials, mechanics, Please be sure not to miss our Wednesday luncheon with and manufacturing establish the foundations guest speaker Dr. John Rogers, Northwestern University. All conference attendees are welcome! for high-performance classes of electronics and other microsystems technologies that Thursday EPS Luncheon have physical properties precisely matched Our sponsor, the IEEE Electronics Packaging Society, will be sponsoring lunch on Thursday for all conference those of the human epidermis. The attendees! resulting devices can integrate with the Friday Program Chair Luncheon skin in a physically imperceptible fashion Please attend Friday’s lunch hosted by the 69th ECTC to provide continuous, clinical-quality Program Chair. We will honor conference paper award information on physiological status. This talk will summarize the recipients and raffle off a variety of prizes including a key ideas and presents specific examples in wireless monitoring hotel stay, free conference registrations, and many other for neonatal intensive care, and in capture, storage, and biomarker attractive items! analysis of sweat. General Chair’s Speakers Reception Tuesday, May 28, 2019 • 6:00 p.m. – 7:00 p.m. (by invitation only)

ECTC Student Reception Tuesday, May 28, 2019 • 5:00 p.m. – 6:00 p.m. Hosted by Texas Instruments, Inc.

Students, have you ever wondered what career opportunities exist at Texas Instruments and in the industry, and how you could use your technical skills and innovative talent? If so, you are invited to attend the ECTC Student Reception, where you will have the opportunity to talk to industry professionals about what helped them succeed in their first job search and reach their current positions. During this reception, you can enjoy good food while networking with industry leaders and achievers. Don’t miss your opportunity to interact with people who you might not have the chance to meet otherwise! You will also be able to submit your resumes to our sponsoring partners.

Exhibitor Reception Wednesday, May 29, 2019 • 5:30 p.m. – 6:30 p.m. All badged attendees are invited to attend a reception in the exhibition hall.

69th ECTC Gala Reception Thursday, May 30, 2019 • 6:30 p.m. – 8:00 p.m. All badged attendees and their guests are invited to attend a reception hosted by the Gala Reception sponsors.

7 Executive Committee Packaging Technologies Sandy Klengel Shaw Fong Wong General Chair Chair Fraunhofer Institute Intel Corporation Mark Poliks Dean Malta Pilin Liu Wei Xu Binghamton University Micross Advanced Interconnect Technology Intel Corporation Huawei [email protected] [email protected] +1-607-727-7104 +1-919-248-8405 Varughese Mathew Tonglong Zhang NXP Semiconductors Nantong Fujitsu Microelectronics, Ltd. Vice General Chair Assistant Chair Christopher Bower Luke England Toni Mattila High-Speed, Wireless & X-Celeprint, Inc. Components GLOBALFOUNDRIES Aalto University [email protected] Chair [email protected] Keith Newman +1-919-522-3230 Wendem Beyene +1-518-222-1860 AMD Program Chair Intel Corporation Daniel Baldwin Nancy Stoffel Donna M. Noctor [email protected] GE Research H.B. Fuller Company Nokia +1-408-544-6683 [email protected] Bora Baloglu S. B. Park Assistant Chair +1-518-387-4529 Amkor Technology, Inc. Binghamton University Lianjun Liu Assistant Program Chair Jie Fu Lakshmi N. Ramanathan NXP Semiconductor, Inc. Rozalia Beica Apple, Inc. Microsoft Corporation [email protected] The Dow Chemical Company +1-480-413-4022 Mike Gallagher [email protected] René Rongen Dow Electronic Materials NXP Semiconductors Amit P. Agrawal +1-508-787-4691 Microsemi Corporation Ning Ge Jr. Past General Chair Scott Savage Consultant Medtronic Microelectronics Center Kemal Aygun Sam Karikalan Intel Corporation Broadcom Limited Allyson Hartzell Jeffrey Suhling [email protected] Veryst Engineering Auburn University Eric Beyne +1-949-926-7296 IMEC Kuldip Johal Pei-Haw Tsao Prem Chahal Sr. Past General Chair Atotech Taiwan Semiconductor Manufacturing Henning Braunisch Michigan State University Beth Keser Company, Ltd. Intel Corporation Zhaoqing Chen Intel Corporation Dongji Xie [email protected] IBM Corporation +1-480-552-0844 Young-Gon Kim NVIDIA Corporation Charles Nan-Cheng Chen Integrated Device Technology, Inc. Assembly & Manufacturing Sponsorship Chair MediaTek Inc. Wolfgang Sauter Andrew Kim Technology GLOBALFOUNDRIES Intel Corporation Chair Craig Gaw [email protected] Mark Gerber NXP Semiconductor John Knickerbocker +1-802-922-3083 Advanced Semiconductor Engineering, Inc. Abhilash Goyal IBM Corporation Finance Chair [email protected] Velodyne LIDAR, Inc. Albert Lan Patrick Thompson +1-214-305-2154 Xiaoxiong (Kevin) Gu Applied Materials Texas Instruments, Inc. Assistant Chair IBM Corporation [email protected] John H. Lau Jin Yang Rockwell Hsu +1-214-567-0660 ASM Pacific Technology Intel Corporation Cisco Systems, Inc. Publications Chair Jaesik Lee [email protected] Lih-Tyng Hwang Steve Bezuk Nvidia +1-971-214-9041 [email protected] National Sun Yat-Sen University Markus Leitgeb Sai Ankireddi +1-858-218-5143 Bruce Kim AT&S Soraa, Inc. City University of New York Publicity Chair Luu Nguyen Christo Bojkov Eric Perfecto Timothy G. Lenihan Texas Instruments Inc. Qorvo [email protected] TechSearch International +1-845-475-1290 Deborah S. Patterson Garry Cunningham Rajen M Murugan Harbor Electronics, Inc. NGC Treasurer Texas Instruments, Inc. Habib Hichri Tom Reynolds Raj Pendse Nanju Na T3 Group LLC Suss Microtech Photonic Systems, Inc. Facebook FRL Xilinx [email protected] Subhash L. Shinde Paul Houston +1-850-897-7323 Dan Oh Engent Notre Dame University Samsung Exhibits Management Joseph W. Soucy Li Jiang Joe Gisler P. Markondeya Raj Draper Laboratory Texas Instruments Vector Associates Georgia Institute of Technology Chunho Kim [email protected] Peng Su Hideki Sasaki +1-480-288-6660 Juniper Networks Medtronic Corporation Renesas Electronics Corporation Exhibits Co-Management Kuo-Chung Yee Wei Koh Li-Cheng Shen Alan Huffman Taiwan Semiconductor Manufacturing Pacrim Technology Wistron NeWeb Corporation Micross Advanced Interconnect Technology Company, Ltd. Ming Li [email protected] Jaemin Shin ASM Pacific Technology +1-919-248-9216 Christophe Zincke Qualcomm Corporation Advanced Semiconductor Engineering, Inc. Debendra Mallik Web Administrator Manos M. Tentzeris Applied Reliability Intel Corporation Ibrahim Guven Georgia Institute of Technology Chair Virginia Commonwealth University Jae-Woong Nah Maciej Wojnowski Deepak Goyal [email protected] IBM Corporation Infineon Technologies AG +1-804-827-3652 Intel Corporation [email protected] Valerie Oberson Yong-Kyu Yoon Professional Development Course Chair +1-480-554-5203 IBM Canada, Ltd. University of Florida Kitty Pearsall Chandradip Patel Boss Precision, Inc. Emerging Technologies Assistant Chair Schlumberger Technology Corporation [email protected] Chair +1-512-845-3287 Darvin R. Edwards Shichun Qu Florian Herrault Edwards Enterprise Consulting, LLC Intersil, a Renesas Company HRL Laboratories, LLC Conference Management [email protected] [email protected] Paul Tiner Lisa Renzi Ragar +1-972-571-7638 +1-310-317-5269 Renzi & Company, Inc. Texas Instruments, Inc. Assistant Chair [email protected] Tim Chaudhry Andy Tseng +1-703-863-2223 Benson Chan Amkor Technology, Inc. JSR Micro Binghamton University EPS Representative Tz-Cheng Chiu Jan Vardaman [email protected] C. P. Wong National Cheng Kung University Techsearch International +1-607-777-4349 Georgia Institute of Technology [email protected] Vikas Gupta Yu Wang Isaac Robin Abothu 8 +1-404-894-8391 Texas Instruments, Inc. Sensata Technologies Siemens Healthineers Meriem Akin Changqing Liu Kimberly Yess Ajey Jacob Leibniz Universitaet Hannover Loughborough University Brewer Science GLOBALFOUNDRIES Vasudeva P. Atluri Nathan Lower Myung Jin Yim Soon Jang Renavitas Technologies Rockwell Collins, Inc. Apple, Inc. ficonTEC, USA Karlheinz Bock James Lu Hongbin Yu Harry G. Kellzi Technische Universitat Dresden Rensselaer Polytechnic Institute Arizona State University Teledyne Microelectronic Technologies Vaidyanathan Chelakara Voya Markovich Thermal/Mechanical Simulation & Richard Pitwon Acacia Communications Microelectronic Advanced Hardware Characterization Resolute Photonics Ltd Rabindra N. Das Consulting, LLC Chair MIT Lincoln Labs Lou Nicholls Przemyslaw Gromala Alex Rosiewicz Dongming He Amkor Technology, Inc. Robert Bosch GmbH A2E Partners [email protected] Qualcomm Technologies, Inc. Henning Schroeder Peter Ramm +49-162-8514983 TengFei Jiang Fraunhofer EMFT Fraunhofer IZM University of Central Florida Assistant Chair Katsuyuki Sakuma Ning Ye Andrew Shapiro Jong-Hoon Kim IBM Corporation Western Digital JPL Washington State University Vancouver Lei Shan [email protected] Masato Shishikura Ahyeon Koh IBM Corporation +1-408-801-1278 Oclaro Japan Binghamton University Ho-Young Son Christopher J. Bailey Masao Tokunari Ramakrishna Kotlanka SK Hynix University of Greenwich Analog Devices IBM Corporation Jean-Charles Souriau Kuo-Ning Chiang Shogo Ura Santosh Kudtarkar CEA Leti National Tsinghua University Analog Devices Kyoto Institute of Technology Chuan Seng Tan Xuejun Fan Kevin J. Lee Nanyang Technological University Lamar University Stefan Weiss Qorvo Corporation II-VI Laser Enterprise GmbH Matthew Yao Nancy Iwamoto Zhuo Li GE Aviation Honeywell Performance Materials and Feng Yu Fudan University Materials & Processing Technologies Huawei Technologies Japan Chukwudi Okoro Chair Thomas Zahner Corning Pradeep Lall Mikel Miller Auburn University OSRAM Opto Semiconductors GmbH Bharat Penmecha EMD Performance Materials Chang-Chun Lee Interactive Presentations Intel Corporation [email protected] National Tsing hua University (NTHU) Chair C. S. Premachandran +1-951-514-4574 Yong Liu Michael Mayer GLOBALFOUNDRIES Assistant Chair ON Semiconductor University of Waterloo Jintang Shang Tanja Braun [email protected] Southeast University Fraunhofer IZM Sheng Liu Wuhan University +1-519-888-4024 Rohit Sharma Yu-Hua Chen IIT Ropar Unimicron Erdogan Madenci Assistant Chair University of Arizona Pavel Roy Paladhi Nancy Stoffel Qianwen Chen IBM Corporation GE Research IBM Research Tony Mak [email protected] Liu Yang Wentworth Institute of Technology Bing Dang +1-512-286-9677 IBM Corporation IBM Research Karsten Meier Technische Universität Dresden Swapan Bhattacharya Jimin Yao Yung-Yu Hsu Engent, Inc. Intel Corporation Apple, Inc. Erkan Oterkus University of Strathclyde W. Hong Yeo Lewis Huang Rao Bonda Georgia Institute of Technology Senju Electronic Sandeep Sane Amkor Technology, Inc. Intel Corporation Hongqing Zhang C. Robert Kao Mark Eblen IBM Corporation National Taiwan University Suresh K. Sitaraman Kyocera International SC Georgia Institute of Technology Interconnections Chin C. Lee Ibrahim Guven Chair University of California, Irvine Wei Wang Virginia Commonwealth University Wei-Chung Lo Qualcomm Technologies, Inc. ITRI Alvin Lee Alan Huffman [email protected] Brewer Science G. Q. (Kouchi) Zhang Micross Advanced Interconnect Technology +886-3-591-7024 Delft University of Technology (TUD) Yi (Grace) Li Jeffrey Lee Tieyu Zheng Assistant Chair Intel Corporation iST-Integrated Service Technology Inc. Microsoft Corporation Dingyou Zhang Ziyin Lin Nam Pham Broadcom Inc. Intel Corporation Jiantao Zheng [email protected] Hisilicon IBM Corporation Yan Liu Thibault Buisson Medtronic Inc. USA Photonics Mark Poliks Yole Développement Chair Binghamton University Daniel D. Lu Jian Cai Henkel Corporation Ping Zhou Patrick Thompson Tsinghua University LDX Optronics, Inc. Texas Instruments, Inc. Joon-Seok Oh William Chen [email protected] Samsung Electro-Mechanics Kristina Young-Fisher Advanced Semiconductor Engineering, Inc. +1-865-981-8822 Praveen Pandojirao GLOBALFOUNDRIES David Danovitch Assistant Chair Johnson & Johnson University of Sherbrooke Z. Rena Huang Professional Development Courses Rensselaer Polytechnic Institute Chair Rajen Dias Mark Poliks [email protected] Amkor Technology, Inc. Binghamton University Kitty Pearsall +1-518-276-6086 Boss Precision, Inc. Bernd Ebersberger Dwayne Shirley [email protected] Intel Corporation Inphi Mark Beranek Naval Air Systems Command +1-512-845-3287 Takafumi Fukushima Ivan Shubin Tohoku University Oracle Stephane Bernabe Co-Chair CEA Leti Jeffrey Suhling Tom Gregorich Bo Song Zeiss Semiconductor Manufacturing HP Inc. Fuad Doany Auburn University [email protected] Technology Yoichi Taira IBM Research +1-334-844-3332 Kangwook Lee Keio University Gordon Elger Amkor Technology Korea Lejun Wang Technische Hochschule Ingolstadt Deepak Goyal Steward Lee Qualcomm Technologies, Inc. Takaaki Ishigure Intel Corporation Li Li Frank Wei Keio University Lakshmi N. Ramanathan Cisco Systems, Inc. Disco Japan Microsoft Corporation 9 2. INTRODUCTION TO FAN-OUT temporary bonding, integrated glass wafers for optical PROFESSIONAL WAFER LEVEL PACKAGING sensors and augmented reality, key components in DEVELOPMENT Course Leader: Beth Keser – Intel RF communications, as well as glass interposers for Corporation 2.5D and 3D packaging. COURSES Course Objective: Course Outline: Tuesday, May 28, 2019 Fan-out wafer level packaging (FO-WLP) 1. Fundamentals of Glass technologies have been developed across the What is Glass? Kitty Pearsall, Chair - industry over the past 15 years and have been Overview of Glass Attributes Boss Precision, Inc. - in high-volume manufacturing for over 10 years. 2. Versatility of Glass [email protected] FO-WLP has matured enough that it has come to Glass Composition Review +1-512-845-3287 - a crossroads where it has the potential to change - Melting and Forming Process Jeff Suhling, Assistant Chair the industry by eliminating wire - Overview of Major Forming Processes Auburn University bond and bump interconnections, substrates, lead - Secondary Processes [email protected] frames, and the traditional flip chip or wire bond chip - Options for Enhanced Properties +1-334-844-3332 attach and underfill assembly technologies across 3. Major Applications and Markets multiple applications. This course will cover the - Wafer-Level Optics MORNING COURSES advantages of FO-WLP, potential application spaces, - structures available in the industry, process - Case Studies 8:00 a.m. – 12:00 Noon flows, material challenges, design rule roadmap, Who Should Attend: reliability, and benchmarking. Engineers, technical managers, scientists, buyers, 1. ACHIEVING HIGH RELIABILITY Course Outline: and managers involved in materials, research and OF LEAD-FREE SOLDER JOINTS – 1. Current Challenges in Packaging development, as well as advanced semiconductor MATERIALS CONSIDERATIONS 2. Definition and Advantages packaging. We welcome individuals or companies Course Leader: Ning-Cheng Lee – Indium with little or no experience in using glass. Corporation 3. Applications 4. Package Structures 4. MOORE’S LAW FOR PACKAGING Course Objective: 5. Process TO REPLACE MOORE’S LAW FOR ICS This course covers the detailed material 6. Material Challenges Course Leader: Rao Tummala – Georgia considerations required for achieving high reliability 7. Design Rule Roadmap Institute of Technology for lead-free solder joints. The reliability discussed 8. Reliability includes joint mechanical properties, development of 9. Benchmarking Course Objective: type and extent of intermetallic compounds (IMC) This course proposes that Moore’s Law for under a variety of material combinations and aging Who Should Attend: Packaging replaces Moore’s Law for ICs, as the conditions and how those IMCs affect the reliability. Engineers and managers responsible for advanced latter is seen as coming to an end. Moore’s Law The failure modes, thermal cycling reliability, and packaging development, package characterization, for ICs is about scaling to ever smaller fragility of solder joints as a function of material package quality, package reliability and package sizes, from node-to-node and interconnecting and combination, thermal history, and stress history will design should attend this course. Suppliers who are integrating these to result in more transistors in be addressed in details, and novel alloys with reduced interested in supporting the materials and equipment smaller chips at lower cost from 300 mm wafers. As fragility will be presented. Also presented are crucial supply chain should also attend. Both newcomers scaling and integration comes to an end parameters for high reliability solder alloys for and experienced practitioners are welcome. due to physical, material, and electrical limitations, automotive industry. Electromigration and tin whisker 3. FUNDAMENTALS OF GLASS Moore’s Law for Packaging (MLP) can be viewed will also be discussed. The emphasis of this course TECHNOLOGY AND APPLICATIONS as interconnecting and integrating smaller chips with is placed on the understanding of how the various FOR ADVANCED SEMICONDUCTOR the highest transistor density and with the highest factors contribute to the failure modes, and how to PACKAGING performance at the lowest cost. Package or system select proper solder alloys and surface finishes for Course Leaders: Dr. Indrajit Dutta – scaling is proposed to be one and the same, as the achieving high reliability. Corning, Inc. and Dr. Jay Zhang – Corning, end goal of packaging is a system. Just as Moore’s Law has two components – number of transistors Course Outline: Inc. and cost of each transistor, MLP is proposed to 1. Main Stream Lead-free Soldering Practice Course Objective: have two components as well – the number of 2. Surface Finishes Issues This course is intended to guide technologists interconnections or I/Os and the cost of each I/O. 3. Mechanical Properties toward a deeper understanding of how to leverage 4. Intermetallic Compounds engineered glass as a material for advanced IC This course lays the ground work for Moore’s Law 5. Failure Modes packaging applications. Following a review of for Packaging by showing how I/Os have evolved 6. Reliability - Thermal Cycle the fundamental principles of glass structure, from one package family node to the next, starting 7. Reliability - Fragility composition, and properties, we will discuss the with <16 I/Os in the 1960s to the current silicon 8. Reliability - Rigidity & Ductility unique attributes that make glass an enabling material, interposers with about 200,000 I/Os. It proposes 9. Reliability - Electromigration including strength and reliability, chemical durability, a variety of ways to extend Moore’s Law, such as 10. Reliability - Tin Whisker thermal behavior, associated thermal relaxation extending Si interposers and beyond using glass in panel embedding. Who Should Attend: behavior, and electrical properties. In addition, we Directors, managers, design engineers, process will review the “glass toolkit” as a platform alternative Just as Moore’s Law has both a doubling of engineers, and reliability engineers who for semiconductor packaging development, including transistors and a simultaneous cost reduction from care about achieving high reliability lead-free solder various manufacturing (glass melting and forming) node to node every 18-24 months, MLP must do joints and would like to know how to achieve it approaches, the diversity of compositional options, the same. Interconnections have been driven by should take this course. and a survey of glass processing approaches that can computing systems and within computing systems, be adapted from adjacent glass technology spaces to between logic and memory. The new era of artificial advanced semiconductor packaging. Finally, a series intelligence, mimicking human brains, is yet another IMPORTANT NOTICE of case studies will illustrate how glass is contributing reason for Moore’s Law for System Interconnections. It is extremely important to to emerging technologies in the microelectronics Currently, the most advanced MLP is with wafer- space and explore current and potential applications based packaging. But silicon-based packaging register in advance to prevent in advanced semiconductor packaging, consumer has many limitations at material, substrate or delays at door registration. electronics, and internet of things (IoT) applications. interconnect and system levels. At material level, its Course sizes are limited. Examples include the role of glass as a carrier for electrical loss and its dielectric constant are very high.

10 At interconnect level, its capacitance and resistance Applications Who Should Attend: are very high, leading to so-called RC delays. In 8. Fundamentals of Electrically Conductive Engineers, scientists, researchers, designers, addition, Si-based packaging doesn’t conform to Adhesives (ECAs) managers, and graduate students interested in the Moore’s Law for cost. Cost, of course, is the basis 9. Recent Advances on Conductive Adhesives fundamentals of electronic packaging as well as those for going away from Moore’s Law for ICs. At 10. Recent Advances on Nano Conductive involved in the process of electrical design, layout, system levels, Si interposers, while they are perfectly Adhesives processing, fabrication, and/or system-integration of matched to ICs, they are totally mismatched to electronic packages. boards, requiring additional packaging, thus making Who Should Attend: system level interconnections even longer. So, what Engineers, scientists and managers involved 7. SOLVING PACKAGE FAILURE are future technologies beyond Si interposers to in designing, processing, and manufacturing of MECHANISMS FOR IMPROVED RELIABILITY drive Moore’s Law for packaging. This course will microelectronic and optoelectronic components present and discuss a variety of options. Course Leader: Darvin Edwards – Edwards and packages, material suppliers, and students and Enterprises Course Outline: researchers on electronic packaging should attend. 1. Current Approach to Devices and Systems Course Objective: 2. Moore’s Law for ICs, Its Evolution and Its Future 6. FUNDAMENTALS OF RF DESIGN This course explores past and present reliability 3. Three Eras of Moore’s Law: For ICs, Packaging AND FABRICATION PROCESSES OF failure mechanisms that plague semiconductor or Interconnections and for Systems FAN-OUT WAFER/PANEL LEVEL packages. Primary reliability challenges and major 4. Moore’s Law for Packaging: Observation and PACKAGES AND INTERPOSERS failure mechanisms will be investigated in emerging Proposal Course Leaders: Ivan Ndip and Markus and high-volume package types such as TSVs, 5. Evolution of Package Interconnections (I/Os) Wöhrmann – Fraunhofer IZM FOWLPs, WLCSPs, FC-BGAs plastic leaded, and from the 1960s Consistent with Moore’s Law no lead packages. The class will focus on reliability Course Objective: 6. Future of Moore’s for Packaging topics including TSV-chip interactions, micro bump Due to their myriad advantages in system- Who Should Attend: mechanical reliability, electromigration performance, R&D executives as well as senior technical and integration, fan-out wafer/panel-level packages stress induced ILD damage under bumps and wire marketing managers involved in all aspects of (FO WLPs/PLPs) and interposers will play a key bonds, Cu vs. Au wire bond reliability challenges, electronics from academic and industry R&D, role in the development of emerging miniaturized complications associated with package delamination, supply-chain IC, package and systems manufacturing, electronic systems. The fabrication processes and solder joint reliability, system level issues such as marketing, investments, and users who deal with RF performance of these advanced packages, drop and bend reliability, and the impact of aging on strategic directions for their company. especially their multi-layered redistribution layers reliability performance. For each failure mechanism, 5. POLYMERS AND (RDLs), required for the interconnection of the the resultant failure modes and failure analysis NANOCOMPOSITES FOR chips and other system components, will contribute techniques needed to verify the mechanisms will be ELECTRONIC AND PHOTONIC significantly to the cost and performance of the entire summarized. Recommended failure analysis fault PACKAGING system. The objective of this course is to provide isolation techniques will be described. Course Leaders: C. P. Wong – Georgia and illustrate the fundamentals of the fabrication This solutions-focused course concentrates on Institute of Technology; Daniel Lu – processes and RF design of FO WLPs/PLPs and process parameters, design techniques and material Henkel Corporation interposers, including their multi-layered RDLs. selections that eliminate failures and improve Course Objective: reliability to ensure participants can design-in An overview of different types of wafer-level Polymers and nanocomposites are widely used in reliability and design-out failures. Characterization packages, fan-out technologies and interposers, as electronic and photonic packaging as adhesives, and implementation of design guidelines that enable encapsulants, insulators, dielectrics, molding well as the advantages of FO WLPs/PLPs and glass/ reliable products will be described and encouraged. compounds, and conducting elements for silicon interposers will first be given. This will be A test structure methodology combined with interconnects. These materials also play a critical role followed by a thorough discussion of the materials qualification by similarity will be highlighted as a in the recent advances of low-cost, high-performance and fundamentals of the fabrication processes of FO technique for early detection of chip/package novel no-flow underfills, reworkable underfills for ball WLPs/PLPs, multilayered RDLs, and glass/silicon reliability risks. grid array (BGA), chip scale packaging (CSP), system interposers. The basics of efficient RF design and in a package (SIP), direct chip attach (DCA), flip-chip Course Outline: measurement of the fundamental building blocks (FC), paper-thin IC and 3D packaging, conductive 1. Introduction to Package Reliability adhesives (both ICA and ACA), embedded passives of FO WLPs/PLPs and glass/silicon interposers, 2. Failure Modes vs. Failure Mechanisms (high K polymer composites), nano particles and considering their multi-layered RDLs, will be given 3. Failure Analysis Techniques and Fault Isolation nano functional materials such as CNTs (some for frequencies right up in the millimeter-wave Package Failure Mechanisms: WLCSPs with graphenes). It is imperative that both material range. Finally, examples of these advanced packages 4. FC-BGA Package Failure Mechanisms suppliers, formulators, and their users have a designed and fabricated at Fraunhofer IZM will be 5. Molded and Leaded Package Failure Mechanisms thorough understanding of polymeric materials discussed. 6. WLCSPs Package Failure Mechanisms and the recent advances on nano materials and 7. Embedded Die & Fan-Out WLP Failure Course Outline: their importance in the advances of the electronic Mechanisms 1. Overview of Different Types of Wafer-Level packaging and interconnect technologies. 8. TSV Failure Mechanisms Packages, Fan-Out Technologies and Interposers Course Outline: 9. Materials, Modeling, Design Rules and Reliability 1. Fundamental of Polymers and Materials Science 2. Advantages: FO WLPs/PLPs and Silicon/Glass 10. Common Test Structures for Failure Mechanism and Engineering Interposers Identification 2. Material Needs for Next-Generation Electronic 3. Materials and Fabrication Processes: FO WLPs/ 11. Qualification by Similarity (QBS) Packaging PLPs, Multi-layered RDLs, and Silicon/Glass 12. Summary 3. Novel Nanocomposites for Flip-Chip Underfill Interposers Who Should Attend: Applications 4. Fundamentals of RF Design and Measurement: 4. Recent Advances on Nano Lead-Free Alloys for This class is for all who work with IC packaging, FO WLPs/PLPs, RDLs, and Silicon/Glass package reliability, package development, package High-Performance Components Interconnects Interposers 5. Low-Cost High-Performance Lead-Free design, and package processing where a working Interconnect Materials and Processes 5. Comparison of RF Performance of Interconnects knowledge of package failure mechanisms is needed. 6. Recent Advances on CNTs as Thermal Interface in FO WLPs/PLPs and Silicon/Glass Interposers Beginning engineers and those skilled in the art Materials (TIMs) 6. Examples of Advanced Packages Designed and will benefit from the holistic failure mechanism 7. Lotus Effect Coating for Self-Cleaning Fabricated at Fraunhofer IZM descriptions and the provided proven solutions.

11 8. CHARACTERIZATION OF Who Should Attend: ADVANCED EMCS FOR FO-WLP, Engineers and technical managers who are already AFTERNOON COURSES HETEROGENEOUS INTEGRATION, involved in the material characterization and 1:15 p.m. – 5:15 p.m. AND AUTOMOTIVE ELECTRONICS modeling, numerical modelling, process engineers Course Leaders: Przemyk Gromala – and PhD students who need fundamental 10. FLIP CHIP TECHNOLOGIES Robert Bosch GmbH; Bongtan Han – understanding or broad overview. Course Leaders: Eric Perfecto – Independent Consultant; Shengmin Wen University of Maryland 9. INTEGRATED THERMAL – Synaptics Inc. Course Objective: PACKAGING AND RELIABILITY OF Epoxy-based molding compounds (EMCs) are POWER ELECTRONICS Course Objective: widely used in the semiconductor industry as one Course Leader: Patrick McCuskey – This course will cover the fundamentals of all steps of the most important encapsulating materials. For University of Maryland and aspects of flip chip assembly process including the advanced packaging technologies, in particular, wafer bumping, solder joint formation, underfill Course Objective: types, substrate selection, and reliability evaluation. FO-WLP technologies and heterogeneous Power electronics are becoming ubiquitous in integrations, EMCs play a more significant role than The course is divided into two major sections. The engineered systems as they replace traditional ways first section is devoted to bumping technology. Two the conventional plastically-encapsulated packages to control the generation, distribution, and use of major bumping technologies that are used in today’s because of thin profiles and complex process energy. They are used in products as diverse as flip chip assembly, i.e., lead-free solder bumping and conditions required for the advanced packaging home appliances, cell phone towers, aircraft, wind highly customized Cu Pillar bumping, will be discussed technologies. In the automotive industry where turbines, radar systems, smart grids, and data centers. in depth, including the details and comparison of demand for more advanced packaging technologies This widespread incorporation has resulted in various UBM (electroplating, electroless plating increases rapidly for autonomous and connected significant improvements in efficiency over previous and sputtering) and solder depositions methods cars, EMCs are often used to protect, not only technologies, but it also has made it essential that (electroplating, ball drop, IMS, and solder screening). individual IC components, but also entire electronic the reliability of power electronics be characterized The course will cover the various failure modes control units (ECUs), or power modules. and enhanced. Recently, increased power levels, related to bumping, such as barrier consumption, The stress caused by the mismatch of the made possible by new compound semiconductor Kirkendall void formation, non-wets, BEOL dielectric coefficient of thermal expansion (CTE) between materials, combined with increased packaging cracking, electromigration, etc. The second section EMCs and adjacent materials is one of the major density have led to higher heat densities in power focuses on the details of assembly processes and causes of reliability problems (e.g., excessive electronic systems, especially inside the switching their applications to single, multi-die, and multi-level warpage, delamination, BRL, etc.). During module, making thermal management more critical flip chip integration, as well as wire bond / flip chip mixed integration. For example, the chip scale assembly or even operating conditions, EMCs to performance and reliability of power electronics. This course will emphasize approaches to integrated packages, wafer-level fan-in and fan-out packages, are subjected to temperatures beyond the thermal packaging that address performance limits chip-on-chip packages, chip-on-wafer packages, and glass transition temperature. Around the glass and reliability concerns associated with increased 2.5D/3D flip chip packages are all discussed with transition temperature, EMCs exhibit significant power levels and power density. Following a quick actual industrial leading application cases. In-depth volumetric and isochoric viscosity, which leads review of active heat transfer techniques, along with discussions include chip package interaction (CPI), to nonlinear viscoelastic behavior. In contrast, at prognostic health management, this short course will package warpage control, yield detractors for flip chip low temperatures, EMCs show linear viscoelastic present the latest developments in the materials (e.g. assembly, substrate technologies, failure modes and behavior. This complex material characteristic in the organic, flexible), packaging, assembly, and thermal root cause analysis, reliability tests, and the important full temperature range of interest renders the design management of power electronic modules, MEMS, roles of electrical and mechanical simulation, Si die of electronic devices a nontrivial task. The mechanical and systems and the techniques used for their floor plan optimization and its consequence on behavior of EMCs has to be understood clearly reliability assessment. packaging, among others. Students will understand to offer predictive simulation strategies, which has the versatility of flip chip technologies and learn a become an integral part of product development Course Outline: range of criteria that they can apply to their daily process. 1. Motivation for Integrated Thermal Packaging for work needs. This section also provides the trend in Reliable Power Electronic Systems the flip chip assembly technologies. This training will address details of such strategies, 2. Simulation and Assessment of Active Thermal summarize the required material characterization Management Techniques: Air, Single Phase The goal of this course is to provide the students with a list of options to apply to their particular procedure, and close with some representative Liquid, Two Phase, Heat Pipes, and flip chip assembly applications so that a reliable, examples. Thermoelectric innovative, better time to market, and more cost- 3. Application of Thermal Management Techniques Course Outline: effective solution can be achieved. Students are to Commercial Power Systems 1. Introduction encouraged to bring topics and technical issues from 2. Selection of the Material (Preliminary Qualitative 4. Durability Assessment: Failure Modeling, their past, present and future job function for group Analysis) Simulation, Testing, and Health Monitoring discussions. A 20-minute group exercise at the end 3. Material Characterization 5. Reliability and Thermal Packaging of Active of the class is planned to make sure the students can 4. Cure Kinetics Devices: Si, SiC, GaN, and Interconnects walk away with the course knowledge that applies to 5. Curing Shrinkage 6. Reliability and Thermal Packaging of Switching their daily job functions. 6. Coefficient of Thermal Expansion Modules, including Organic Encapsulates Course Outline 7. Linear Viscoelastic Properties 7. Reliability in Rigid Assembly Packaging: PCB, Solders, and Glass Interposers 1. Introduction to Flip-Chip Technologies - Master Curve and Shift Factor of Young’s 2. Flip Chip Technologies: Mass Reflow Process Modulus 8. Flexible Materials, Packaging, and Thermal Management: Flex Circuit, OLED, Wearables 3. Flip Chip Technologies: Thermal Compression - Master Curve and Shift Factor of Bulk 4. Flip Chip Si Package Co-Design and Chip- Modulus 9. Reliability of Additively Manufactured and Embedded Power Electronics Package Interaction 8. Viscoelastic Behavior in the Non-linear Domain 5. Flip Chip New Trends: Wafer Level, Panel Level, - Moisture Diffusivity and Solubility Who Should Attend: and u-BGA - Coefficient of Hygroscopic Swelling This course is intended for practicing engineers, 6. Substrate Technologies, Underfill, Package 9. Modeling Strategies designers, and technical managers who work with Warpage Control, and Yield - Linear Viscoelastic Modeling high heat flux electronics or power electronics and 7. Flip Chip Reliability Assessment, Failure Modes, - Nonlinear Viscoelastic Modeling want to learn more about the design, manufacturing, Examples, and Modeling - Verification and Validation thermal management, and reliability of these power 8. Bumping General 10. Summary electronic systems. 9. Flip Chip Under-Bump Metal and Intermetallics

12 10. Flip Chip Solder Deposition Processes WLCSP as a potential alternative for their packaging 10. Additive Technologies in Flexible Electronics 11. Cu Pillar Technology solutions. 11. Reflow and Printing Processes 12. Flip Chip Solder Selection and Characterization 12. FLEXIBLE HYBRID 12. Accelerated Testing Protocols 13. Flip Chip Electromigration TECHNOLOGIES - MANUFACTURING 14. Non-Solder Interconnects Who Should Attend: AND RELIABILITY The targeted audience includes scientists, engineers, Who Should Attend: Course Leader: Pradeep Lall – Auburn and managers currently using flexible electronics The target audience includes scientists, engineers, University or considering moving from rigid electronics to and managers currently using flip-chip (with solder Course Objective: flexible electronics, as well as reliability, product or Cu pillar) or those considering moving from In this course, manufacture, design, assembly, and or applications engineers who need a deeper wire bonding to flip-chip, as well as reliability, accelerated testing of flexible hybrid electronics understanding of flexible electronics: the advantages, product or applications’ engineers who need a for applications in some of the emerging areas will deeper understanding of flip-chip technologies: the limitations, and failure mechanisms. be covered. Flexible hybrid electronics opens the advantages, limitations, and failure mechanisms. possibilities for the development of stretchable, 13. FAN-OUT WAFER/PANEL 11. WAFER-LEVEL CHIP- bendable, foldable form-factors in electronics LEVEL PACKAGING AND 3D IC SCALE PACKAGING (WCSP) applications which have not been possible with HETEROGENEOUS INTEGRATION FUNDAMENTALS the use of rigid electronics technologies. Flexible Course Leader: John Lau – ASM Pacific Course Leader: Patrick Thompson – Texas electronics may be subjected to strain magnitudes Technology Ltd. Instruments, Inc. in the neighborhood of 50-150 percent during Course Objective: Course Objective: normal operation. The integration processes Recent advances in fan-out wafer/panel level This course will provide an overview of Wafer- and semiconductor packaging architectures for packaging (TSMC’s InFO-WLP and Fraunhofer IZM’s flexible hybrid electronics may differ immensely in Level Chip-Scale Packaging (WLCSP) technology. FO-PLP), 3D IC packaging (TSMC’s InFO_PoP comparison with those used for rigid electronics. The The market drivers, end applications, benefits, and vs. Samsung’s ePoP), 3D IC integration (Hynix/ manufacture of thin electronic architectures requires challenges of using WLCSPs in different applications Samsung’s HBM for AMD/NVIDIA’s GPU vs. will be discussed. WLCSP configurations, such as the integration of thin-chips, flexible encapsulation, compliant interconnects, and stretchable inks Micron’s HMC for Intel’s Knights Landing CPU), bump on-pad and bump-on-polymer, as well as 2.5D IC Integration (Xilinx/TSMC’s CoWoS and fan-in, and fan-out formats, will be discussed in terms for metallization traces. A number of additive manufacturing processes for the fabrication and TSV-less interconnects and interposers), embedded of their construction, manufacturing processes, 3D hybrid integration (of VCSEL, driver, serializer, materials and equipment, and electrical and thermal assembly of flexible hybrid electronics have become polymer waveguide, etc.), 3D CIS/IC integration, 3D performance, together with package and board level tractable. Processes for handling, pick-and-place reliability. Extensions to higher pin count packages operations of thin silicon and compliant interposers MEMS/IC integration, and Cu-Cu hybrid bonding and other arenas such as RF sensors and MEMS will through interconnection processes such as reflow will be discussed in this presentation. Emphasis is be reviewed. Future trends will be covered, including requires an understanding of the deformation and placed on various FOWLP assembly methods such alternate alloy solder balls, increasing ball count, warpage processes for development of robust as chip-first with die-up, chip-first with die-down, and decreasing ball pitch, wafer-level underfill, decreasing process parameters which will allow for acceptable chip-last (RDL-first). Because redistribution layers package thickness, stacked WLCSP, fan-out WLCSP levels of yields in high-volume manufacture. Modeling (RDLs) play an integral part of FOWLP, various RDL modules, embedded components, and the advent of of operational stresses in flexible electronics requires fabrication methods such as Cu damascene, polymer, large format (panel) processing. Since the technology the material behavior under loads including constant and PCB/LDI will be discussed. A few notes and marks the convergence of fab, assembly, and test, exposure to human body temperature, saliva, sweat, recommendations on wafer vs. panel, dielectric the course will address questions such as: Does it fit ambient temperature, humidity, dust, wear and materials, and molding materials will be provided. abrasion. The strains imposed on flexible stretchable best with front-end or back-end processing? Are the Also, TSV-less interposers such as those given by electronics may far exceed those experienced in rigid current standards for design rules, package outline, Xilinx/SPIL, Amkor, SPIL/Xilinx, STATSChipPac, reliability, and equipment sufficient? Will WLCSP electronics requiring the consideration of finite-strain formulation in development of predictive models. ASE, MediaTek, Intel, ITRI, Shinko, Cisco/ technology be applicable and cost-effective for eSilicon, Samsung, and Sony will also be discussed. memory and other complex devices such as ASICs The failure mechanisms, failure modes, acceleration factors in flexible electronics under operational Furthermore, new trends in semiconductor and microprocessors? What are the benefits and packaging will be presented. limitations of WLCSP in automotive applications? loads of stretch, bend, fold and loads resulting from human body proximity are significantly different Course Outline: Course Outline: than rigid electronics. The testing, qualification, and 1. Formation of FOWLP: (a) Chip-first (die face- 1. Market Drivers for WLCSPs: Portable quality assurance protocols to meaningfully inform Consumer, Medical, Automotive, Industrial, down); (b) Chip-first (die face-up); (c) Chip-last manufacturing processes and ensure reliability and 2. Fabrication of RDLs: (a) Polymer and ECD Cu + Sensors, MEMS survivability under exposure to sustained harsh Etching; (b) PECVD and Cu Damascene + CMP; 2. Key WLCSP Technologies environmental operating conditions, may differ in (c) Hybrid RDLs 3. Equipment and Materials References flexible electronics as well. A number of product 4. Infrastructure Service Providers areas for the application of flexible electronics are 3. TSMC InFO-WLP, InFO-PoP, InFO_AiP 5. Pitch and Height Trends tractable in the near-term including Internet of 4. Formation of FOPLP: (a) PCB + SAP; (b) PCB 6. Cost, Benefits, and Limits of WLPs Things (IoT), medical wearable electronics, textile + LDI; (c) PCB + TFT-LCD; (d) SEMCO PLP 7. Reliability: Thermal Cycling, Drop, Bend, woven electronics, robotics, communications, asset 5. Wafer vs. Panel: (a) Application Ranges; (b) Temperature/Humidity, Electromigration monitoring, and automotive electronics. Critical Issues of FOPLP 8. Fan-Out WLP 6. Embedded Chips Panel-Level Packaging (ECP): Course Outline: 9. Supply Chain (a) TI/AT&S; (b) TDK; (c) Fujikura; (d) 1. Ultra-Thin Chips 10. Embedded Die Schweizer 11. Single Die Embedding vs. SiP Module 2. Die-Attach Materials for Flexible Semiconductor Packaging 7. Embedded Chips: (a) in Silicon (Maxim); (b) in 12. Challenges in Evolution to Large Format Glass (GIT) Processing 3. Compliant Interconnects 4. Flexible Encapsulation Materials 8. System-on-Chip (SoC): (a) A10; (b) A11; (c) Who Should Attend: 5. Inkjet and Aerosol-Jet Printing Processes A12 The course will be useful to the following groups 6. Dielectric Materials for Large-Area Flexible 9. Heterogeneous Integration vs. SoC of engineers: Newcomers to the field who would Electronics 10. Heterogeneous Integration on Organic like to obtain a general overview of WLCSP; R&D 7. Flexible Substrates Substrates (SiP): (a) Amkor (Automobiles); (b) practitioners who would like to learn new methods 8. Stretchable Inks for Printed Traces ASE (Watches); (c) Intel/AMD’s CPU/GPU/ for solving CSP problems; and those considering 9. Pick-and-Place and Material Handling Processes HBM; (d) Cisco/eSilicon (Organic Interposer)

13 11. Heterogeneous Integration on Silicon Substrates 7. Polymer Challenges in Fan-out Wafer Level 16. ROBUST ELECTRONICS FOR (TSV-Interposers): (a) Leti (SoW); (b) TSMC/ Packaging AUTOMOTIVE APPLICATIONS Xilinx (CoWoS); (c) AMD and NVidia’s Graphic 8. Reliability Testing for Fan-out Wafer Level INCLUDING AUTONOMOUS DRIVING Cards; (d) AMD (chiplet) Packaging Course Leaders: Matthias Petzold – 12. Heterogeneous Integration on RDLs and/or 9. Wafer versus Panel Processing; Polymer Fraunhofer IZM, Mervi Paulasto-Kröckel – TSV-less Interposers (1): (a) Xilinx/SPIL’s TSV- Challenges and Solutions Aalto University, and Klaus-Juergen Wolter less SLIT and NTI; (b) Amkor’s TSV-less SLIM – TU Dresden Who Should Attend: and SWIFT with FOWLP; (c) SPIL’s TSV-less Packaging engineers involved in the development, Course Objective: FOWLP with Hybrid RDLs production, and reliability testing of semiconductor The amount of electronics in vehicles has increased 13. Heterogeneous Integration on RDLs and/or packages would benefit from the course. dramatically over the last several years and will TSV-less Interposers (2): (a) STATSChipPac’s R&D professionals interested in gaining a basic increase further in the future. Autonomous driving FOFC eWLB; (b) ASE’s TSV-less FOCoS; (c) understanding of the structure/property/process/ demands highly robust surround-sensing of the entire MediaTek’s TSV-less RDLs by FOWLP performance relationships in polymers and polymer- vehicle. The demand for alternative, more energy- 14. Heterogeneous Integration on RDLs and/or based materials used in electronic packaging will also efficient forms of mobility stimulates the application TSV-less Interposers (3): (a) Intel’s TSV-less find this course valuable. of electro mobility. Electronics modules integrated in EMIB; (b) Imac’s bridge + FOWLP; (c) 3D IC sensors and actuators facing harsh environment and 15. RELIABILITY MECHANICS AND Heterogeneous Integration for Application higher temperatures. Smaller packages and higher MODELING FOR IC PACKAGING - Processor Chipset integration levels are needed through embedded THEORY, IMPLEMENTATION, AND 15. Samsung’s Heterogeneous Integration on RDLs: systems in package, multi-die packages and finer pitch PRACTICES (a) for Mobile Applications and (b) for High-end packages. New packaging technologies have to be Course Leaders: Ricky Lee – HKUST and Applications qualified for the reliability and safety of automotive Xuejun Fan – Lamar University 16. Trends in FOWLP, FOPLP, and Heterogeneous standards. E-mobility increases today’s life time Integration Course Objective: requirements of automotive electronics. Additional Who Should Attend: This course aims to present a comprehensive to the driving time, the charging operations have If you (students, engineers, and managers) are coverage of reliability mechanics and modeling to be considered. To meet these new life time involved with any aspect of the electronics and under various loading conditions. In addition to the requirements, the qualification of electronics optoelectronic industry, you should attend this introduction of fundamentals, the course contents module is changing from the detection of defects to course. It is equally suited for R&D professionals and are arranged in four modules. Module 1 covers robustness validation. This approach to qualification is scientists. All the materials are based on the papers modeling under thermal loading, such as problems based on knowledge of physics of failure mechanisms and books published in the past three years, and related to mismatch of thermal expansion or non- and how they relate to specific mission profiles. each participant will receive more than 200 pages of uniform temperature distribution. Module 2 deals Based on broad practical experience with complete the lecture notes. with the modeling under mechanical loading, such as supply chain examples of robustness validation will be mechanical bending and/or drop impact. Module 3 demonstrated. Finally, an overview of the methods 14. POLYMERS FOR WAFER LEVEL will cover modeling under humidity/moisture loading of design for reliability with a focus on modeling and PACKAGING for moisture related problems, such as failures in simulation of materials interactions will be given. Course Leader: Jeffrey Gotro – InnoCentrix, soldering reflow as well as under HAST and biHAST. Course Outline: LLC Module 4 will introduce multi-physics modeling that 1. Electronics Packages for External Sensing and Course Objective: involves the combined thermal, moisture, electrical, e-Drive The course will provide an overview of polymers and mechanical loading. Theoretical foundation, 2. Robustness Validation of Automotive Electronics used in wafer level packaging and the important modeling implementation, and the best practices 3. Damage Mechanism in Automotive Electronics structure-property-process-performance for numerical simulations will be covered. Emerging 4. Design for Reliability of Automotive Electronics relationships for polymers used in wafer level trends and future perspectives in reliability mechanics packaging. The main learning objectives will be: 1) and modeling will be discussed. Who Should Attend: understand the types of polymers used in wafer level This PDC is dedicated to engineers and managers Course Outline: already involved in the field of reliability of electronics packages, including underfills (pre-applied and wafer 1. Fundamentals of Stress Analysis and packaging especially for automotive electronics and applied), mold compounds, and substrate materials; Computational Modeling for IC Packaging for those who need fundamental understanding on 2) gain insights on how polymers are used in Fan Out 2. Reliability Issues and Modeling under Thermal robustness validation and design for reliability. Wafer Level Packaging, specifically mold compounds Loading and polymer redistribution layers (RDL); and 3) 3. Reliability Issues and Modeling under Mechanical 17. FROM WAFER TO PANEL LEVEL learn the key polymer and processes challenges Loading PACKAGING in Fan Out Wafer Level Packaging including panel 4. Reliability Issues and Modeling under Moisture/ Course Leaders: Tanja Braun and Michael level processing. We will cover in more depth Humidity Loading Töpper – Fraunhofer IZM the chemistries, material properties, process 5. Reliability Issues and Modeling under Combined Course Objective: considerations, and reliability testing for polymers Loading – Multi-physics Modeling used in wafer level packaging including epoxy mold Panel Level Packaging (PLP) is one of the latest compounds and dielectric redistribution layers (RDL) Who Should Attend: trends in microelectronics packaging. Besides for eWLP. The course has been completely updated This course is intended for technical managers technology developments towards heterogeneous to include a detailed discussion of the polymers and and staff members, reliability engineers, scientific integration including multiple die packaging, passive polymer-related processing for Fan-Out Wafer Level researchers, and graduate students who are component integration in package and redistribution packaging (such as chip first and chip last (RDL first). involved in thermal/mechanical modeling, package layer or package-on-package approaches also larger design, material selection, qualification and reliability substrates formats are targeted. Manufacturing is Course Outline: assessment of chip-package interaction, package, and currently done on wafer level up to 12”/300 mm 1. Overview of Polymers used in Wafer Level and 330 mm respectively. For higher productivity package/board interaction. Packaging and therewith lower costs, larger form factors are 2. Wafer Level Process Flows (Chip-first versus introduced. Instead of following the wafer level Chip-last (RDL first)) roadmaps to 450 mm, PLP might be the next big 3. Epoxy Mold Compounds for eWLP step. PLP has the opportunity to adapt processes, 4. Photosensitive Polyimides and Polybenzoxazoles IMPORTANT NOTICE materials and equipment from other technology 5. Pre-applied Underfills and Wafer Level Underfills, areas. (PCB), Liquid Crystal It is extremely important to register Display (LCD) or solar equipment is manufactured Chemistry and Process in advance to prevent delays at 6. High Density Substrate Materials including on panel sizes and offer new approaches also for door registration. Course sizes PLP. However, an easy upscaling of technology when Coreless Substrates are limited.

14 moving from wafer to panel level is not possible. 3. Liquid Cooling of Very High-Power Electronics Materials, equipment and processes have to be - Advantages and Disadvantages of Liquid IMPORTANT NOTICE further developed or at least adapted. The PDC will Cooling Morning PD Courses 1 through give a status of the current Fan-in and Fan-out Wafer - When and Where to Consider Liquid over 9 or afternoon PD Courses 10 Level Packaging as well as Panel Level Packaging Air Cooling through 18 run concurrently. including Fan-out Panel Level Packaging substrate Coolant Types - Make sure you indicate which embedding approaches. This will include material - Limits of Single-Phase Liquid Cooling discussion, technologies, applications and market course you plan to attend in the Who Should Attend: morning and/or in the afternoon. trends as well as cost modelling. Engineers and technical managers who are involved in Course Outline: packaging technology development that necessitates As sessions run concurrent, 1. Introduction Advanced Packaging an understanding of heat sink design and optimization attendance is only allowed at one 2. Trends in Wafer Level Packaging in the context of the thermal management of session in the morning and 3. Fan-In and Fan-Out Wafer Level: Material, electronics should attend. one session in the afternoon. Processes, Applications See page 32 for registration 4. Introduction and Definition Level Packaging information 5. Fan-Out Panel Level Packaging: Technologies, Challenges and Opportunities 6. Substrate Embedding Technologies 7. Cost Modelling Who Should Attend: AREA ATTRACTIONS Anyone who is interested in Advanced Packaging, Touted as The Entertainment Capital of the World, Las Vegas offers something for Fan-in and Fan-out Wafer Level Packaging and the everyone. Most famous for its gambling, shopping, fine dining, entertainment, and transition to Panel Level Packaging should attend. Engineers and managers are welcome as detailed nightlife, Las Vegas is also known as a top three destination in the U.S. for business technology descriptions, as well as market trends, conventions. applications, and cost modelling are presented. It’s a city that caters to young and old, from those who crave the outdoors and 18. ELECTRONICS COOLING adventure, to those who want to be wined and dined and enjoy the nightlife. While TECHNOLOGIES FOR HANDHELD DEVICES, COMPUTING, AND HIGH- excursions to the Grand Canyon, Hoover Dam, and the American Alpine Institute POWER ELECTRONICS are all within reach, when you’re ready to relax and unwind, The Cosmopolitan of Las Course Leaders: William Maltz and Guy Vegas offers world-class restaurants, luxurious spas, unique entertainment, and sleeping Wagner – Electronic Cooling Solutions rooms that are more reminiscent of a private urban residence than they are of an Course Objective: actual hotel room. The objective of this course is to cover the major aspects of thermal design from hand-held consumer electronics devices up through liquid cooling of very high heat density devices. Rather than presenting “heat transfer 101,” the purpose of this course is to present a synopsis of the practical knowledge and best practices we at Electronic Cooling Solutions have gained by working on the thermal design of these devices. The course starts out looking at the thermal limits for natural convection and radiation cooling of hand-held devices. From there, it addresses forced convection of higher power devices including servers and datacom equipment. This will cover the use of various types of fans and blowers including the best position for locating them inside of the chassis. The acoustic challenges of using air movers will also be discussed. Finally, the practical aspects of when and how to implement liquid cooling will be presented. This will include looking at the advantages and disadvantages of liquid cooling as well as a discussion of the limits of single-phase liquid cooling. Course Outline: 1. Cooling of Handheld Devices - Cooling Limits Driven by Touch Temperature - Convection - Radiation - Use of Heat Spreaders and Heat Pipes - Use of Micro-Blowers - Importance of Solar Radiation 2. Cooling of Computers, Servers, Datacom Equipment - When to Use Air Movers - Axial Flow Fans vs. Centrifugal Blowers - Testing and Fan Acoustics - Fan Location: Push vs Pull - Limits of Air Cooling

15 Program Sessions: Wednesday, May 29, 8:00-11:40 a.m.

Session 1: Wafer Level Fan-Out Process Session 2: Next-Generation Wirebonding Session 3: Re-Distribution Layer and Integration and Die Attach/Sintering Additive Manufacturing

Committee: Packaging Technologies Committee: Interconnections Committee: Packaging Technologies joint with Emerging Technologies

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Bora Baloglu Matthew Yao C. S. Premachandran Amkor Technology Inc. GE Aviation GLOBALFOUNDRIES Email: [email protected] Email: [email protected] Email: [email protected]

Beth Keser Nathan Lower Kuldip Johal Intel Corporation Collins Aerospace Atotech USA, LLC. Email: [email protected] Email: [email protected] Email: [email protected]

1. 8:00 AM - 3D-MiM Fan-Out for 3D-MiM 1. 8:00 AM - SB²-WB a New Process Solution 1. 8:00 AM - Sub-Micron-Scale Cu RDL (MUST-in-MUST) Technology for Advanced for Advanced Wire-bonding Patterning Based on Semi-Additive Process System Integration Matthias Fettke, Andrej Kolbasow, Thorsten Teutsch, for Heterogeneous Integration Ann-Jhih Su, Terry Ku, CHung-Hao Tsai, Kuo-Chung Anna Palys, Georg Friedrich – Pac Tech - Packaging Hiroshi Kudo, Takamasa Takano, Satoru Kuramochi , Yee, and Douglas Yu – Taiwan Semiconductor Technologies GmbH Massaya Tanaka – Dai Nippon Printing Co., Ltd. Manufacturing Company

2. 8:25AM - Construction on FO-MCM With 2. 8:25 AM - Smart Wire Bond Solutions for 2. 8:25 AM - Sub-Micron RDL Patterning for C4 Bumps Built First Based on Chip Last SiP and Memory Packages Advanced Packaging Assembly Technology Basil Milton, Aashish Shah, Hui Xu, Odal Kwon, Gary Ken-Ichiro Mori, Douglas Shelton, Yoshio Goto, Chih-Hsun Hsu, C. Key Chung, C.F. Lin, Yih Jenn Jiang, Schulze, Ivy Qin, Nelson Wong – Kulicke and Soffa, Yasuo Hasegawa, Seiya Miura – Canon Inc. Trista Xie – Siliconware Precision Industries Co., Ltd. Inc.

3. 8:50AM - Feasibility Study of Fan-Out 3. 8:50 AM - Determination of Relationship 3. 8:50 AM - Optimization of Electrolytic Panel-Level Packaging for Heterogeneous Between Cu-Al IMC Kinetics and Bond Pad Plating Process for Challenging Fan-Out Integration Characteristics Panel Level Package Designs Cheng-Ta Ko, Henry Yang – Unimicron; John Lau, Subramani Manoharan, Sriram Jayanthi, Chandradip Ralph Zoberbier, Christian Ohde – Atotech Ming Li - ASM Patel, Stevan Hunter, Patrick McCluskey – University Deutschland GmbH of Maryland

Refreshment Break: 9:15-10:00 a.m.

4. 10:00AM - Development of Ultra-Thin FO 4. 10:00 AM - Au-Rich/Sn-Bi 4. 10:00 AM - Embedded Actives and Package-on-Package for Mobile Application Interconnection in Chip-on-Module Package Microfluidics for the Design of Compact RF Hsiang-Yao Hsiao, Soon Wee Ho, Lim Siak Boon; Jin Wang, Qian Wang, Jian Cai – Tsinghua University; Systems Wai Leong Ching, Chong Ser Choong, Lim Pei Xinnan Hou, Ke Du, Lixin Zhao – GalaxyCore Inc. Mohd Ifwat Mohd Ghazali, Saikat Mondal, Saranraj Siang, Tai Chong Chai – Institute of Microelectronics, Karuppuswami, Kyoung Youl Park – Agency for A*STAR Defense Development; Premjeet Chahal – Michigan State University

5. 10:25AM - Development of Wafer Level 5. 10:25 AM - The Properties of Cu Sinter 5. 10:25 AM - Fully Additively Manufactured Process for the Fabrication of Advanced Paste for Pressure Sintering at Low- Tunable Active Frequency Selective Surfaces Capacitive Fingerprint Sensor Using Embedded Temperature with Integrated On-Package Solar Cells Silicon Fan-Out (eSiFO®) Technology Jung-Lae Jo; Shinichi Yamauchi, Kei Anai, Takahiko Syed Abdullah Nauroze, Xuanke He, Syed Nauroze – Shuying Ma, Fengxia Zheng, Daquan Yu, Peng Li, Sakaue – Mitsui Mining & Smelting Co., Ltd. Georgia Institute of Technology Weidong Liu - Huantian Technology Electronics Co., Ltd.; Jambo Yu, Jason Goodelle – Synaptics Incorporated

6. 10:50AM - Three-Dimensional Integrated 6. 10:50 AM – Low-Temperature Sintering 6. 10:50 AM - First Demonstration of a Low- Circuit (3D-IC) Package Using Fan-Out of Dendritic Cu Based Pastes for Power Cost/Customizable Chip Level 3D Printed Technology Interconnection Microjet Hotspot-Targeted Cooler for High- Jun Kyu Lee, Sang Yong Park, Young Ho Kim, Jae Gang Li, Jilei Fan, Siyuan liao, Pengli Zhu, Baotan Power Applications Cheon Lee, Yong Tae Kwon, Jong Heon Kim, Nam Zhang, Tao Zhao, Rong Sun, Ching-Ping Wong – Tiwei Wei, Herman Oprins, Eric Beyne, Vladimir Chul Kim, Chang Woo – NEPES Corporation Shenzhen Institute of Advanced Technology Cherman, Ingrid De Wolf – IMEC; Martine Baelmans – KU Leuven

7. 11:15AM - Ultra-High Density I/O Fan- 7. 11:15 AM - A New Development of Direct 7. 11:15 AM - Rapid Production of Out Design Optimization with Signal and Bonding to Aluminum and Nickel Surfaces Customized 3D Electronics via Hybrid Power Integrity by Silver Sintering in Air Atmosphere Additive Manufacturing Technology Chih-Yi Huang, Chen-Chao Wang, Hung-Chun Ly May Chew, Wolfgang Schmitt – Heraeus, Ji Li, Yang Wang, Jianglin He, Handa Liu – Southeast Kuo, Ming-Fong, Jhong, Tsun-Lung Hsieh, Mi-Chun Tamira Stegmann, Erika Schwenk, Monique Dubis University Hung, Keng Tuan Chang – Advanced Semiconductor – Hochschule Aschaffenburg, University of Applied Engineering, Inc. Sciences

16 Program Sessions: Wednesday, May 29, 8:00-11:40 a.m.

Session 4: Advancements in Automotive Session 5: Bonding Manufacturing Session 6: Emerging Flexible Hybrid and Power Devices Technologies Electronics

Committee: Materials & Processing Committee: Assembly & Manufacturing Technology Committee: Emerging Technologies

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Praveen Pandojirao-S Valérie Oberson Hongqing Zhang Johnson & Johnson Services, Inc. IBM Corporation IBM Corporation Email: [email protected] Email: [email protected] Email: [email protected]

Lewis Huang Paul Houston Jong-Hoon Kim Senju Metal Industry Co., Ltd. Engent, Inc. Washington State University, Vancouver Email: [email protected] Email: [email protected] Email: [email protected]

1. 8:00 AM - Solid-Liquid InterDiffusion 1. 8:00 AM - Comprehensive Study of 1. 8:00 AM - Stretchable and Printable (SLID) Bonding for Thermally Challenging Copper Nano-Paste for Cu-Cu Bonding Medical Dry Electrode Arrays on Textile for Applications Ser Choong Chong, Pei Siang – Institute of Electrophysiological Monitoring Knut E. Aasmundtveit, Hoang-Vu Nguyen, Andreas Microelectronics Yougen Hu, Hui Wang, Yaoxu Xiong, Han Gu, Pengli Larsson – University of South-Eastern Norway; Thi- Zhu, Guanglin Li, Rong Sun – Shenzhen Institutes of Thuy Luu – Zimmer & Peacock; Torleif A. Tollefsen Advanced Technology; Ching-Ping Wong – Georgia – Tegma Institute of Technology

2. 8:25 AM - Fluxless Bonding Technique 2. 8:25 AM - Enhanced Performance of 2. 8:25 AM - Screen-Printed Flexible of Diamond to Copper Using Silver-Indium Laser-Assisted Compression Bonding (LACB) Coplanar Waveguide Transmission Lines: Multilayer Structure Compared with Thermal Compression Multi-Physics Modeling and Measurement Roozbeh Sheikhi, Yongjun Huo, Chin C. Lee – Bonding (TCB) Technology Nahid Aslani Amoli, Sridhar Sivapurapu, Rui Chen, University of California, Irvine Kwang-Seong Choi, Yong-Sung Eom, Seok Hwan Moon – ETRI; Yi Zhou, Mohamed Bellaredj, Paul Kohl, Suresh Kwangjoo Lee, Jung Hak Kim, Ju Hyeon Kim – LG Chem; Gil-Sang Sitaraman, Madhavan Swaminathan – Georgia Institute Yoon – Korea Institute of Industrial Technology; Kwang-Hee Lee, of Technology Chul-Hee Lee – Inha University; Geun-Sik Ahn – Protec

3. 8:50 AM - Formulation and Processing 3. 8:50 AM - A Study of 3D Packaging 3. 8:50 AM - Inkjet-Printed Filtering of Conductive Polysulfide Sealants for Interconnection Performance Affected Antenna on a Textile for Wearable Automotive and Aerospace Applications by Thermal Diffusivity and Pressure Applications Bo Song, Fan Wu, Kyoung-Sik Moon, C. P. Wong – Transmission Hsuan-Ling Kao, Chun-Hsiang Chuang – Chang Gung Georgia Institute of Technology Jinsan Jung, Junsu Lim, Jiin Yu, Sungill Cho, Dong W. University; Cheng-Lin Cho – National Tsing Hua Kim, SangHo An – Samsung Electronics Company, University Ltd.

Refreshment Break: 9:15-10:00 a.m.

4. 10:00 AM - Challenges and Approaches 4. 10:00 AM - Vertical Laser Assisted 4. 10:00 AM - Mechanical and Electrical to Developing Automotive FCBGA Grade 1/0 Bonding for Advanced “3.5D” Chip Characterization of FOWLP-Based Flexible Package Capability Packaging Hybrid Electronics (FHE) for Biomedical Rajen Dias – Amkor Technology, Inc.; Mike Kelly, Andrej Kolbasow, Matthias Fettke, Thorsten Teusch – Sensor Application Devarajan Balaraman, KwangSeok Oh, JoonYoung Pac Tech – Packaging Technologies GmbH Yuki Susumago, Hisashi Kino, Takafumi Fukushima, Park, Hideaki Shoji, Tomio Shiraiwa – Amkor Tetsu Tanaka, Takafumi Fukushima – Tohoku Technology, Inc. University

5. 10:25 AM - Advanced Substrates for GaN- 5. 10:25 AM - Optimization of a BEOL 5. 10:25 AM - A Wearable Fingernail Based HEMTs Devices Aluminum Deposition Process Enabling Deformation Sensor and Three-Dimensional Anthony Cibié, Julie Widiez, René Escoffier, Denis Wafer Level Al-Al Thermo-Compression Finite Element of Fingertip Blachier, Stéphane Bécu, Perceval Coudrain, William Bonding Katsuyuki Sakuma, Bucknell Webb, Jeff Rogers – IBM Vandendaele, Jerome Biscarrat, Charlotte Gillot, Sebastian Schulze, Matthias Wietstrick, Mirko Thomas J. Watson Research Center Matthew Charles – CEA-LETI Fraschke, Mehmet Kaynak – IHP; Peter Kerepesi, Helmut Kurz, Bernhard Rebhan – EVGroup

6. 10:50 AM - A New Reliable, Corrosion 6. 10:50 AM - Self-Assembly Process for 3D 6. 10:50 AM - Heterogeneous Integration Resistant Gold-Palladium Coated Copper Die-to-Wafer using Direct Bonding: A Step of a Fan-Out Wafer-Level Packaging Based Wire Material Forward Toward Process Automation Foldable Display on Elastomeric Substrate Sandy Klengel, Robert Klengel, Tino Stephan, Jan Amandine Jouve, Loïc Sanchez, Clément Castan, Arsalan Alam, Amir Hanna, Randall Irwin, Goutham Schischka,Matthias Petzold – Fraunhofer IMWS; Emmanuel Rolland, Frank Fournel, Rémi Franiatte, Ezhilarasu, Hyunpil Boo, Yuan Hu, Chee Wei Wong, Motoki Eto, Noritoshi Araki, Takashi Yamada – Brigitte Montmayeul, Severine Cheramy – CAE-Leti Timothy Fisher, Subramanian S. lyer – University of Nippon Micrometal Corporation California, Los Angeles

7. 11:15 AM - Ultrasonic-Accelerated 7. 11:15 AM - A Single Bonding Process to 7. 11:15 AM - A Study on the Flexible Chip- Intermetallic Joint Formation with Achieve Various Organic-Inorganic Substrate on-Fabric (COF) Assembly Using Anisotropic Composite Solder for High-Temperature Integration in IOT Conductive Films (ACFs) Materials Power Device Packaging Tilo Hongwei Vang, C. Robert Kao – National Taiwan Seoung-Yoon Jung, Kyung-Wook Paik – Korea Hongjun Ji, Mingyu Li, Weiwei Zhao – Harbin Institute University, Akitsu Shigetou – National Institute for Advanced Institute of Science and Technology of Technology Materials Science

17 Program Sessions: Wednesday, May 29, 1:30-5:10 p.m.

Session 7: Advances in Flip Chip Technology Session 8: Material and Process Trends in 9: Wearables and Thin Package Reliability FOWLP & PLP Session & CPI

Committee: Packaging Technologies Committee: Materials & Processing Committee: Thermal/Mechanical Simulation & Characterization

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Dan Baldwin Tanja Braun Przemyslaw Gromala H.B. Fuller Company Fraunhofer IZM Robert Bosch GmbH Email: [email protected] [email protected] email: [email protected]

Michael Gallagher Yi Li Yong Liu DuPont Electronics and Imaging Intel Corporation ON Semiconductor Email: [email protected] [email protected] email: [email protected]

1. 1:30 PM - 7nm Chip-Package Interaction 1. 1:30 PM - Laser Releasable Temporary 1. 1:30 PM - Effect of Charging Cycle Study on a Fine Pitch Flip Chip Package Bonding Film with High Thermal Stability Elevated Temperature Storage and Thermal with Laser Assist Bonding and Mass Reflow Yongsuk Yang, Kyosung Hwang, Robin Gorrell – 3M Cycling on Thin Flexible Technology Pradeep Lall, Amrit Abrol – Auburn University; Jason Ming-Che Hsieh, NamJu Cho – STATS ChipPAC Pte. Marsh – NextFlex; Ben Leever – Air Force Research Ltd.; Ian Hsu, Chi-Yuan Chen, Stanley Lin, Ta-Jen Yu – Laboratory MediaTek, Inc.

2. 1:55 PM - Ultra Large Area SIPs and 2. 1:55 PM - Design and Demonstration of 2. 1:55 PM - Bladder Inflation Stretch Test Integrated mmW Antenna Array Module for 1µm Low Resistance RDL Using Panel Scale Method for Reliability Characterization of 5G mmW Outdoor Applications Processes for High Performance Computing Wearable Electronics Pouya Talebbeydokhti, Sidharth Dalmia, Trang Thai, Applications Benjamin Stewart, Suresh Sitaraman – Georgia Sharon Tal, Raanan Sover – Intel Corporation Bartlet DeProspo, Chandra Nair, Emanuel Torres, Fuhan Liu, Institute of Technology Mohan Kathaperumal, Rao Tummala – Georgia Institute of Technology; Frank Wei, Ye Chen – DISCO Corporation; Aya Momozawa, Atsushi Kubo – Ohka Kogyo Co., Ltd.

3. 2:20 PM - Hybrid Approach for Large Size 3. 2:20 PM - Advances in Temporary Carrier 3. 2:20 PM - Study of BEOL Failure Mode FC-BGA to Enhance Thermal and Electrical Technology for High-Density Fan-Out in Flip Chip Packages at High-Temperature Performance Including Power Delivery Device Build-Up Conditions Heesok Lee, Younheok Im, Jisoo Hwang, Junghwa Alain Phommahaxay, Arnita Podpod, Pieter Bex, John Wei Wang, Yangyang Sun, Xuefeng Zhang, Lejun Kim, James Jeong, Youngsang Cho, Heejung Choi, Slabbekoorn, Julien Bertheau, Adbellah Salahouelhadj, Wang, Mark Schwarz, Bill Stone, Ahmer Syed – Youngmin Shin - Samsung Electronics Company, Ltd. Eric Beyne – IMEC; Alice Guerrero, Kim Yess, Kim Qualcomm Technologies, Inc. Arnold – Brewer Science

Refreshment Break: 2:45-3:30 p.m.

4. 3:30 PM - Package-on-Package Micro- 4. 3:30 PM - Development of Novel 4. 3:30 PM - A Novel Metal Scheme BGA Microstructure Interaction with Bond Low-Temperature Curable Positive-Tone and Bump Array Design Configuration Assembly Parameters Photosensitive Dielectric Materials with to Enhance Advanced Si Packages CPI Pascale Gagnon, Clément Fortin, Tom Weiss – IBM High Reliability Reliability Performance by Using Finite Corporation Yutaro Koyama, Yuki Masuda, Yu Shoji, Keika Element Modeling Technique Hashimoto, Masao Tomikawa – Toray Industries, Inc. Kuo-Chin Chang, Mirng-Ji Lii, Steven Hsu, Hao-Chun Liu, Yen-Kun Lai, Sheng-Han Tsai, Chieh-Hao Hsu – Taiwan Semiconductor Manufacturing Company, Ltd.

5. 3:55 PM - Low Cost Flip-Chip Stack for 5. 3:55 PM - Highly Reliable Photosensitive 5. 3:55 PM - Assessment of CMP Fill Partitioning Processing and Memory Negative-Tone Polyimide with Low Cure Pattern Effect on the Thermal Performance Fabian Hopsch, Andy Heinig – Fraunhofer IIS/EAS Shrinkage of Multilayered BEOL Interconnects in Daisaku Matsukawa, Hiroko Yotsuyanagi, Shiori Integrated Circuits Sakakibara, Noriyuki Yamazaki, Tetsuya Enomoto, Assaad El Helou, Peter Raad – Southern Methodist Takeharu Motobe – Hitachi Chemical DuPont University; Archana Venugopal – Texas Instruments, MicroSystems, LLC Inc.

6. 4:20 PM – High-Density, Large Area 6. 4:20 PM - Advanced Pre-Cleaning 6. 4:20 PM - Three-Dimensional Simulation Indium Bump Bonding Process Development Method of Seed Layer Sputtering for Fan- of the Thermo-Mechanical Interaction for CMOS Camera Integration Out Panel Level Packaging Between the Micro-Bump Joints and Cu Matthew B. Jordan, John Murdick, Lauren Rohwer, Tetsushi Fujinaga – ULVAC, Inc. Protrusion in Cu-filled TSVs of the High T. A. Friedmann, M. David Henry – Sandia National Bandwidth Memory (HBM) Structure Laboratories Jie-Ying Zhou, Shui-Bao Liang, Cheng Wei, Min- Bo Zhou, Xiao Ma, Xin-Ping Zhang – South China University of Technology

7. 4:45 PM - Impact of LTS on Electronic 7. 4:45 PM - Investigation and Methods 7. 4:45 PM - Study of Board Level Reliability Package Dynamic Warpage Requirement Using Various Release and Thermoplastic of eWLB (Embedded Wafer Level BGA) for Ron Kulterman – Flex, Ltd.; Wei Keat Loh – Intel Bonding Materials to Reduce Die Shift 0.35mm Ball Pitch Corporation; Haley Fu – International Electronics and Wafer Warpage for eWLB Chip-First Seung Yoon, Kang Hai Lee, Yeow Kheng Lim, Seng Manufacturing Intiative (iNEMI) Processes Guang Chow –STATS ChipPAC Pte. Ltd.; NW Liu, Michelle Fowler, John P. Massey – Brewer Science, Yenyao Chi, Benson Lin – Mediatek, Inc. Inc.; Tanja Braun, Steve Voges, Robert Gernhardt, Markus Woehrmann; Fraunhofer IZM 18 Program Sessions: Wednesday, May 29, 1:30-5:10 p.m.

Session 10: Dicing and Encapsulation Session 11: Automotive and Harsh Session 12: Advanced Photonic Devices & Technologies Environment Reliability Packaging

Committee: Assembly & Manufacturing Technology Committee: Applied Reliability Committee: Photonics

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Garry Cunningham Vikas Gupta Stéphane Bernabé NGC Texas Instruments, Inc. CEA-LETI Email: [email protected] [email protected] Email: [email protected]

Paul Tiner Sandy Klengel Gordon Elger Texas Instruments, Inc. Fraunhofer Institute for Microstructure of Materials and Technische Hochschule Ingolstadt Email: [email protected] Systems Email: [email protected] [email protected]

1. 1:30 PM - A More than Moore Enabling 1. 1:30 PM - Improvement on Thermal- 1. 1:30 PM - Micro-Fabricated SERF Atomic Wafer Dicing Technology Aging Reliability of Ag Sinter Joining on Gold Magnetometer for Weak Gradient Magnetic Jeroen van Borkulo, Rogier Evertsen, Richard van der Surface Finished Substrates via a Preheating Field Detection Stam – ASM Pacific Technology Treatment Xiang Yue, Jingtang Shang, Chen Ye – Southeast Zheng Zhang, Chuan Tong Chen, Katsuaki Suga University Numa – University

2. 1:55 PM - Plasma Dicing Integration 2. 1:55 PM - Package Material Selection 2. 1:55 PM - Highly Reliable White LED Schemes for Scribe Lane Layout and the Criteria for High-Temperature Automotive Chip Fabricated by Direct Printing Phosphor Impact on Die Strength Applications Glass Layer on LED Wafer David Parker – STMicroelectronics Rene Rongen, Amar Mavinkurve, Orla O’Halloran, Yang Peng, Yun Mou, Hao Wang, Mingxiang Chen, Norman Owens, Yann Weber, Pascal Oberndorff, Xiaobing Luo – Huazhong University of Science and Mark Luke Farrugia, Erik van Olst, Michiel van Technology Soestbergen – NXP Semiconductors

3. 2:20 PM - Advanced Dicing Technologies 3. 2:20 PM - Solder Joint Reliability of 3. 2:20 PM - Collective Curved CMOS Sensor for Combination of Wafer-to-Wafer and Double-Side Mounted DDR Modules for Process: Application for High-Resolution Collective Die to Wafer Direct Bonding Consumer and Automotive Applications Optical Design and Assembly Challenges Fumihiro Inoue, Alain Phommahaxay, Arnita Podpod, Dongji Xie, Dongji Dongji, Joe Hai, Zhongming Wu, Bertrand Chambion, Christophe Gaschet, Marc Samuel Suhard, Erik Sleeckx, Kenneth June Rebibis, Manthos Economou – Nvidia Corp. Lombard, Maïlys Fernandez, Fabien Zuber, Stéphane Andy Miller, Eric Beyne – IMEC; Hitoshi Hoshino Caplet, Aurélie Vandeneynde, David Henry – CEA- Berthold Moeller – DISCO Corporation LETI; Emmanuel Hugot – Laboratory of Astrophysics of Marseille Refreshment Break: 2:45-3:30 p.m.

4. 3:30 PM - Active Control of NCF Fillet 4. 3:30 PM - Reliability Investigation of 4. 3:30 PM - Silicon Photonic 4X4 Switch Shape for 3D CoW by Multibeam Laser Extremely Large Ratio Fan-Out Wafer-Level with Flip-Chip Integrated Semiconductor Bonder Package with Low Ball Density for Ultra- Optical Amplifiers Keiko Ueno, Kazutaka Honda, Tsuyoshi Ogawa – Short-Range Radar Fuad Doany, Nicolas Dupuis, Russell Budd, Laurent Hitachi Chemical Company, Ltd. PuShan Huang, C.K. Yu, W.S. Chiang, M.Z. Lin, Schares, Christian Baks, Daniel Kuchta, Benjamin Lee Y.H. Fang, M.J. Lin, N.W. Liu, Benson Lin, Ian Hsu – – IBM Research MediaTeK, Inc.

5. 3:55 PM - Ultrafast Laser Scribe: An 5. 3:55 PM - Fatigue Behaviour of Lead-Free 5. 3:55 PM - Y-Branched Multimode / Improved Metal and ILD Ablation Process Solder Joints Under Combined Thermal and Single-Mode Polymer Optical Waveguides Julia Chiu, Tyler Osborn, Aaron Gore – Intel Vibration Loads for Low-Loss WDM MUX Device: Corporation; Daragh Finn, David Lord, Jon Mellen – Karsten Meier, Maria Winkler, Karlheinz Bock – Fabrication and Characterization Electro Scientific Industries, Inc. Technical University of Dresden; David Leslie, Abhijit Takaaki Ishigure, Tomoki Nakayama, Fukino Nakazaki, Dasgupta - University of Maryland Hiroki Hama – Keio University

6. 4:20 PM - Reliability and Benchmark 6. 4:20 PM - Prognostication of Accrued 6. 4:20 PM - Vertically Stacked and of 2.5D Non-Molding and Molding Damage and Impending Failure Under Directionally Coupled Cavity-Resonator- Technologies Temperature-Vibration in Automotive Integrated Grating Couplers for Integrated- Yu-Hsiang Hsiao, Che-Ming Hsu, Yi-Sheng Lin, Electronics Optic Beam Steering Chien-Lin Chang Chien – Advanced Semiconductor Pradeep Lall, Tony Thomas, Jeff Suhling – Auburn Shogo Ura, Junichi Inoue – Kyoto Institute of Engineering, Inc. University Technology; Kenji Kintaka – National Institute of Advanced Industrial Science and Technology

7. 4:45 PM - Laser-Induced Trench Design, 7. 4:45 PM - Electrochemical Impedance 7. 4:45 PM - CiB (Chip-in-Board) Optical Optimisation and Validation for Restricting Spectroscopy (EIS) for Monitoring the Water Engine Module Using Advanced Fan-Out Capillary Underfill Spread in Advanced Load on PCBAs to Predict Electrochemical Package Technology Packaging Configurations Migration Under DC Loads Sang Yong Park, Jun Kyu Lee, Young Tae Kwon, Gul Zeb, David Danovitch – University of Sherbrooke; Simone Lauser, Theresia Richter – Robert Bosch Jong Heon, Nam Chul Kim, Chang Woo Lee, Jo Eric Turcotte – IBM Canada, Ltd. GmbH; Rajan Ambat, Vadimas Verdingovas – Hyun Nam, Ji Ni Shim, Sung Hyuk Lee – NEPES Technical University of Denmark Corporation

19 Program Sessions: Thursday, May 30, 8:00-11:40 a.m.

Session 13: Technologies Enabling 3D and Session 14: Fine Pitch Solder-Free Bonded Session 15: High-Bandwidth Packaging Heterogeneous Integration Interconnects

Committee: Packaging Technologies Committee: Interconnections Committee: High-Speed, Wireless & Components

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Peng Su Chuan Seng Tan P. Markondeya Raj Juniper Networks Nanyang Technological University Florida International University Email: [email protected] Email: [email protected] Email: [email protected]

Subhash L. Shinde Tom Gregorich Amit P. Agrawal University of Notre Dame Zeiss Semiconductor Manufacturing Technology Microsemi Corporation Email: [email protected] Email: [email protected] Email: [email protected]

1. 8:00 AM - Active Interposer Technology 1. 8:00 AM - Fine-Pitch (≤10 μm) Direct 1. 8:00 AM - Electrical Performance for Chiplet-Based Advanced 3D System Cu-Cu Interconnects Using In-Situ Formic Limits of Fine-Pitch Interconnects for Architectures Acid Vapor Treatment Heterogeneous Integration Perceval Coudrain, Jean Charbonnier, Rémi Vélard, Siva Chandra Jangam, Umesh Mogera, Pranav Ahmet Durgun, Zhiguo Qian, Kemal Aygun, Ravi Arnaud Garnier, Didier Lattard, Pascal Vivet, Fabienne Ambhore, Subramanian S. Iyer – University of Mahajan, Tim Tri Hoang, Sergey Shumarayev – Intel Ponthenier, Thierry Mourier – CEA-LETI; Andrea California; Adeel Bajwa, Tom Colosimo, Tom Corporation Vinci – Intitek; Alexis Farcy – STMicroelectronics Palumbo, Dominick DeAngelis, Bob Chylak – Kulicke and Soffa, Inc.

2. 8:25 AM - Process Development of Power 2. 8:25 AM – Low-Temperature Cu Inter- 2. 8:25 AM - A High-Bandwidth Fine-Pitch Delivery Through Wafer Vias for Silicon connect with Chip to Wafer Hybrid Bonding 2.57Tbps/mm In-Package Communication Interconnect Fabric Guilian Gao, Laura Mirkarimi, Thomas Workman, Gill Link Achieving 48fJ/Bit/mm Efficiency Meng-Hsiang Liu, Amir Hanna, Yandong Luo, Zhe Fountain, Jeremy Theil, Gabe Guevara, Ping Liu, Bongsub Nicolas Pantano, Geert Van der Plas, Pieter Bex, Wan, Subramanian S. Iyer – University of California, Lee, Pawel Mrozek, Michael Huynh – Xperi Corporation; Philip Nolmans, Dimitrios Velenis, Eric Beyne – IMEC; Los Angeles Catharina Rudolph, Thomas Werner, Anke Hanisch – Marian Verhelst – KU Leuven Fraunhofer Institute for Reliability and Micro-Integration, IZM – ASSID

3. 8:50 AM - Active Through-Silicon 3. 8:50 AM - Cu Inter-Diffusion Behavior on 3. 8:50 AM - A New SI-PI Co-Simulation Interposer Based 2.5D IC Design, Wafer-to-Wafer Hybrid Bonding Approach for Efficient Consideration of Fabrication, Assembly and Test Seokho Kim, Pilkyu Kang, Taeyeong Kim, Kyuha Lee Coupling Between PDN and SDN Jayasanker Jayabalan, Vivek Chidambaram, Sharon Joohee Jang – Samsung Electronics Company, Ltd. Heeseok Lee, Jisoo Hwang, Youngmin Shin – Samsung Lim Pei Siang, Wang Xiangyu, Jong Ming Chinq, Surya Electronics Company, Ltd. Bhattacharya – Institute of Microelectronics

Refreshment Break: 9:15-10:00 a.m.

4. 10:00 AM - System on Integrated Chips 4. 10:00 AM - Low-Resistance and 4. 10:00 AM - Signal Integrity of Submicron (SoIC) for Next-Generation Advanced System High-Strength Copper Direct Bonding InFO Heterogeneous Integration for High- Integration Technology in No-Vacuum Ambient using Highly Performance Computing Applications M.F. Chen, W.C. Chiou, F.C. Chen, C.H. Yu – Taiwan (111)-Oriented Nano-Twinned Copper Chuei-Tang Wang, Jeng-Shien Hsieh, Victor C. Y. Semiconductor Manufacturing Company, Ltd. Jing-Ye Juang, Kai-Cheng Shie, Yu-Jin Li, Chih Chen - Chang, Shih-Ya Huang, T. Ko, Han-Ping Pu, Douglas National Chiao Tung University; K. N. Tu – University Yu – Taiwan Semiconductor Manufacturing Company, of California, Los Angeles Ltd.

5. 10:25 AM - Die-to-Wafer (D2W) 5. 10:25 AM - Sub-10µm Pitch Hybrid Direct 5. 10:25 AM - 28GHz Band Pass Filter Using Processing and Reliability for 3D Packaging Bond Interconnect Development for Die-to- Through Fused Silica Via (TFV) Technology of Advanced Node Logic Die Hybridization Renuka Bowrothu, Seahee Hwangbo, Yong Kyu Yoon Luke England, Daniel Fisher, Katie Rivera, William John Mudrick, Jonatan Sierra-Suarez, Matthew B. – University of Florida; Anthony Ng’Oma, Cheolbok Guthrie – GLOBALFOUNDRIES; Calvin Lee, Zeke Jordan, T.A. Friedmann, Robert Jarecki, M. David Kim – Corning, Inc. Chen – Advanced Semiconductor Engineering, Inc. Henry – Sandia National Laboratories

6. 10:50 AM - Cu Pillar with Nanocopper 6. 10:50 AM - Innovative Packaging 6. 10:50 AM - Enabling Ultra-Thin Die Caps: The Next Interconnection Node Solutions of 3D Double Side Molding to Wafer Hybrid Bonding for Future Beyond Traditional Cu Pillar with System in Package for IoT and 5G Heterogeneous Integrated Systems Vanessa Smet, Ramon Sosa, Kashyap Mohan, Antonia Application Alain Phommahaxay, Samuel Suhard, Pieter Bex, Antoniou, Rao Tummala – Georgia Institute of Mike Tsai, Ryan Chiu, Dick Huang, Feng Kao, Eric He, Serena Iacovo, John Slabbekoorn, Fumihiro Inoue, Lan Technology J. Y. Chen, Simon Chen, Jensen Tsai, Yu-Po Wang – Peng, Koen Kennes, Erik Sleeckx,Eric Beyne – IMEC Siliconware Precision Industries Co., Ltd.

7. 11:15 AM - The Thermal Dissipation 7. 11:15 AM - Cu-Cu Bonding by Low- 7. 11:15 AM - Enhancing Efficiency of Characteristics of the Novel System-in- Temperature Sintering of Self-Healable Cu Antenna-in-Package (AiP) by Through-Silicon- Package Technology (ICE-SiP) for Mobile Nanoparticles Interposer (TSI) with Embedded Air Cavity and Packages and 3D High-End Packages Junjie Li, Qi Liang, Chen Chen, Tielin Shi, Guanglan Polyimide Dielectric Micro-Substrate Taejoo Hwang, Dan (Kyung Suk) Oh, Eunseok Song, Liao, Zirong Tang – Huazhong University of Science & Yunna Sun; Yunting, Sun, Jiangbo Luo, Huiying Wang, Jaechoon Kim, Jangwoo Lee, Seung Kon Mok, Kilsoo Technology Zhuoqing Yang, Yan Wang, Guifu Ding – Shanghai Jiao Kim – Samsung Electronics Company, Ltd. Tong University, Kwangwoo Han - Samsung

20 Program Sessions: Thursday, May 30, 8:00-11:40 a.m.

Session 16: Advanced Materials for High- Session 17: Materials and Design for Session 18: Warpage and Material Speed Electronics Reliability of Next Generation Packages Performance

Committee: Materials & Processing Committee: Applied Reliability Committee: Thermal/Mechanical Simulation & Characterization

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Yoichi Taira Varughese Mathew Pradeep Lall Keio University NXP Semiconductors Auburn University Email: [email protected] Email: [email protected] Email: [email protected]

Yu-Hua Chen Lakshmi Narayan Ramanathan Karsten Meier Unimicron Technology Corporation Microsoft Corporation Technical University of Dresden Email: [email protected] Email: [email protected] Email: [email protected]

1. 8:00 AM - Low-Loss Glass Substrates 1. 8:00 AM - Highly (111) Oriented 1. 8:00 AM - Improved Finite Element Formulated with a Variety of Dielectric Nanotwinned Cu for High Fatigue Resistance Modeling of Moisture Diffusion Considering Characteristics for mm Wave Applications in Fan-Out Wafer-Level Packaging Discontinuity at Material Interfaces in Kazutaka Hayashi, Nobutaka Kidera, Yoichiro Sato – Yu-Jin Li, Chih-Han Tseng, I-Hsin Tseng – National Electronic Packages AGC Inc. Chiao Tung University; Benson Lin, Cia-Cheng Chang Leila Saveri, Xuejun Fan – Lamar University; Rahul – MediaTek, Inc. Joshi, Keith Newman – Advanced Micro Devices, Inc.

2. 8:25 AM - Evaluation of Fine-Pitch 2. 8:25 AM - WLCSP Package/PCB Design 2. 8:25 AM - Study of Thermal Aging Routing Capabilities of Advanced Dielectric for Board Level Reliability Improvement Behavior of Epoxy Molding Compound for Materials for High-Speed Panel-RDL in Jason Chiu, Kuo-Chin Chang, Pei-Haw Tsao, Applications in Harsh Environments 2.5D Interposer and Fan-Out Packages Steve Hsu, Mirng-Ji Lii – Taiwan Semiconductor Adwait Inamdar, Alexandru Prisacaru, Martin Shreya Dwarakanath, Fuhan Liu, Pulugurtha Markondeya Raj, Manufacturing Company, Ltd. Fleischman – Robert Bosch GmbH; Agnes Veres Mohanalingam Kathaperumal, Rao R Tummala – Georgia Institute – Robert Bosch Kft; Bongtae Han – University of of Technology; Atsushi Kubo – Tokyo Ohka Kogyo Co; Daichi Maryland Okamaoto – Taiyo Ink Mfg. Co.

3. 8:50 AM - Attenuation of High-Frequency 3. 8:50 AM - Assessing the Reliability of 3. 8:50 AM - Warpage Variation Analysis Signals in Structured Metallization on Glass: Highly Stretchable Interconnects for Flexible and Model Prediction for Molded Packages Comparing Different Metallization Techniques Hybrid Electronics Yuling Niu, Wei Wang, Zhijie Wang, Mark Schwarz, With 24GHz Signals and Higher Frequencies Rajesh Sivasubramony, Ashwin Zachariah, Arun Raj, Ahmer Syed – Qualcomm Technologies, Inc. Martin Letz, Matthias Jotz – SCHOTT AG; Matthias Jost, Holger Maune – Mark Poliks Peter Borgesen - Binghamton University; Technische Universität Darmstadt; Alex Bruderer – Varioprint AG; Manuel Martina – Schweizer Electronics AG; Tetsuya Onishi – Grand Joint Technology Nancy Stoffel, David Shaddock, Liang Yin - GE Global Ltd.; Masatoshi Takayama – KOTO Electric Co.; Siddharth Ravichandran – Georgia Research Institute of Technology; Brandon Gore – Samtec Microelectronics

Refreshment Break: 9:15-10:00 a.m.

4. 10:00 AM - The Highly Effective EMI 4. 10:00 AM - The How and Why of Biased 4. 10:00 AM - Peridynamics for Predicting Shielding Materials for Magnetic and Humidity Tests with Copper Wire Thermal Expansion Coefficient of Graphene Electric Wave Over the Wide Range of Amar Mavinkurve, Rene Rongen, Michiel Erdogan Madenci, Atila Barut, Mehmet Dorduncu – Frequency in Near Field VanSoestbergen, Orla O’ Halloran, Mark Luke The University of Arizona Yoon-Hyun Kim, Seung Jae Lee, Kyu Jae Lee, Kisu Joo, Farrugia, Leon Goumans, Erik Van Olst – NXP Jung Woo Hwang, Se Young Jeong – Ntrium, Inc.; Semiconductors Hyun Ho Park – University of Suwon

5. 10:25 AM - Low-Loss NCF Material for 5. 10:25 AM - In-Situ Photoelastic 5. 10:25 AM - Machine Learning Approach High-Frequency Device Measurement of Temperature Dependent to Improve Accuracy of Warpage Kazutaka Honda, Keiko Ueno, Nozomi Matsubara, Stresses in Copper Through-Glass Via (TGV) Simulations in Ultra-Thin Packages Tsuyoshi Ogawa, Toshihisa Nonaka – Hitachi Substrate Cheryl Selvanayagam and Nagarajan Raghavan – Chemical Company, Ltd. Chukwudi Okoro, William Furnas, Shrisudersan Singapore University of Technology and Design Jayaraman, Scott Pollard – Corning, Inc.

6. 10:50 AM - In-Situ Redox Nanowelding 6. 10:50 AM - Mechanical Properties and 6. 10:50 AM - Study on Warpage of Fan-Out of Copper Nanowires with Surfacial Oxide Microstructural Fatigue Damage Evolution Panel Level Packaging (FO-PLP) Using Gen-3 Layer as Solder for Flexible Transparent in Cyclically Loaded Lead-Free Solder Joints Panel Electromagnetic Interference Shielding Sinan Su, Md Mahmudur Chowdhury, Mohd Aminul Faxing Che, Kaz Yamamoto, Srinivasa Rao Xianwen Liang, Jianwen Zhou, Gang Li, Tao Zhao, Hoque, Sa’d Hamasha, Jeffrey C. Suhling, John Evans, Vempati, Nagendra Sekhar Vasarla – Institute of Pengli Zhu, Rong Sun – Shenzhen Institutes of Pradeep Lall – Auburn University Microelectronics Advanced Technology; Ching-Ping Wong – Georgia Institute of Technology

7. 11:15 AM - High Conductive 7. 11:15 AM - Improving Reliability of Si 7. 11:15 AM - Mechanical Properties of Compartment EMI Shielding Material with Interconnect Fabric (Si-IF) Intermetallic Compounds at Elevated Jet-Dispensing Technology Niloofar Shakoorzadeh, Shiva Chandra Jangam, Pranav Temperature by Nanoindentation Xuan Hong, Qizhuo Zhuo, Xinpei Cao, Dan Maslyk, Ambhore, Han Chien, Amir Hannah, Subramanian Fan Yang, Sheng Liu, Zhiwen Chen – Wuhan Juliet Sanchez – Henkel Corporation Iyer – University of California University; Zhaoxia Zhou, Canyu Liu, Stuart Roberson, Changqing Liu – Loughborough University; Li Liu – Wuhan University of Technology

21 Program Sessions: Thursday, May 30, 1:30-5:10 p.m.

Session 19: MEMS, Sensors, & IoT Session 20: Fan-Out and Heterogeneous Session 21: 5G, mm-Wave and Antenna-in- Integration Package

Committee: Packaging Technologies Committee: Interconnections Committee: High-Speed, Wireless & Components

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Joseph W. Soucy Jean-Charles Souriau Maciej Wojnowski Draper, Inc. CEA-LETI Infineon Technologies Email: [email protected] Email: [email protected] Email: [email protected]

Ning Ge William Chen Xiaoxiong Gu Consultant Advanced Semiconductor Engineering, Inc. IBM Corporation Email: [email protected] Email: [email protected] Email: [email protected]

1. 1:30 PM - A MEMS-Microphone in a Fan- 1. 1:30 PM - Feasibility Study of Fan-Out 1. 1:30 PM - Vivaldi Antenna Array Out Wafer Level Package Wafer-Level Packaging for Heterogeneous Completely Fabricated Using Additive Horst Theuss, Christian Geissler, Franz-Xaver Integration Manufacturing Muehlbauer, Claus Von Waechter, Thomas Kilger, John Lau, Ming Li, Margie Li – ASM Pacific Technology; Vincens Gjokaj, Cameron Crump, John Albrecht, John Juergen Wagner, Thomas Fischer, Ulf Bartl, Stephan Tong Chen, Iris Xu – JCAP Papapolymerou, Premjeet Chahal - Michigan State Helbig, Alfred Sigl – Infineon Technologies University

2. 1:55 PM - Fan-Out Wafer Level 2. 1:55 PM - Experiment of 22FDX® Chip 2. 1:55 PM - Novel Multicore PCB and Packaging - A Platform for Advanced Sensor Board Interaction (CBI) in Wafer Level Substrate Solutions for Ultra Broadband Packaging Packaging Fan-Out (WLPFO) Dual Polarized Antennas for 5G Millimeter Tanja Braun, Karl-Friedrich Becker, Ole Holck, Jae Cho, Jens Paul, Simone Capecchi, Wave Covering 28 GHz & 39 GHz Range Ruben Kahle, Pascal Graap, Markus Wohrmann, Frank Kuechenmeister, Ta-Chien Cheng – Trang Thai, Sidharth Dalmia, Josef Hagn, Pouya Rolf Aschenbrenner – Fraunhofer IZM; Steve Voges, GLOBALFOUNDRIES Talebbeydokhti, Yossi Tsfati – Intel Corporation Marc Dreissigacker, Klaus-Dieter Lang – Technical University Berlin

3. 2:20 PM - 3D-MID Evaluation and 3. 2:20 PM - FOWLP Design for Digital and 3. 2:20 PM - 3D Glass Package-Integrated, Validation for Space Applications RF Circuits High-Performance Power Dividing Networks Etienne Hirt, Klaus Ruzicka – Art of Technology AG; Teck Lim – Institute of Microelectronics for 5G Broadband Antennas Benedikt Wigger, Maximilian Barth, Rafet Saleh, Florian Muhammad Ali, Atom Watanabe, TongHong Lin, Janek – Hahn-Schickard; Ernst Muller – Institute for Fuhan Liu, Manos Tentzeris, Rao Tummala – Georgia Microintegration, University of Stuttgart Institute of Technology; Markondeya Raj Pulugurtha – Florida International University

Refreshment Break: 2:45-3:30 p.m.

4. 3:30 PM - High-Temperature Pressure 4. 3:30 PM - Next-Generation of 2 to 7 4. 3:30 PM - Advanced Wafer Level Package Sensor Package and Characterization of Micron Ultra-Small Microvias for 2.5D Solutions for 60GHz WiGig (802.11ad) Thermal Stress in the Sensor and Operation Panel Redistribution Layer by Using Laser Telecom Infrastructure up to 500 °C and Photolithography Technologies Dapeng Wu, Robin Dahlbäck, Erik Öjefors, Mats Nilavazhagan Subbiah, Qingming Feng, Kevin Ali Fuhan Liu, Chandrasekharan Nair, Atom Watanabe, Carlsson – Sivers IMA AB Beltran Ramirez, Juergen Wilde – University of Bart H. DeProspo, Rao R. Tummala – Georgia Freiburg, IMTEK; Gudrun Bruckner – CTR AG Institute of Technology; Atsushi Kubo – Tokyo Ohka Kogyo Co., Ltd.

5. 3:55 PM - Development of 3D WLCSP 5. 3:55 PM - Multiple RDL on Fan-Out 5. 3:55 PM - Antenna and Module Design With Black Shielding for Optical Finger Print Packages Considerations for mm-Scale IoT Devices at Sensor for the Application of Full Screen Yi Hang Lin, T.M. Lai, P.N. Kavle, C.H. Lin, T.J. Fang, mm-Wave 5G Frequencies Smart Phone F.C. Hsu, S.M. Chen, M.C. Yew, Shin Puu Jeng – Arun Paidimarri, Duixian Liu, Christian Baks, Daquan Yu, Yichao Zou, Xirui Xu, Aihua Shi, Zhiyi Taiwan Semiconductor Manufacturing Company, Ltd. Bodhisatwa Sadhu, Alberto Valdes-Garcia – IBM Xiao – Huantian Technology (Kunshan) Electronics Corporation Co., Ltd.

6. 4:20 PM - Micro Fountain-Like 6. 4:20 PM - Effects of Dielectric Curing 6. 4:20 PM - Advanced Thin-Profile Fan- Resonators Conditions on the Interfacial Adhesion of Cu Out with Beamforming Verification for 5G Jianfeng Zhang, Jintang Shang, Bin Luo, Zhaoxi Su – RDL for Fan-Out Wafer Level Packaging Wideband Antenna Southeast University Gahui Kim, Kirak Son, Dogeun Kim, Young-Bae ShengChi Hsieh, Lucus Chu, ChengYu Ho, ChenChao Park – Andong National University; Seok-Hyun Lee – Wang – Advanced Semiconductor Engineering, Inc. Samsung Electronics Company, Ltd.

7. 4:45 PM - Novel Additively Manufactured 7. 4:45 PM - Al-Al Direct Bonding With Sub- 7. 4:45 PM - Integrated Compact Planar Packaging Approaches for 5G/mm-Wave µm Alignment Accuracy for Millimeter Wave Inverted-F Antenna (PIFA) With a Shorting Wireless Modules SiGe BiCMOS Wafer Level Packaging and Via Wall for Millimeter-Wave Wireless Chip- Tong-Hong Lin, Aline Eid, Jimmy Hester, Bijan Tehrani, Heterogeneous Integration to-Chip (C2C) Communications in 3D-SiP Manos Tentzeris – Georgia Institute of Technology; Jo Matthias Wietstruck, Sebastian Schulze, Selin Tolunay Wipf, Seahee Hwangbo, Renuka Bowrothu, Haein Kim – Bito – Texas Instruments, Inc. Christian Wipf, Mehmet Kaynak – Innovations for High University of Florida Performance Microelectronics; Bernhard Rebhan, Peter Kerepesi, Helmut Kurz, Gerald Silberer, Josef Meiler – EV Group, Inc. 22 Program Sessions: Thursday, May 30, 1:30-5:10 p.m.

Session 22: Advanced Substrates and Session 23: High Bandwidth 3D & Session 24: Advancements in Solder Joint Interconnect Technology Photonics Integration Characterization and Reliability Evaluation

Committee: Materials & Processing Committee: Interconnection joint with Photonics Committee: Applied Reliability

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Mikel Miller Dingyou Zhang Scott Savage EMD Performance Materials Broadcom, Inc. Medtronic Microelectronics Center [email protected] Email: [email protected] Email: [email protected]

Kimberly Yess Takaaki Ishigure Pei-Haw Tsao Brewer Science, Inc. Keio University Taiwan Semiconductor Manufacturing Company, Ltd. [email protected] Email: [email protected] Email: [email protected]

1. 1:30 PM - Temporary SiC-SiC Wafer 1. 1:30 PM - A Highly Reliable 1.4um Pitch 1. 1:30 PM - Significant Elongation Bonding Compatible with High Temperature Via-Last TSV Module for Wafer-to-Wafer Improvement of Eutectic Sn58Bi Alloy Annealing Hybrid Bonded 3D-SOC Systems Induced by In and Zn Double Addition Fengwen Mu, Tadatomo Suga, – University of Tokyo; Stefaan Van Huylenbroeck, Joeri De Vos, Zaid Shiqi Zhou, Yu-An Shen, Hiroshi Nishikawa – Osaka Miyuki Uomoto, Takehito Shimatsu – Tohoku El-Mekki, Geraldine Jamieson, Nina Tutunjyan, Karthik University; Tiffani Uresti, Vasanth Shunmugasamy, Bilal University Muga, Michele Stucchi, Andy Miller, Gerald Beyer, Eric Mansoor – Texas A&M University at Qatar Beyne – IMEC

2. 1:55 PM - Ultra-Thin Glass to Ultrathin 2. 1:55 PM - Nanoscale Topography 2. 1:55 PM - Microstructural Evolution in Glass Bonding Using Laser Sealing Approach Characterization for Direct Bond SAC+X Solders Subjected to Aging Messaoud Bedjaoui, Jean Brun, Johnny Amiran – CEA- Interconnect Jing Wu, Jeffrey C. Suhling, Pradeep Lall – Auburn LETI Bongsub Lee, Pawel Mrozek, Gill Fountain, John University Posthill, Jeremy Theil, Rajesh Katkar, Laura Mirkarimi – Xperi Corporation

3. 2:20 PM - Development of Resins for 3. 2:20 PM - Fabrication and 3. 2:20 PM - Microstructure Signature Bumpless Interconnections and Wafer-On- Characterisation of Carbon-Based Evolution in Solder Joints, Solder Bumps, Wafer (WOW) Integration Interconnects for 3D ICs and Micro-Bumps Interconnection in A Naoko Araki, Shinji Maetani – Daicel Corporation; Andreas Nylander, Marlene Bonmann, Yifeng Fu, Large 2.5D FCBGA Package During Thermo- Young Suk Kim, Shoichi Kodama – DISCO Andrei Voroblev, Johan Liu – Chalmers University Mechanical Cycling Corporation; C. Hsiao, H. Chang, C. Lin – Industrial of Technology; Jie Zhao, Zhibin Zhang – Uppsala Tae-Kyu Lee, Richa Sharma, Greg Baty – Portland Technology Research Institute; Takayuki Ohba – University State University; Peng Su – Juniper Networks Tokyo Institute of Technology Refreshment Break: 2:45-3:30 p.m. 4. 3:30 PM - 3D Silicon Photonics Interposer 4. 3:30 PM - Development of Novel for Tb/s Optical Interconnects in Data 4. 3:30 PM - Long-Term Reliability of Photosensitive Dielectric Material for Centers with Double-Side Assembled Active Solder Joints in 3D Memory ICs Under Near- Reliable 2.1D Package Components and Integrated Optical and Application Conditions Yune Kumazawa, Seiji Shika, Shunsuke Katagiri, Takuya Electrical Through Silicon Via on SOI Omar Ahmed, Golareh Jalilvand, Hector Fernandez, Suzuki, Tsuyoshi Kida, Shu Yoshida – Mitsubishi Gas Bogdan Sirbu, Yann Eichhammer, Oppermann Hermann, Tolga Tekin – Tengfei Jiang, Jessica Dieguez – University of Central Chemical Company, Inc. Fraunhofer Institute for Reliability and Microintegration; Victor Sidorov, Florida; Peng Su – Juniper Networks; Tae-Kyu Lee – Jochen Kraft – AMS AG; Xin Yin, Johan Bauwelinck – Interuniversitair Micro-Electronica Centrum IMEC; Christian Neumeyr – VERTILAS Portland State University GmbH; Francisco Soares – Fraunhofer Heinrich-Hertz Institute

5. 3:55 PM - An Advanced Solder Resist with 5. 3:55 PM - Flip-Chip III-V-to-Silicon 5. 3:55 PM - Experimental Investigation Strong Adhesion and High Resolution for Photonics Interfaces for Optical Sensor of the Correlation Between a Load-Based High-Density Packaging Yves Martin, Jason S. Orcutt, Chi Xiong, Laurent Metric and Solder Joint Reliability of BGA Sawako Shimada, Kazuya Okada, Tomoya Kudo, Schares, Tymon Barwicz, Martin Glodde, Swetha Assemblies on System Level Chiho Ueta – Taiyo Ink Mfg. Co. Ltd.; Yuya Suzuki – Kamlapurkar, Eric J. Zhang, William M. J. Green – Fabian Schempp, Marc Dressler, Daniel Kraetschmer, Taiyo America, Inc. IBM Corporation; Victor Dolores-Calzadilla, Ariane Friederike Loerke – Robert Bosch GmbH; Juergen Sigmund, Martin Moehrle – Fraunhofer Heinrich-Hertz Wilde – University of Freiburg, IMTEK Institute

6. 4:20 PM - Solution Method of Warpage 6. 4:20 PM - Extremely Low-Profile Single 6. 4:20 PM - Fatigue Life Predictive Model Behavior for Ultra-Thin FC-CSP by Control Mode Fiber Array Coupler Suitable for Development for Decoupling Capacitors of EMC Properties Silicon Photonics Joseph Ross, Kamal Sikka, Bakul Parikh – IBM Chika Arayama, Takahiro Akashi, Yasunari Tomita, Mitsuharu Hirano, Akira Furuya, Hideki Machida, Corporation Naoki Kanagawa – Panasonic Corporation Koichi Koyama, Yasunori Murakami, Kazunori Tanaka – Sumitomo Electric Industries, Ltd.

7. 4:45 PM - Innovative Socketable and 7. 4:45 PM - Micro Lens Array Assembly for 7. 4:45 PM - A Study of Various Substrate Surface-Mountable BGA Interconnections Optical Organic Substrates Models and its Effect on Board-Level Solder Omkar Gupte, Kristie Teoh, Vanessa Smet, Rao Patrick Jacques, Richard Langlois – IBM Bromont; Koji Joint Reliability Tummala – Georgia Institute of Technology Masuda, Masao Tokunari, Hsiang Han Hsu – IBM Van Lai Pham, Huayan Wang, Jiefeng Xu, Vishnu Tokyo Research Lab; Paul Fortier – IBM Corporation Veeraraghavan, Seungbae Park – Binghamton University; Yuling Niu – Qualcomn Technologies, Inc.; Charandeep Singh – Corning, Inc.

23 Program Sessions: Friday, May 31, 8:00-11:40 a.m.

Session 25: Wafer Level Packaging Fan-In- Session 26: High-Speed Signaling for HPC Session 27: Advanced Biosensors and Fan-Out Structure and Materials and Memory Bioelectronics

Committee: Packaging Technologies Committee: High-Speed, Wireless & Components Committee: Emerging Technologies

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Albert Lan Rockwell Hsu Zhuo Li Applied Material, Inc. Cisco Systems, Inc. Fudan University Email: [email protected] [email protected] Email: [email protected]

Christophe Zinck Jaemin Shin Jimin Yao Advanced Semiconductor Engineering Inc. Qualcomm Technologies, Inc. Intel Corporation Email: [email protected] [email protected] Email: [email protected]

1. 8:00 AM - 3D Fan-Out Package 1. 8:00 AM - Hybrid Prepreg Conventional 1. 8:00 AM - Microfabricated Biodissolvable Technology with Photosensitive Through Build-Up Laminate for 112Gbit/s SerDes Probe for Electrical Neural Signal Recording Mold Interconnects Kwang Won Choi, Edmund Blackshear, Eric Tremble, Sajay Bhuvanendran, Nair Gourikutty, Ruiqi Lim – Kentaro Mori, Soichi Yamashita, Takafumi Fukuda, David Stone – GLOBALFOUNDRIES; Jean Audet – Institute of Microelectronics, A*STAR Masahiro Sekiguchi, Hirokazu Ezawa, Shuzo Akejima – IBM Corporation; Keiichi Hirabayashi – Shinko Electric Toshiba Electronic Devices and Storage Corporation Industries Co., Ltd.

2. 8:25 AM - Effects of the Materials 2. 8:25 AM - PI/SI Analysis and Design 2. 8:25 AM – Stretchable, Implantable Properties of Epoxy Molding Films (EMFs) on Approach for HPC Platform Applications Nanomembrane Biosensor for Wireless, Fan-Out Packages (FOPs) Characteristics Sungwook Moon, Chanmin Jo, Seungki Nam – Real-Time Monitoring of Hemodynamics SangMyung Shin, HanMin Lee, JunMo Kim, Tae-Ik Lee, Samsung Electronics Company, Ltd. Robert Herbert, Woon-Hong Yeo – Georgia Institute Taek-Soo Kim, Youjin Kyung, Chem Minsu Jeong, of Technology Chem Kwangjoo Lee, Chem Kyung-Wook Paik – Korea Advanced Institute of Science and Technology

3. 8:50 AM - Mechanism of Moldable 3. 8:50 AM - PoP LPDDR5 (6.4 Gbps) 3. 8:50 AM - A Wearable Passive pH Sensor Underfill (MUF) Process for RDL-1st Fan- NTODT and 1-Tap DFE for Signal Integrity for Health Monitoring Out Panel Level Packaging Enhancement Saikat Mondal, Saranraj Karuppuswami, Rachel Lin bu, Faxing Che, Vempati Srinivasa Rao, Xiaowu Sunil Gupta – Qualcomm Technologies, Inc. Steinhornst, Premjeet Chahal – Michigan State Zhang – Institute of Microelectronics University

Refreshment Break: 9:15-10:00 a.m. 4. 10:00 AM - OpenCAPI Memory Interface 4. 10:00 AM - Study of the Board Level Signal Integrity Study for High-Speed DDR5 4. 10:00 AM - Novel Packaging Structure Reliability Performance of a Large 0.3 mm Differential DIMM Channel With Standard and Processes for Micro-Size Thin Film Pitch Wafer Level Package Loss FR-4 Material and SNIA SFF-TA-1002 Batteries (TFB) to Enable Miniaturized Bernd Waidhas, Jan Proschwitz, Christoph Pietryga, Connector Healthcare Internet-of-Things (IoT) Devices Thomas Wagner, Beth Keser – Intel Corporation Biao Cai, Jose Hejase, Kyle Giesen, Junyan Tang, Brian Connolly, Bing Dang, Qianwen Chen, Leanna Pancoast, Yu Luo, Kyu Hyoun(Kh) Kim, Daniel Dreps – IBM Corporation; Zhineng Hongqing Zhang, John Knickerbocker – IBM Corporation; Fan, Rocky Huang, Luyun Yi, Qiaoli Chen, Yifan Huang, Stephen Andy Shih, Barry Cheng, Kai Liu, Mengnian Nio, Simon Smith – Amphenol ICC Nieh – Front Edge Technology, Inc.

5. 10:25 AM - Study of Board Level 5. 10:25 AM - Effectiveness of Equalization 5. 10:25 AM - Printed Temporary Transfer Reliability of eWLB (Embedded Wafer Level and Performance Potential in DDR5 Tattoos for Skin-Mounted Electronics BGA) for 0.35mm Ball Pitch Channels with RDIMM(s) Samuli Tuominen, Matti Mäntysalo – Tampere Seung Wook Yoon, Yeow Kheng Lim, Seng Guang Nanju Na, Thomas To – Xilinx, Inc. University Chow, Kang Hai Lee, NW Liu, Yenyao Chi, Benson Lin – STATS ChipPAC Pte. Ltd.

6. 10:50 AM - Board Level Reliability Study 6. 10:50 AM - Inductive Link for 3D Stacked 6. 10:50 AM - Thermoset Polymers for of Fan-Out Single Die Package With 350um Chip to Chip Communication Bioelectronic Interfaces: Engineering of Bump Pitch Xiao Sun, Nicolas Pantano, Soon-Wook Kim, Geert Thermomechanical Properties Chieh Lung Lai, Gu Yan Lin, Tz Yuan Chao, Chun Van der Plas, Eric Beyne – IMEC Alexandra Joshi-Imre, Walter E. Voit, Joseph J. Hung Lu, Yih Sin Chen, Feng Lung Chien – Siliconware Pancrazio, Melanie Ecker – The University of Texas Precision Industries Co., Ltd. at Dallas

7. 11:15 AM - The Analysis for Bump 7. 11:15 AM - System Co-Design of a 600V 7. 11:15 AM - Direct Heterogeneous Resistance Improvement by Optimizing the GaN FET Power Stage With Integrated Bonding of SiC to Si, SiO2, and Glass for Sputter Condition Driver in a QFN System-in-Package (QFN- High-Performance Power Electronics and Ming-Sin Su, C.N. Wang, T.L. Yang, W.C. Liu, J.M. SiP) Bio-MEMS Chiu, Y. F. Chen, Harry Ku, Kirin Wang, C.H. Su – Jie Chen, Yong Xie, Trombley Django, Rajen Murugan Jikai Xu, Chenxi Wang, Qiushi Kang, Shicheng Zhou, Taiwan Semiconductor Manufacturing Company, Ltd. – Texas Instruments, Inc Yanhong Tian – Harbin Institute of Technology

24 Program Sessions: Friday, May 31, 8:00-11:40 a.m.

Session 28: Embedded Substrates and Session 29: Electromigration and Innovative Session 30: Assembly and Process Modeling Integrated Technologies Reliability Test Methods

Committee: Assembly and Manufacturing Committee: Applied Reliability Committee: Thermal/Mechanical Simulation & Technology Characterization

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Christo Bojkov Keith Newman Suresh K. Sitaraman Qorvo, Inc. Advanced Micro Devices, Inc. Georgia Institute of Technology Email: [email protected] Email: [email protected] Email: [email protected]

John H. Lau Pilin Liu Kuo-Ning Chiang ASM Pacific Technology Intel Corporation National Tsinghua University Email: [email protected] Email: [email protected] Email: [email protected]

1. 8:00 AM - Development of Flexible 1. 8:00 AM - Effect of Intermetallic 1. 8:00 AM - Explicit FE Failure Prediction Hybrid Electronics Using Reflow Assembly Compound Growth on Electromigration of Interfaces and Interconnect in Potted with Stretchable Film Failure Mechanism in Low-Profile Solder Electronics Assemblies Subject to High-G Weifeng Liu, William Uy, Alex Chan, Dongkai Joints Acceleration Loads Shangguan – Flex, Ltd. ; Andy Behr, Takatoshi Abe, Madanipour Hossein, Yi-Ram Kim, Choong-Un Kim – Pradeep Lall, Kalyan Dornala – Auburn University; Tomohiro Fukao – Panasonic Corporation The University of Texas at Arlington; Ninad Shashane, John Deep – Air Force Research Laboratory; Ryan Dibyajat Mishra, T. Noguchi, M. Yoshino, Luu Nguyen Lowe – ARA – Texas Instruments, Inc.

2. 8:25 AM - Highly Compact RF Transceiver 2. 8:25 AM - Effect of Grain Orientation 2. 8:25 AM - Numerical Simulation on the Module using High Resistive Silicon and Microstructure Evolution on Formation Process of Metal Droplets by Interposer With Embedded Inductors and Electromigration in Flip-Chip Solder Joint Pneumatic Diaphragm Drop-On-Demand Heterogeneous Dies Integration Xing Fu, Ruohe Yao – South China University of Technology Gabriel Pares, Jean-Philippe Michel, Edouard Technology; Yunfei En, Bin Zhou, Si Chen, Yun Huang Kun Ma, Sheng Liu, Zhiwen Chen, Chunxi Wang, Li Deschaseaux, Pierre Ferris, Ayssar Serhan, Alexandre – CEPREI Liu – Wuhan University of Technology Giry – CEA-LETI

3. 8:50 AM - Process Induced Wafer 3. 8:50 AM - Highly (111)-Oriented 3. 8:50 AM - On the Curing-Induced Warpage Optimization for Multi-Chip Nanotwinned Cu for Redistribution Lines in Residual Stresses After Molding Processes: Integration on Wafer Level Molded Wafer 3D IC With High Electromigration Resistance Mold Shrinkage, Chemical Shrinkage or Chen-Yu Huang, Daniel Ng, Hung-Ho Lee, Vito Lin, I-Hsin Tseng, Chih-Han Tseng, Yu-Jin Li – National Both? Chang-Fu Lin, C. Key Chung – Siliconware Precision Chiao Tung University; Benson Lin, Chia-Cheng Chang Bongtae Han, Changsu Kim, Sukrut Phansalkar – The Industries Co., Ltd – MediaTek, Inc. University of Maryland

Refreshment Break: 9:15-10:00 a.m.

4. 10:00 AM - Improvement Structure for 4. 10:00 AM - Non-Destructive Failure 4. 10:00 AM - Realistic Solder Joint Package Substrate with Embedded Thin Film Analysis of Various Chip to Package Geometry Integration with Finite Element Capacitor Interaction Anomalies in FCBGA Packages Analysis for Reliability Evaluation of Printed Tomoyuki Akahoshi, Daisuke Mizutani – Fujitsu Subjected to Temp Cycle Reliability Testing Circuit Board Assembly Laboratories, Ltd.; Kei Fukui, Shogo Yamawaki, Vishnu V. B. Reddy, I. Charles Ume – Georgia Institute Chun Sean Lau, Ning Ye, Hem Takiar – Western Hidehiko Fujisaki – Fujitsu Interconnect Technologies, of Technology; Jaimal Williamson, Luu Nguyen –Texas Digital Corporation Ltd.; Manabu Watanabe, Masateru Koide – Fujitsu Instruments, Inc. Advanced Technologies, Ltd.

5. 10:25 AM - 3D Packaging with Embedded 5. 10:25 AM - Assessment of Accelerometer 5. 10:25 AM - Multi-Physics Modelling and High-Power-Density Passives for Integrated Versus LASER for Board Level Vibration Experimental Investigation – An Original Voltage Regulators Measurements Approach for Laser-Dicing/Grooving Process Teng Sun, Robert Spurney, Atom Watanabe, Varun Thukral, Maëlle Cahu, Jeroen Zaal, Jeroen Optimization Himani Sharma, Rao Tummala – Georgia Institute Jalink, Romuald Roucou, Rene Rongen – NXP Jeff Moussodji, Dominique Drouin – University of of Technology; Pulugurtha Markondeya – Florida Semiconductors Sherbrooke; Oswaldo Chacon, Francis Santerre – IBM International University; Furukawa Yoshihiro - Nitto Corporation Denko Corporation

6. 10:50 AM - A Novel Panel Level Double 6. 10:50 AM - Effect of Process Parameters 6. 10:50 AM - Thermal Characteristics Side-Embedded Package for Small Size on the Long-Run Print Consistency and of Vertically Integrated GaN/SiC-on-Si Power Devices Material Properties of Additively Printed Assemblies: A Comparative Study Kunpeng Ding, Mian Huang – Shenzhen Siptory Electronics Kimmo Rasilainen, Christian Fager – Chalmers Technologies Co., Ltd; Zhichao Wu, Jian Cai – Pradeep Lall, Amrit Abrol, Nakul Kothari, Jeff Suhling – University of Technology; Per Ingelhag, Peter Melin – Tsinghua University; Bowei Zhang – Wuxi Sky Chip Auburn University Ericsson AB; Torbjörn M. J. Nilsson – Saab AB; Mattias Interconnection Technology Co., Ltd. Thorsell – Chalmers University of Technology

7. 11:15 AM - EMI Shielding on Electronic 7. 11:15 AM A Viscoplastic-Based Fatigue 7. 11:15 AM - Comprehensive Investigation Packages Realized by Electrolytic Plating Reliability Model for the Polyimide on Warpage Management of FOPLP with Mustafa Öezköek, Eckart Klusmann, Sven Lamprecht Dielectric Thin Film Multi Embedded Ring Designs – Atotech Germany GmbH; Katharina Krefft, – Yu-Chen Chang, Tz-Cheng Chiu – National Chang-Chun Lee, Yan-Yu Liou, Pei-Chen Huang Qualcomm Technologies, Inc. Cheng Kung University; Yu-Ting Yang, Yi-Hsiu – National Tsing Hua University; Fussen Hsu, Puru Tseng, Xi-Hong Chen – Advanced Semiconductor Bruce Lin, Cheng-Ta Ko, Yu-Hua Chen – Unimicron Engineering, Inc. Technology Corporation

25 Program Sessions: Friday, May 31, 1:30-5:10 p.m.

Session 31: Automotive and Power Session 32: Power and Panel Assembly Session 33: Thermal-Mechanical Simulation Packaging for Fan-Out, Flip Chip, and WLCSP

Committee: Packaging Technologies Committee: Assembly and Manufacturing Committee: Thermal/Mechanical Simulation & Technology Characterization

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Young-Gon Kim Habib Hichri Ning Ye Integrated Device Technology, Inc. SUSS MicroTec Photonic Systems, Inc. Western Digital Email: [email protected] Email: [email protected] Email: [email protected]

Kuo-Chung Yee Shichun Qu Wei Wang Taiwan Semiconductor Manufacturing Company Ltd. Renesas Electronics America Qualcomm Technologies, Inc. Email: [email protected] Email: [email protected] Email: [email protected]

1. 1:30 PM - Development of High Power 1. 1:30 PM - An RDL-First Fan-Out 1. 1:30 PM - A Sequential Finite Volume and High Junction Temperature SiC Based Panel Level Package for Heterogeneous Method / Finite Element Analysis of a Power Power Packages Integration Applications Electronic Semiconductor Chip Gongyue Tang, Ching Wai Leong, Teck Guan Yu-Min Lin, Sheng-Tsai Wu, Ang-Ying Lin, Shin-Yi Huang, Mario Gschwandl, Peter Fuchs – Polymer Competence Center Leoben Lim, Zhaohui Chen, Yong Liang Ye, Ravinder Pal Tao-Chih Chang – Industrial Technology Research GmbH; Thomas Antretter – Montanuniversitaet Leoben; Martin Pfost Singh, Lin Bu, Boon Long Lau, Tai Chong Chai, Institute; Chun-Min Wang, Puru Bruce Lin, Cheng-Ta Ko – Technical University of Dortmund; Tao Qi, Thomas Krivec – AT & Kazunori Yamamoto, Xiaowu Zhang – Institute of - Unimicron; Chia-Hsin Lee – Brewer Science, Inc.; Kuan- S Austria Technologie & Systemtechnik Aktiengesellschaft; Angelika Microelectronics Neng Chen – National Chiao Tung University Schingale – Continental Automotive GmbH

2. 1:55 PM - Development for Highly Heat 2. 1:55 PM - High Yield Precision Transfer 2. 1:55 PM - Failure Life Prediction of Resistant Joint Materials on Exhaust Gas and Assembly of GaN μLEDs Using Laser Wafer Level Packaging Using DoS with AI Sensor; SiC-FET-type NOx Sensor and SAW- Assisted Micro Transfer Printing Technology Type PM Sensor Goutham Ezhilarasu, Amir Hanna, Subramanian Iyer P.H. Chou, X.Y. Hsiao, K. N. Chiang – National Tsing Chiko Yorita, Nobuyuki Ushifusa, Yoshitaka Sasago, – University of California, Los Angeles; Ajit Paranjpe – Hua University Atsushi Isobe, Takahiro Odaka, Shigenobu Komatsu – Veeco Instruments, Inc. Hitachi Chemical Company, Ltd.; Kenji Okishiro, Yuta Sugiyama – Hitachi Metals, Ltd.

3. 2:20 PM - Innovative Flip-Chip Package 3. 2:20 PM – High-Density Flexible Substrate 3. 2:20 PM - Thermal Cycling Simulation Solutions for Automotive Applications Technology with Thin-Chip Embedding and and Sensitivity Analysis of Wafer Level Chip Tom Tang, David Ho, Mark Liao, Jensen Tsai, Yu-Po Partial Carrier Release Option for IoT and Scale Package with Integration of Metal- Wang, Boxiang Fang – Siliconware Precision Industries Sensor Applications Insulator-Metal Capacitors Co., Ltd. Kai Zoschke, Piotr Mackowiak, Ha-Duong Ngo, Yong Liu, Bill Chen – ON SEMICONDUCTOR; Yi Christian Tschoban, Carola Fritsche, Kevin Kröhnert, Zhou, Suresh K. Sitaraman – Georgia Institute of Thorsten Fischer, Ivan Ndip – Fraunhofer IZM; Klaus- Technology Dieter Lang – Technical University Berlin Refreshment Break: 2:45-3:30 p.m.

4. 3:30 PM - Reliability of Laminated Bond 4. 3:30 PM - Advance Embedded Packaging 4. 3:30 PM - Effect of Time-Dependent Structure Using (Cu,Ni)/Sn TLP Bonding for Power Discrete Device Bulk Modulus on Reliability Assessment of With Al Interlayer for High-Temperature Jiaren Huo, Guanqiang Song, Juntao Wang – Wuxi Sky Automotive Electronic Control Unit Power Electronics Packaging Chip Interconnection Technology Co., Ltd. Hyun Seop Lee, Bongtae Han – University of Maryland Yanghe Liu, Shailesh Joshi, Ercan M. Dede – Toyota Motor Engineering & Manufacturing North America Chemical Company, Inc.

5. 3:55 PM - Silver Sintering on Organic 5. 3:55 PM - Large Panel Size Bonder with 5. 3:55 PM - Thermal and Mechanical Substrates for the Embedding of Power High Performance and High Accuracy Simulations for Fan-out Wafer-Level Semiconductor Devices Hubert Selhofer, Hugo Pristauz, Andreas Mayr – Besi Packaging Technology: Introduction of a Alexander Schiffmacher, Lorenz Litzenberger, Juergen Austria GmbH “Solder Heatsink Wilde – University of Freiburg, IMTEK; Till Huesgen – Loic Marnat, Mathilde Cartier, Gabriel Pares, Hochschule Kempten, University of Applied Science Dominique Noguet – CEA-LETI

6. 4:20 PM – High-Temperature Resistant 6. 4:20 PM - Advances in High-Speed Plating 6. 4:20 PM - Wafer Level Warpage Packaging Technology for SiC Power Module for Vertical Glass Panel Fine-Line Plating Modelling and Validation for FOWLP by using Ni Micro-Plating Bonding Claudia Landstorfer, Herbert Ötzlinger, Christian Considering Effects of Viscoelastic Material Kohei Tatsumi, Isamu Morisako, Keiko Wada, Minoru Fukumori, Tomonori Iizuka – Waseda University; Nobuaki Sato, Koji Shimizu, Dunkel, Tetsuya Onishi, Raoul Schroeder – Semsysco Properties under Process Loadings Kazutoshi Ueda – Mitsui High-Tec Inc.; Masayuki Hikita – Kyushu Zhaohui Chen, Xiaowu Zhang – A*STAR Institute of Institute of Technology; Rikiya Kamimura – Kitakyushu Foundation for Microelectronics the Advancement of Industry Science and Technology; Naoki Kawanabe – WALTS Co., LTD; Kazuhiko Sugiura, Kazuhiro Tsuruta – Denso Corporation; Keiji Toda – Toyota Motor Corporation

7. 4:45 PM - Pb-Free, High Thermal and 7. 4:45 PM - Study of the Properties of AlN 7. 4:45 PM - Ultra-thin Package Board Electrical Performance Driven Die Attach PMUT used as a Wireless Power Receiver Level Drop Impact Modeling and Validation Material Development for Power Package Dan Gong, Shenglin Ma, Han Cai, Xinxin Hu – Xiamen Shu-Shen Yeh, Po-Yao Lin, Ming-Chih Yew, Wen-Yi Byong Jin Kim, DongSu Ryu, Hyeong Il Jeon, Weng University; Yunheng Sun, Yihsiang Chiu, Huan Liu, Lin, K. C. Lee, C. C. Yang, J. H. Wang, P. C. Lai, Chia- Tuck Chim, JinYoung Khim, Muhammad Hadhari Yufeng Jin – Peking University Kuei Hsu, Shin-Puu Jeng – Taiwan Semiconductor Hazellah – Amkor Technology, Inc. Manufacturing Company

26 Program Sessions: Friday, May 31, 1:30-5:10 p.m.

Session 34: Emerging Materials and Session 35: New Interconnects for Package Session 36: RF & Power Components and Processing Scaling Modules

Committee: Materials & Processing joint with Committee: Interconnections Committee: High-Speed, Wireless & Components Applied Reliability

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Ziyin Lin David Danovitch Yong-Kyu Yoon Intel Corporation University of Sherbrooke University of Florida Email: [email protected] Email: [email protected] Email: [email protected]

Dwayne Shirley Katsuyuki Sakuma Craig Gaw Inphi IBM Corporation NXP Semiconductor Email: [email protected] Email: [email protected] Email: [email protected]

1. 1:30 PM - Flexible Graphene-Glass Fiber 1. 1:30 PM - Development of 2.3D High 1. 1:30 PM - Multilayer Trench Decoupling Composite Film with Ultra-High Thermal Density Organic Package Using Low Capacitor Using Stacked Layers of BST and Conductivity and Mechanical Strength as Temperature Bonding Process with Sn-Bi LNO Highly Efficient Thermal Interface Materials Solder Todd Schumann, Sheng-Po Fang, Yong-Kyu Yoon Xiaoliang Zeng, Linlin Ren, Rong Sun – Shenzhen Shota Miki, Hiroshi Taneda, Naoki Kobayashi, Kiyoshi – University of Florida; Jongmin Yook, Dongsu Kim – Institutes of Advanced Technology; Jianbin Xu – The Oi, Koji Nagai, Toshinori Koyama – Shinko Electric Korea Electronics Technology Institute Chinese University of ; Ching-Ping Wong – Industries Co., Ltd. Georgia Institute of Technology

2. 1:55 PM - Highly Thermal Conductive 2. 1:55 PM - PowerTherm Attachment 2. 1:55 PM - System Co-Design of a High- and Electrically Insulated Graphene Based Process for Power Delivery and Heat Current (40A) Synchronous Step-Down Thermal Interface Material with Long-Term Extraction in the Silicon-Interconnect Fabric Converter in an Innovative Multi-Chip Reliability Pranav Ambhore, Boris Vaisband, Umesha Mogera, Module (MCM) in LGFN-Type Packaging Nan Wang, Lilei Ye – SHT Smart High Tech AB; Ujash Shah, Timothy Fisher, Mark Goorsky, Technology Shujing Chen – Shanghai University; Johan Liu – Subramaniam Iyer – University of California Los Todd Harrison, Jie Chen, Rajen Murugan – Texas Chalmers University of Technology Angeles Instruments, Inc.

3. 2:20 PM - Design of Mixed Spherical 3. 2:20 PM - Interconnect Scheme for 3. 2:20 PM - Integrating Solid-State and Platelet h-BN Particles Filled Polymer- Die-to-Die and Die-to-Wafer Level Protection With a RF-MEMS Switch for Based Thermal Interface Material for Heterogeneous Integration for High- Achieving ESD Robustness Power Electronics with Enhanced Thermal Performance Computing Srivatsan Parthasarathy, Padraig Fitzgerald, Javier Conductivity by Finite Element Modeling and Rabindra Das, Vladimir Bolkhovsky, Christopher Salcedo, Ray Goggin, Jean-Jacques Hajjar – Analog Experimental Characterization Galbraith, Daniel Oates, Scott Zarr, Jason Plant, Devices, Inc. Han Jiang, Han Zhou, Stuart Robertson, Zhaoxia Zhou, Changqing Terence Weir, Leonard Johnson, Eric Dauler – MIT Liu – Loughborough University Lincoln Laboratory Refreshment Break: 2:45-3:30 p.m.

4. 3:30 PM - Wafer-Level Integration of 4. 3:30 PM - Ultra-Wide Micro Bumps 4. 3:30 PM - A “Zero Height” Small- Thin Silicon Bare Dies within Flexible Label Interconnection Matrix for High-Energy Size Low-Cost RF Interconnect Substrate Jean-Charles Souriau Ahmad Itawi, Laëtitia Castagné Particle Detection: Process and Assembly Technology for RF Front Ends For M.2 – CEA-LETI Jean Charbonnier, Myriam Assous, Thierry Mourier, Modules and Sip Celine Ribière, Pierre Tissier, Remi Coquand, Mehmet Sidharth Dalmia, Kirthika Nahalingam, Swathi Bicer, Gabriel Pares – CEA-LETI Vijayakumar, Pouya Talebbeydokhti – Intel Corporation

5. 3:55 PM - Laser Sintering of Aerosol Jet 5. 3:55 PM - Growth Behavior and 5. 3:55 PM - Open and Closed Loop Printed Conductive Interconnects on Paper Orientation Evolution of Cu6Sn5 Grains Inductors for High Efficiency System on Substrates During the Formation of Full IMC Micro Package Integrated Voltage Regulators Mohammed Alhendi, Darshana Weerawarne, Jack Interconnects Claudio Alvarez, Mohamed Bellaredj, Madhavan Lombardi, Mark Poliks – Binghamton University; Azar Ning Zhao, Shi Chen, Yunpeng Wang, Haitao Ma – Swaminathan – Georgia Institute of Technology Alizadeh – General Electric Dalian University of Technology; C.M.L. Wu – City University of Hong Kong

6. 4:20 PM - In-Situ Investigation of 6. 4:20 PM - Development of a No Reflow 6. 4:20 PM - RF Inductors Integrated in Organic Additive Interactions in Copper Cu Pillar Bump to Improve Chip/Package Organic Packaging Electroplating Solutions with Surface Interactions (CPI) Process and Reliability Denis Mercier, Jean-Philippe Michel, Christine Enhanced Raman Spectroscopy (SERS) Performance Raynaud, Christophe Billard – CEA-LETI Nithin Nedumthakady, Bartlet DeProspo, Himani Sharma, Jiunn Jie Wang, Yen Neng Wang, Feng Lung Chien, Sajanlal Panikkanvalappil, Rao Tummala – Georgia Institute Rick Lee, Kuei Hsiao Kuo – Siliconware Precision of Technology; Nasrin Hooshmand – Georg; Rahul Industries Co., Ltd. Manepalli, Sashi Kandanur – Intel Corporation

7. 4:45 PM - C4 Compatible Ultra-Thick Cu 7. 4:45 PM - A Novel Interconnection 7. 4:45 PM - Optimal Package Capacitor On-Chip Magnetic Inductor Architecture Technology Using Ultra-Thin Under Barrier Hook Up Strategies for Power Delivery Integrated with Advanced Polymer/Cu Metal for Multiple Chip-on-Chip Stacking Network Planarization Process Structure Abinash Roy, Aniket Patil – Qualcomm Technologies, Chien-Hsien Kuo, Rolance Yang, Chien-Chih Kuo, Hon-Lin Satoru Wakiyama, Takuya Nakamura, Kan Shimizu, Masataka Inc. Huang, Harry Ku, Kirin Wang, K.Y. Wu, J.Y. Wu, Y.N. Chen, Maehara, Toshihiko Hayashi, Kentaro Akiyama, Junichiro K.S. Yuan, C.B. Jan, G.C. Huang, T.C. Chang, C.C. Hsu, Fujimagari, Tomohiro Ohkubo, Atsushi Fujiwara, Hayato C.L. Chang, K.C. Liu, Alex Kalnitsky, Marvin Liao – Taiwan Iwamoto – Sony Semiconductor Solutions Corporation Semiconductor Manufacturing Company Ltd. 27 Interactive Presentations: Wednesday, May 29, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m.

Wednesday, May 29, 2019 Fully-Filled, Highly-Reliable Fine-Pitch Low-Temperature Cu-Cu Bonding using Session 37: Interactive Presentations 1 Interposers with TSV Aspect Ratio >10 for Nano-Cu Paste Sintering in Pt-Catalyzed Time: 9:00 AM – 11:00 AM Future 3D-LSI/IC Packaging Formic Acid Vapor M. Mariappan, T. Fukushima, K. Mori, A. Nakamura, Fengwen Mu, Tadatomo Suga – The University Committee: Interactive Presentations Y. Lee, M. Motoyoshi, J. C. Bea, M. Koyanagi – Global of Tokyo; Hui Ren, Lei Liu – Tsinghua University, Yinghui Wang – Institute of Microelectronics, Chinese Session Co-Chairs: INTegration Initiative; S. Watariguchi – Meltex, Inc. Nam Pham Academy of Sciences; Guisheng Zou – Tsinghua IBM Corporation Wireless Transfer of Power and Data via a University Single Resonant Inductive Link Email: [email protected] Ultra-Thin QFN-Like 3D Package with 3D Yi-Chen Hsieh, Lih-Tyng Hwang, Shiang-Hwua Yu – Pavel Roy Paladhi Integrated Passive Devices National Sun Yat-Sen University IBM Corporation Ayad Ghannam – 3DiS Technologies; Niek van Email: [email protected] Adaptive Patterning of Optical and Haare, Birgit Brandstatter, Sebastiaan Kersjes- Besi; Julian Bravin – EV Group; Philippe Meunier – NXP Comprehensive Solution for Micro Bump Electrical Fan-Out for Photonic Chip Semiconductors Coplanarity Control Packaging Chun-Chen Liu, Max Chen, Ann Hsu, Rung-De Wang, Ahmed Elmogi, Andres Desmet, Jeroen Missinne, 3D Glass Panel Embedding (GPE) for Bin-En Ho, Chin-Yu Ku, Kirin Wang, Calvin Lu, K.C. Liu, Hannes Ramon, Joris Lambrecht Peter De Heyn, Superior Bandwidth, Power-Efficiency and De-Dui Liao – Taiwan Semiconductor Manufacturing Marianna Pantouvaki, Joris Van Campenhout, Geer Cost than Current Approaches Co., Ltd. Van Steenberge – Ghent University Siddharth Ravichandran, Fuhan Liu, Vanessa Smet, Mohanalingam Kathaperumal, Rao Tummala – Georgia Structural Enhancement for a CMOS-MEMS Low Surface Reflectance at Near Infrared Institute of Technology; Shuhei Yamada – Murata Microphone Under Thermal Loading by Wavelength Thermoplastic Optical Lens Manufacturing Co., Ltd. Taguchi Method Without AR Coating Chun-Lin Lu, Meng-Kao Yeh – National Tsing Hua Polylithic Integration of Heterogeneous Dice Sho Yakabe, Takuro Watanabe, Takayuki Shimazu Paul Jo, Ting Zheng, Muhannad Bakir – Georgia University – Sumitomo Electric Industries, Ltd.; Ryohei Hokari, Institute of Technology A Methodology to Correct In-Fixture Kazuma Kurihara – National Institute of Advanced Highly Energy Efficient Low Leakage Current Measurement of Impedance by a Machine Industrial Science and Technology RF Tunable Capacitors using Silver Doped Learning Model Characterization of Aerosol Printed Copper Barium Strontium Titanate Bo-Siang Fang, Cha-Chu Lai, Ying-Wei Lu, Kuan-Ta Todd Schumann, Kyoung-Tae Kim, Sheng-Po Fang Chen, Don-Son Jiang – Siliconware Precision Industries and Silver Nanoparticle Inks for Millimeter- Yong-Kyu Yoon – University of Florida Co., Ltd. Wave Applications Cameron Crump, Christopher Oakley, John Albrecht, High-Temperature Aging Effects in SAC and Material and Structure Design Optimization John Papapolymerou, Premjeet Chahal – Michigan SAC+X Lead Free Solders for Panel-Level Fan-Out Packaging State University; Kyle Byers – Honeywell International, Mohmmad Alam, KM Rafidh Hassan, Jeffrey C. Suhling, Dao-Long Chen – Advanced Semiconductor Pradeep Lall – Auburn University Engineering, Inc. Inc. A High Entropy Alloy as Very Low Melting Characterization of Fine-Pitch Hybrid Wednesday, May 29, 2019 Point Solder for Advanced Electronic Bonding Pads Using Electrical Misalignment Session 38: Interactive Presentations 2 Packaging Test Vehicle Time: 2:00 PM – 4:00 PM Li Pu, Xiuchen Zhao, Zhuangzhuang Hou - Beijing Imed Jani, Didier Lattard, Pascal Vivet, Edith Beigné, Institute of Technology; Quanfeng He, Yong Yang Lucile Arnaud – CEA-LETI; Alexis Farcy, Joris Jourdan, Committee: Interactive Presentations – City University of Hong Kong; King-Ning Tu – Yann Henrion, Emilie Deloffre, Haim Bilgem – Session Co-Chairs: University of California, Los Angeles STMicroelectronics Pat Thompson Texas Instruments, Inc. A Versatile Fan-Out Infrastructure Based 3D Printed Interposer Layer for High- Email: [email protected] on Die-Stencil Substrate Promoted by an Density Packaging of IoT Devices Advanced Multifunctional Temporary Saikat Mondal, Mohd. Ifwat Mohd. Ghazali, Kanishka Rao Bonda Bonding Material Wijewardena, Deepak Kumar, Premjeet Chahal – Amkor Technology, Inc. Xiao Liu, Baron Huang, Hong Zhang, Lisa Kirchner, Email: [email protected] Michigan State University Rama Puligadda, Tony Flaim – Brewer Science, Inc. Laundering Reliability of Electrically New Developments of Copper Plating Low-Temperature and Pressureless Conductive Fabrics for E-Textile Technology for Embedded Power Chip Microfluidic Electroless Bonding Process for Applications Vertical Interconnections Packages Jeffrey Lee – Integrated Service Technology, Inc.; H. T. Hung, S. Yang, I. A. Weng, C.R. Kao – Yung- Da Chiu - Advanced Semiconductor Weifeng Liu – Flex, Ltd. Engineering Inc. National Taiwan University; Y. H. Chen – Unimicron Preconditioning Technologies for Sputtered Technology Corporation Moisture Dependent Mechanical Behavior Seed Layers in FOPLP 3D Integration of CMOS-Compatible of Underfill Encapsulants Johannes Weichart, Jürgen Weichart, Andreas Erhart Surface Electrode Ion Trap and Silicon Promod Chowdhury, Jeffrey C. Suhling, Pradeep Lall – – Evatec Corporation; Lars Boettcher – Fraunhofer Photonics for Scalable Quantum Computing Auburn University IZM; Kay Viehweger – Fraunhofer IZM ASSID Jing Tao, Yu Dian Lim, Nam Piau Chew – Nanyang Effects of Electromigration on Impact of Thermal Boundary Resistance on Technological University; Hong Yu Li, Anak Agung Alit the Thermal Design of GaN-on-Diamond Microstructural Evolution and Mechanical Apriyana, Lin Bu – IME.A-STAR; Peng Zhao, Chuan HEMTs Properties of Preferred Orientation IMC Seng Tan – Nanyang Technological University; Luca Huaixin Guo, Yuechan Kong, Tangsheng Chen – Interconnects for 3D Packaging Guidoni – University Paris Diderot Nanjing Electronic Devices Institute Mingliang Huang, Lin Zou – Dalian University of RTD Sensor Based Approach for Technology Measuring the Electric Properties of Maintaining Thermal Uniformity During Thin-Film Shape Memory Polymers in TCB Process Telemetry for Implantable Biosensors Physiological Conditions Salwa Ben Jemaa, Julien Sylvestre – University of Ryan Green, Erdem Topsakal – Virginia Daniel Del Nero, Alexandra Joshi-Imre, Walter Voit – Sherbrooke; Pascale Gagnon, IBM Commonwealth University University of Texas at Dallas 28 Interactive Presentations: Wednesday, May 29, 2:00 p.m. - 4:00 p.m. and Thursday, May 30, 9:00 a.m. - 11:00 a.m.

Evaluation of WLP Dielectrics for High Vertical Interconnect Technology for PCB Microstrip Line Far-End Crosstalk Voltage Applications Enlarging Capacity on Micr-Solid Thin-Film Mitigation by Surface Mount Capacitors Marcus Paeck, Michael Toepper – Fraunhofer IZM Rechargeable Battery Zhaoqing Chen – IBM Corporation Akihiro Horibe, Kuniaki Sueoka, Risa Miyazawa, Systematic Failure Mode Based Underfill Mitigating the Effects of Microvortices in Hiroyuki Mori – IBM Corporation High-Re Deterministic Lateral Displacement Characterization Platform for Super Large Dynamic Characteristics Evaluation on by using Symmetric Airfoil-Shaped Pillars FCBGA NCF Under Challenging Conditions and its Brian Dincau, Kawkab Ahasan, Jong-Hoon Kim – Xiao Hu, Jiu Li, Shujun Dai, Shuming Lv, Chi Zhang, Application Washington State University Shujie Cai, Nan Zhao, Xiongcai Kuang – HiSilicon Tomonori Nakamura, Hiromi Shibahara, Osamu Technologies Co., Ltd. A Huawei Company Plasma Dry Process Technology Watanabe, Tetsuya Utano, Daisuke Tani, Sung New Cost-Effective Via-Last Approach by Development of Glass-Epoxy Film on the Chenhsiu Toru Maeda, Doug Day – Shinkawa Ltd; “One-Step TSV” After Wafer Stacking for Silicon Substrate to Fabricate RDL for Future Hidekazu Yagi, Ryoji Kojima – Dexerials Corporation 3D Memory Applications GPU/AI Application Electrical and Mechanical Simulation With Masaya Kawano, Xiang-Yu Wang, Qin Ren – Institute Finite-Element Model of Printed Inset Feed Takahide Murayama, Muneyuki Sato, Akiyoshi Suzuki, of Microelectronics Atsuhito Ihori, Tetsushi Fujinaga, Yasuhiro Morikawa Microstrip Patch Antenna Under Uniaxial – ULVAC, Inc. and Biaxial Bending Microstructure and Property Changes Yi Zhou, Rui Chen, Nahid Aslani Amoli, Sridhar in Cu/Sn-58Bi/Cu Solder Joints During Fully Solid-State Integrated Capacitors Sivapurapu, Mohamed Bellaredj, Madhavan Thermomigration Based on Carbon Nanofibers and Dielectrics Swaminathan, Suresh Sitaraman – Georgia Institute of Yu-An Shen, Shiqi Zhou, Hiroshi Nishikawa – Osaka with Specific Capacitances Higher than 200 Technology University; Jiahui Li – City University of Hong Kong; K. nF/mm^2 Effects of Oven and Laser Sintering N. Tu – University of California, Los Angeles Amin Saleem, Rickard Andersson, Maria Bylund, Parameters on the Electrical Resistance of Chiplet Microassembly Printer Charlotte Goemare, Guilhem Pacot, Shafiq Kabir, IJP Nano-Silver Traces on Mesoporous PET Eugene Chow, Brad Rupp, Anne Plochoweitz, Sergey Vincent Desmaris – Smoltek Before and During Fatigue Cycling Butylkov, Yunda Wang, Matthew Shreve, Sourbh Gurvinder Singh Khinda, Maan Z. Kokash, Mohammed Application of Fan-Out Panel Level Raychaudhuri, Lara Crawford, Jeng Ping Lu – Palo Alto Alhendi, Jack P. Lombardi, Darshana L. Weerawarne, Packaging Techniques for Development of Research Center Incorporated Mark D. Poliks, Peter Borgesen – Binghamton Flexible Hybrid Electronics Systems University; Nancy C. Stoffel – GE Global Research Simulation and Experimental Validations Wei-Yuan Cheng, Shau-Fei Cheng – Industrial of EM/TM/SM Physical Reliability for The Poisson’s Ratio of Lead-Free Solder – Technology Research Institute Interconnects Utilized in Stretchable and The Often Forgotten but Important Material Foldable Electronics Structuring of Laser Activated Polymers for Property Chang-Chun Lee, Oscar Chuang – National Tsing Sensor Applications KM Rafidh Hassan, Mohammad Alam, Jeffrey C. Hua; Chia-Ping Hsieh – National Taiwan University; Kevin Cromwell, Sebastian Bengsch, Maximilian Aue, Suhling, Pradeep Lall – Auburn University Wei-Yuan Cheng, Steve Chiu – Industrial Technology Marc Wurz – Leibniz University Multilayer Glass Substrate with High- Research Institute A Deep Learning Approach for Volterra Density Via Structure for Inorganic Based A Complex Structure Kernel Extraction for Time Domain Multi-Chip Packaging Module Toshiki Iwai, Taiji Sakai – Fujitsu Laboratories, Ltd. Transformation, Modeling and Simulation Simulation of Weakly Nonlinear Circuits Method Additive Laser Metal Deposition on Silicon Thong Nguyen, Xinying Wang – University of Illinois Daixing Wang, Yudan Pi, Wei Wang, Yufeng Jin– Arad Azizi, Matthias Daeumer, Scott Schiffres – Peking University 224G Package Interconnect Study Based on Binghamton University a New Neural Network Modeling Approach A Study on the Optimization of O2 Plasma UV-Stable and Transparent Polymer Hui Liu, Qian Ding, Penglin Niu – Intel Corporation Parameters on the Peel Adhesion Strength Modifications for Roll-to-Roll Processed High-Performance Reliability of SiP Module Solar Photovoltaic (PV) Module Packaging and Solder Wettability of SnBi58 Based by Mold Encapsulation with EMI Shielding Jinho Hah, Michael Sulkis, Minsoo Kang, Kyoung-sik Anisotropic Conductive Films Shuye Zhang, Tiesong Lin, Peng He – Harbin Institute Yu-Chou Tseng, Kuo-Hsien Liao, Alex Chan, Mark (Jack) Moon, Samuel Graham, C. P. Wong – Georgia of Technology; Ming Yang – Hisilicon Optoelectronics Gerber – Advanced Semiconductor Engineering, Inc. Institute of Technology Co., Ltd.; Kyung-Wook Paik – Korea Advanced Study of the Effect and Mechanism of a Cap Additive Laser Metal Deposition on Silicon Institute of Science and Technology Layer in Controlling the Statistical Variation Arad Azizi, Matthias Daeumer, Scott Schiffres – SUNY Binghamton Numerical Analysis of the Influence of of Via Extrusion Polymeric Materials on a MEMS Package Golareh Jalilvand, Tengfei Jiang – University of Central Thursday, May 30, 2019 Performance Under Humidity and Florida Session 39: Interactive Presentations 3 Temperature Loads Least-Squares Method Built in Processing Time: 9:00 AM – 11:00 AM Mahesh Yalagach, Peter Filipp Fuchs – Polymer Model of Finite Element Analysis Utilized Committee: Interactive Presentations Competence Center Leoben GmbH ; Luca Viero – to Obtain Accurate Prediction for Non- AMS AG; Qi Tao – AT&S Axisymmetric Warpage of 2L ETS MUF Session Co-Chairs: Electromigration-Induced-Sn Grain Rotation FCCSP SiP Michael Mayer in Lead-Free Flip Chip Solder Bumps Chih-Sung Chen, Nicholas Kao, Poyu Liao, Ssu-Cheng University of Waterloo Email: [email protected] Mingliang Huang, Jiameng Kuang, Hongyu Sun – Dalian Lai, Don Son Jiang – Siliconware Precision Industries University of Technology Co., Ltd. Alan Huffman Micross Advanced Interconnect Low-Cost MT-Ferrule-Compatible Optical Three-Dimensional Copper Foam-Filled Technology Connector for Co-Packaged Optics using Elastic Conductive Composites with Email: [email protected] Single-Mode Polymer Waveguide Simultaneously Enhanced Mechanical, Modeling and Design of Power Distribution Akihiro Noriki, Takeru Amano – National Institute of Electrical, Thermal and Electromagnetic Network for a Heterogeneous Integrated Advanced Industrial Science and Technology Interference (EMI) Shielding Properties Active Interposer with Neuromorphic Tan Lu, Han Gu, Tao Zhao, Yougen Hu, Pengli Computing Circuits Characterization of Coated Silver Wire Bond Zhu, Rong Sun – Shenzhen Institute of Advanced Min Miao, Jincan Zhang, Liyuan Wang, Huan Liu Interface Using TEM Technology, CAS; Ching-Ping Wong – Georgia – Peking University; Xin Sun – Beijing Information Murali Sarangapani, Eric Tan, Swee Seng, Jason Wong Institute of Technology Science and Technology University Chin Yeung – Heraeus 29 Interactive Presentations: Thursday, May 30, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m.

Research on Applied Reliability of BGA Thursday, May 30, 2019 Physics of Failure Based Simulation and Solder Balls in Extreme Marine Environment Session 40: Interactive Presentations 4 Experimental Testing of Quad Flat No-Lead Liyuan Liu, Tao Lu, Daojun Luo – MIIT Fifth Time: 2:00 PM – 4:00 PM Package Electronics Research Institute Committee: Interactive Presentations Jia-Shen Lan, Mei-Ling Wu – National Sun Yat-Sen University Influence of Single/Double Sweeping Modes Session Co-Chairs: Study of Design Optimization Method for and Sweeping Voltage Increments/Polarities Mark Eblen Ultra-Low Power Micro Gas Sensor Kyocera Corporation on Measurement of TSV Leakage Current Eiji Nakamura, Keiji Matsumoto – IBM Research; Email: [email protected] Qinghua Zeng, Jing Chen, Yufeng Jin – Peking Andrea Fasoli, Luisa Bozano – IBM Research; Hiroyuki University Jeffrey Lee Mori – IBM Research iST-Integrated Service Technology, Inc. An Assessment of Electromigration in 2.5D Preparation and Application of Cu-Ag Email: [email protected] Composite Solder Preform for Power Packaging Die Thickness Optimization for Preventing Jiefeng Xu, Huayan Wang, Jing Wang, Stephen R. Cain, Electronic Packaging Electro-Thermal Fails Induced by Solder S. B. Park Binghamton University; Scott McCann, Ho Dongxiao Zhang, Zhiwen Chen, Li Liu – Wuhan Voids in Power Devices Hyung Lee, Gamal Refai-Ahmed – Xilinx, Inc. University of Technology Dario Vitello, Andrea Albertinetti, Marco Rovitto – Diffusion Enhanced Drive sub 100 °C Wafer STMicroelectronics Zhaoxia Zhou, Canyu Liu, Stuart Robertson, Level Fine-Pitch Cu-Cu Thermocompression Changqing Liu – Loughborough University Reversed Pulsed Electrodeposition of Bonding for 3D IC Integration Nanostructured Nickel Tungsten With Improving the Solder Wettability via Asisa Kumar Panigrahi, Tamal Ghosh, Siva Rama Controlled Grain Structure as an Effective Krishna Vanjari, Shiv Govind Singh – Indian Institute of Atmospheric Plasma Technology Diffusion Barrier Layer Technology, Hyderabad Sagung Kencana, Yee-Wen Yen, Yu-Lin Kuo Nazila Dadvand – Texas Instruments, Inc. Extremely Detailed Package Level Thermal – National Taiwan University of Science and 3-T Decoupling Capacitors for Improved Modeling for an Enhaced Understanding Technology; Wallace Chuang, Eckart Schellkes – PDN in LPDDR4/4X/5 System of Passive Cooling Techniques in Wireless Robert Bosch Taiwan Co. Sunil Gupta – Qualcomm Technologies, Inc. Products Orthogonal Quilt Packaging 3D Integration Improved Correlation Between Accelerated Daniel Cox, Bhagyashree Ganore, Richard Perry, Sidharth Dalmia – Intel Corporation for High Energy Particle Detectors Board Level Reliability (BLR) Testing and Jason Kulick, Tian Lu, Carlos Ortega – Indiana Customer BLR Results Using a Hybrid Development of Sheet Type Molding Closed-Form/Finite Element Methodology Compound for Panel Level Package Integrated Circuits, LLC; Christopher Kenney, Julie Maxim Serebreni, Natalie Hernandez, Gil Sharon, Akira Nakao, KazuhiroDohi, YuiSuzuki, Masakazu Segal Stanford University; Gary Bernstein – University Nathan Blattau, Craig Hillman – DfR Solutions Hirose – Sanyu Rec Co., Ltd. of Notre Dame Fabrication and Reliability Demonstration of Defect Detection for the TSV Transmission Electroless Plating on 3D Printed Parts for 3 µm Diameter Photo Vias at 15 µm Pitch in Channel Using Machine Learning Approach RF Circuit Applications Thin Photosensitive Dielectric Dry Film for Huan Liu, Runiu Fang, Yufeng Jin – Peking University; Nicholas Bannon, Mohd Ifwat Mohd Ghazali, 2.5 D Glass Interposer Applications Min Miao – Beijing Information Science and Daichi Okamot, Yoko Shibasaki, Daisuke Shibata, Technology University Amanpreet Kaur, Premjeet Chahal – Michigan State Tadahiko Hanada – Taiyo Ink Mfg. Co. Ltd.; Fuhan University Direct Printing of Heat Sinks, Cases and Liu, Mohanalingam Kathaperumal, Rao R. Tummala – Power Connectors on Insulated Substrate Carbonized Electrodes for Electrochemical Georgia Institute of Technology using Selective Laser Melting Techniques Sensing Pre-Cure Modification of Electrically Rabih Khazaka, Donatien Martineau, Toni Youssef, Mohammad Aminul Haque, Nicole McFarlane – The Conductive Adhesive for Low-Temperature Thanh Long Le, Stephane Azzopardi – Safran University of Tennessee, Knoxville; Nickolay V. Lavrik, Interconnection Novel Solder Pads for Self-Aligned Flip-Chip Dale Hensley – Oak Ridge National Laboratory Jinto George, David Danovitch – University of Assembly Sherbrooke; Alexandre Leblanc, Eric Savage – IBM Yves Martin, Swetha Kamlapurkar, Nathan Marchack, Rectangular Waveguide and Interconnect Corporation Jae-Woong Nah, Tymon Barwicz – IBM Corporation Using Additive Manufacturing for W-Band RDL-1st Fan-Out Panel Level Packaging Integration and Characterization of InP Dies Kyoung Youl Park – Agency for Defense (FOPLP) for Heterogeneous and Economical on Silicon Interconnect Fabric Development; Mohd Ifwat Ghazali, Premjeet Packaging Eric Sorensen, Boris Vaisband, SivaChandra Jangam, Chahal – Michigan State University; Nophadon Nagendra Sekhar Vasarla, Srinivasa Rao Vempati, F. Subramanian S. Iyer – University of California, Los Wiwatcharagoses – King Mongkut’s University of X. Che, Ser Choong Chong, Kazunori Yamamoto – Angeles; Tim Shirley – Keysight Technologies Institute of Microelectronics A*STAR Technology at North Bangkok Server CPU Package Design Using PoINT Epoxy Composites with Surface Modified Architecture Moldability Challenges Associated with the Fillers for High-Temperature Arun Chandrasekhar, Vijaya Boddu, Erich Chuh, Assembly of Thicker IC Packages Molding Compounds Krishna Bharath, Farzaneh Yahyaei-Moayyed, Sadia Naseem, Jack Chiang, Bob Lee, Jason Chien – Fan Wu, Nicholas C. Mitchell, Bo Song, Kyoung-Sik Srikrishnan Venkataraman, Sriram Srinivasan, Ram Texas Instruments, Inc. Moon, C. P. Wong – Georgia Institute of Technology Viswanath, Ritesh Jain, Huthasana Kalyanam – Intel Corporation Highly Compact, Multiband Composite- Ultra-Low Resistivity and High Electrical Stability Silo-Ag ECAs Produced from Right/Left-Handed (CRLH) Transmission Highly Reliable Die Attach Silver Joint with Curing Chemistry Optimization for Flexible Pressure-Less Sintering Process Line Based Stub for Tri-Band GPS Electronics Sihai Chen, Christine LaBarbera, Ning-Cheng Lee Applications Xueqiao Wang, Kyoung-sik Moon, C. P. Wong – Indium Corporation; William Shambach, Jordan Hae-In Kim, Seahee Hwangbo, Yong-Kyu Yoon – – Georgia Institute of Technology; Bo Song – Palmer – Rochester Institute of Technology; Xuanyi University of Florida GLOBALFOUNDRIES Ding – Cornell University 30 Interactive Presentations: Thursday, May 30, 2:00 p.m. - 4:00 p.m and Friday, May 31, 8:30 a.m. - 10:30 a.m.

3D Power Packaged Device Thermo- On-Chip ESD Monitor Pressureless Transient Liquid Phase Sintering Mechanical Modeling and Stress Analysis Kannan Kalappurakal Thankappan, Boris Vaisband, Bonding of Sn-58Bi with Ni Particles for After Reliability Trials Subramanian S. Iyer – University of California, Los High-Temperature Packaging Applications Lucrezia Guarino – STMicroelectronics Angeles Kyung Deuk Min, Kwang-Ho Jung, Choong-Jae Lee, High-Density Ultra-Thin Organic Substrate Seung-Boo Jung – Sungkyunkwan University Preparation and Characterization of for Advanced Flip Chip Package Nokibul Islam, Seung Wook Yoon, K. H. Tan, Tony Electroplated Cu/Graphene Composite Epoxy/Cyanate Ester Copolymer for High- Chen – STATS ChipPAC Pte. Ltd. Xin Wang, Jian Cai, Yang Hu – Tsinghua University Temperature Encapsulant Applications Jiaxiong Li, Kyoung-Sik Moon, C. P. Wong – Georgia Millimeter Wave Dual Polarization Design Quantifying the Impact of RF Probing Institute of Technology Using Frequency Selective Surface (FSS) for Variability on TRL Calibration for LTCC 5G Base-Station Applications Substrates Low-Temperature Ag-Ag Direct Bonding Chi-Hau Yang, Chung-Yi Hsu, Lih-Tyng Hwang – Ömer Faruk Yildiz, David Dahl, Christian Schuster – Technology for Advanced Chip-Package National Sun Yat-Sen University. The Institut fur Theoretische Elektrotechnik Interconnection Low-Loss Additively Deposited Ultra- Jiaqi Wu, Chin C. Lee – University of California, Irvine Short Copper Paste Interconnections in 3D Effects of NCF and UBM Materials on Antenna-Integrated Packages for 5G and Electromigration Reliabilities of Sn-Ag Reliability of Micro-Alloyed SnAgCu Based IoT Applications Microbumps for Advanced 3D Packaging Solder Interconnections for Various Harsh Atom Watanabe, Yiteng Wang, Markondeya R. Kirak Son, Gahui Kim, Hyodong Ryu, Young-Cheon Applications Sinan Su, Francy Akkara, Anto Raj, Seth Pulugurtha, Vanessa Smet, Manos Tentzeris, Rao Kim, Jeong Sam Han, Young-Bae Park – Andong Tummala – Georgia Institute of Technology; Nobuo Gordon, Sharath Sridhar, Sivasubramanian National University; Gyu-Tae Park – Amkor Ogura – Nagase & Co., Ltd. Thirugnanasambandam, Sa’d Hamasha, Jeffery Suhling, Technology, Inc.; Ho-Young Son, Nam-Seog Kim – Direct Bonding of Low-Temperature John Evans – Auburn University; Cong Zhao – Apple, SK hynix Inc.; Cheol-Woong Yang – Sungkyunkwan Heterogeneous Dielectrics Inc. Serena Iacovo, Lan Peng, Alain Phommahaxay, University A Miniaturized and High-Performance Fumihiro Inoue, Patrick Verdonck, Soon-Wook Kim, Ag Diffusion Control Through Sn Bump on a 28GHz AiP with Integrated Metamaterials Erik Sleeckx, Miller Andy, Gerald Beyer, Eric Beyne Sequential Plating Based Process – IMEC Mei Xue – IMECAS Abderrahim EL Amrani, Etienne Paradis, David Twist Testing for Flexible Electronics Danovitch, Dominique Drouin – University of Automatic Transient Thermal Impedance Justin Chow, Suresh Sitaraman – Georgia Institute of Sherbrooke Tester for Quality Inspection of Soldered Technology; Jeffrey Meth – DuPont and Sintered Power Electronic Devices on Mechanical Reliability Assessment of Cu6Sn5 Modelling and Experimental Demonstration Panel and Tile Level Intermetallic Compound and Multilayer of Microfluidic Cooling for a Heterogeneous Maximilian Schmid, Sri Krishna Bhogaraju, Gordon 2.5D IC Structures in Cu/Sn Interconnects for 3D IC Elger – Technical University of Applied Research Sreejith Kochupurackal Rajan, Md Obaidul Hossen, Applications Time 0 Void Evolution and Effect on Thomas Sarvey, Ankit Kaul, Muhannad Bakir – Georgia Jui-Yang Wu, C. Robert Kao – National Taiwan Electromigration Institute of Technology; Gary May – University of University California, Davis Jiefeng Xu, Van Lai Pham, Huayan Wang, Stephen A Study on the Anchoring Polymer Layer R. Cain, S.B. Park – Binghamton University; Scott Friday, May 31, 2019 (APL) Anisotropic Conductive Films (ACFs) McCann, Ho Hyung Lee, Gamal Refai-Ahmed – Xilinx, Session 41: Student Interactive With Self-Exposed Surface of Conductive Inc. Presentations Particles for Ultra-Fine Pitch Chip-on-Glass Quintuple Band Quarter Wavelength Time: 8:30 AM – 10:30 AM (COG) Applications Stub Using Unbalanced Bridged CRLH Dal-Jin Yoon, Kyung-Wook Paik – Korea Advanced Committee: Interactive Presentations Transmission Lines Institute of Science and Technology Session Co-Chairs: Renuka Bowrothu, Seahee Hwangbo, Yong-Kyu Yoon Kristina Young-Fisher Bending Properties of Fine Pitch Flexible – University of Florida GLOBALFOUNDRIES CIF (Chip-in-Flex) Packages Using APL Product Level Design Optimization for 2.5D Email: Kristina.Young-Fisher@ (Anchoring Polymer Layer) ACFs (Anisotropic globalfoundries.com Package Shock Impact Reliability Conductive Films) Huayan Wang, Jing Wang, Jiefeng Xu, Vanlai Pham, Ibrahim Guven Ji-Hye Kim, Dal-Jin Yoon, Kyung-Wook Paik – Korea Virginia Commonwealth University Seungbae Park – Binghamton University; Hohyung Advanced Institute of Science and Technology Email: [email protected] Lee, Gamal Refai-Ahmed – Xilinx, Inc. Effect of the Curing Properties and Low-Temperature Transient Liquid Phase Microstructure of Sn-Ag-Cu (SAC) Solder (TLP) Bonding Using Eutectic Sn-In Solder Viscosities of Non-Conductive Films (NCFs) Joints by Mass-Reflow (MR) and Thermo- Anisotropic Conductive Films (ACFs) for on Sn-Ag Flip Chip Solder Bump Joint Compression Bonding (TCB) Process Flexible Ultrasonic Transducers Morphology and Reliability Jinho Hah, Jack Moon, CP Wong – Georgia Institute Jae-Hyeong Park, Kyung-Wook Paik – Korea HanMin Lee, SeYong Lee, SangMyung Shin, Kyung- of Technology; Yongja Kim – Samsung Electronics Advanced Institute of Science and Technology; Wook Paik – Korea Advanced Institute of Science Company, Ltd. Jongcheol Park – National NanoFab Center South and Technology; TaeJin Choi, SooIn Park – Doosan Korea Novel Decapsulation Method for Silver- Corporation Electro-Materials BG Room-Temperature Wire Bonding with Pd Based Wire Bond Semiconductor Packages Coated Cu Wire on Al Pads: Reliable Ball Experimental Investigations on Vertical with High Reliability Using Mixed Salt Acid Bonds using 2-Stage Optimization Ultrasonic Assisted Low-Temperature Chemistry Nicholas Kam, Michael Hook, Michael Mayer – Sintering Process Yong Ja Kim – Samsung Electronics Company, Ltd.; University of Waterloo; Celal Con, Karim Karim – KA Henning Seefisch, Jens Twiefel – Leibniz University Jinho Hah, Kyoung Sik (Jack), C. P. Wong – Georgia Imaging Hannover Institute of Technology 31 2019 TECHNOLOGY CORNER EXHIBITS

Today’s high-tech companies 3D Systems Packaging Research Heraeus Electronics Rudolph Technologies are being very selective in Advance Reproductions Corp Hitachi Chemical Co., Ltd. Samtec, Inc. choosing the conferences and trade shows where they AGC i3 Electronics Sanyu Rec Company Ltd. will exhibit their products AI Technology Inc. IBM Canada Ltd. SavansSys and services. Each year more Akrometrix, LLC Integrated Service Technology (iST) SCHOTT North America, Inc. companies have determined Alpha Novatech, Inc. Interconnect Systems, Inc. that ECTC provides them the Senju Comtek opportunity to identify superior Amkor Technology, Inc. JSR Micro, Inc. SET North America prospects. The primary Asahi Kasei Corporation Kyocera America SHENMAO AMERICA, Inc. reason is that the engineers ASE Group LINTEC of AMERICA INC. and managers who attend Shin-Etsu MicroSi, Inc. ECTC hold decision-making ASM Pacific Technology Malico Inc. Shinkawa USA, Inc. positions at the world’s leading ATO Tech Germany GmbH Mentor, A Siemens Business Shinko Electric America electronics equipment and Binghamton University Micross Advanced Interconnect Tech. component manufacturers. SPTS Technologies Ltd. Cadence Design Systems, Inc. Mini-Systems, Inc. (MSI) The attendees are attracted STATS ChipPAC, a JCET Company by ECTC’s strong technical Camtek USA Inc. Mitsui Chemicals America Suss Microtec program and excellent Canon USA Nagase America Corporation Exhibition attendance. Authors TAIYO INK MFG. CO., LTD CEA-LETI NAMICS Technologies, Inc. in the field believe that ECTC TATSUTA USA Inc. offers the best forum for Circuits Multi-Projets (CMP) Neu Dynamics Corp. TechSearch International Inc. presenting their work. Exhibit CPS Technologies Corporation Nepes Corporation hours will be from 9:00 AM TECNISCO, LTD. CVInc Nikon Metrology, Inc. to Noon and 1:30 to 6:30 PM ThreeBond International, Inc. on Wednesday, May 29, and DECA Technologies Nitto Inc. Teikoku Taping Systems 9:00 AM to Noon and 1:30 to DISCO Hi-Tec America, Inc. Nordson DAGE TOK America 4:00 PM on Thursday, May 30. DOWA International Corp. Nordson SONOSCAN(R), Inc. The demand for booths in the Toray International America exhibit hall continues to be very Dupont Electronics and Imaging NTK Technologies, Inc. high, and once again all booths EMD Performance Materials Ntrium Inc. Towa USA Corporation are already reserved. Following Evatec NA Inc. PAC TECH USA TRESKY GmbH is a list of exhibitors as of Feb. Trymax 5, 2019. The 2019 Exhibit EV Group, Inc. Palomar Technologies Inc. Brochure, a current exhibitor ficonTEC Panasonic Factory Solutions Unisem list, and a booth layout showing Finetech Panasonic Industrial Devices Sales Co. Xperi - Invensas the available booths can be XYZTEC found on the ECTC web site FlipChip International Plasma-Therm, LLC at www. ectc.net under the Fraunhofer Center for Applied Promex Industries Inc. Yield Engineering Systems heading Exhibits. Should you Fraunhofer Institute for Reliability PURE TECHNOLOGIES YOLE DEVELOPPEMENT need additional information or FUJIFILM Electronic Materials QualiTau ZEISS have questions, call Joe Gisler at +1-480-288-6660 or email HD MicroSystems, LLC Quik-Pak, a Division of Promex Zuken, Inc. [email protected] Henkel Electronic Materials Royce Instruments Zymet, Inc.

CONFERENCE REGISTRATION HOTEL RESERVATIONS The Cosmopolitan of Las Vegas • 3708 S. Las Vegas Blvd. • Las Vegas, NV 89109 USA FOR ECTC: Hotel reservations for ECTC can be made one of two ways: Online: Submit your registration 1) Contact The Cosmopolitan of Las Vegas at +1-877-551-7772 and reference the ECTC Conference to receive the conference rate of US$166 per night. electronically via www.ectc.net. Your or … registration must be received by the 2) Log onto www.ectc.net and click on the Location tab near the top of the page to find a special online cutoff date, May 2, 2019, to qualify for hotel registration link.

the early registration discounts. Note about Hotel Rooms Attendees should note that only reputable sites should be used to book a hotel room for ECTC. Be You may contact our registration advised that you may receive emails about booking a hotel room for ECTC from third-party companies. These emails and sites are not to be trusted. The only formal communication ECTC will staff at [email protected] for convey about hotel rooms will come in the form of ECTC e-blasts or ECTC emails from our Executive additional information. Payment can Committee. ECTC’s only authorized site for reserving a room is through our website (www.ectc. net). You may, however, use other trusted sites that you have personally used in the past to book be made by Visa, Mastercard, or travel. Please be advised, there are scam artists out there, and if it’s too good to be true, it likely is. Should American Express. you have any questions about booking a hotel room, please contact ECTC staff at: [email protected]

32 69th Electronic Components & Technology Conference

2019 ECTC REGISTRATION INFORMATION

Conference Registration Advance Registration Door Registration IEEE Member Attendee (full ECTC conference) US$750 US$860 Attendee (Joint ECTC + ITHERM conferences) $1000 $1160 Attendee One-Day Registration $565 $565 Speaker or Chair (full ECTC conference) $625 $765 Speaker or Chair One-Day Registration $430 $430 Non-IEEE Member Attendee (full ECTC conference) $950 $1055 Attendee (Joint ECTC + ITHERM conferences) $1110 $1375 Attendee One-Day Registration $565 $565 Speaker or Chair (full ECTC conference) $625 $765 Speaker or Chair One-Day Registration $430 $430 Student Attendee or Speaker (full conference) $315 $315 Exhibits Access to Exhibits Only (not attending conference) $25 $25 Exhibit Booth Attendant $0 $0 Professional Development Courses (PDCs) Note: all PDCs include a luncheon IEEE Member Full PDC (both a.m. and p.m.) $605 $710 Single PDC (a.m. or p.m.) $420 $500 Non-IEEE Member Full PDC (both a.m. and p.m.) $655 $710 Single PDC (a.m. or p.m.) $470 $500 Student Full PDC (both a.m. and p.m.) or Single PDC $130 $130 Other Registration Options Extra Proceedings $100 $100 Extra Luncheon Tickets $65 $65 Cancellation Fee $50 $50 Please log onto www.ectc.net/registration to register for the 2019 ECTC. There will be no refunds or cancellations after May 2, 2019. Please note that a $50 cancellation fee will be in effect for all cancellations made on or prior to May 2, 2019. Substitutions can be made at any time. For additional information about registration or ECTC please contact us at: Renzi & Company, Inc. • Phone: +1-703-863-2223 • Email: [email protected] *If you join IEEE BEFORE you register for the 2019 ECTC you can save on registration fees and receive a Electronics Packaging Society (EPS) membership free for one year! To take advantage of this offer, visit: https://www.ieee.org/membership-application/public/join.html?grade=Member&promo=EPS2019FREE At the URL, create your IEEE Web Account. Once complete, proceed to the Shopping Cart and enter EPS2019FREE in the promotion code box. Click “Apply” and the Shopping Cart will be updated to show the discount. Use your new IEEE membership ID number and register for ECTC at the discounted IEEE Member Rate. *Non-IEEE members can join IEEE and save $100 or more on ECTC registration and receive EPS membership free for 2019. Existing IEEE members receive a free EPS membership for the remainder of 2019 with ECTC registration.

33 CONFERENCE SPONSORS PLATINUM

www.aseglobal.com www.statschippac.com

GOLD

www.amkor.com www.asahi-kasei.co.jp www.atotech.com

www.cadence.com www.corning.com/worldwide www.decatechnologies.com

www.dupont.com/electronic-materials www.evgroup.com www.evatecnet.com

www.ibm.com www.istgroup.com www.lintec-usa.com www.micross.com

www.nepes.us www.pactech.com www.spil.com

www.spts.com www.suss.com www.taiyo-hd.co.jp www.zeiss.com SILVER

www.appliedmaterials.com www.micron.com www.lamresearch.com www.smoltek.com PROGRAM

averasemi.com www.brewerscience.com www.globalfoundries.com www.yieldengineering.com 34 CONFERENCE SPONSORS

TOTE BAGS BADGE LANYARD

www.emdgroup.com www.hdmicrosystems.com

STUDENT RECEPTION AND BEST STUDENT INTERACTIVE PRESENTATION INTEL BEST STUDENT PAPER

www.ti.com/support-packaging/packaging-information.html www.intel.com

INTERNET THUMB DRIVE

www.camtek.com www.amkor.com

REFRESHMENT BREAK

www.fujifilmusa.com www.jsrmicro.com www.microsoft.com

www.namics.co.jp www.tok.co.jp

MEDIA

Official Media Sponsor

www.chipscalereview.com Additional Media Sponsors

www.i-micronews.com www.3dincites.com www.circuitassembly.com

electroiq.com www.magneticsmagazine.com www.memsjournal.com

www.meptec.com www.semiconductorpackagingnews.com www.yole.fr 35 FIRST CLASS U.S. POSTAGE PAID RALEIGH, NC PERMIT NO. 2172

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Advance Registration through May 2, 2019 – Hotel Reservations through April 26, 2019 For more information, visit: www.ectc.net

Mark Your Calendar for ECTC 2020 Walt Disney World Swan & Dolphin Resort Lake Buena Vista, Florida, USA May 26-29, 2020