DOCSLIB.ORG

Assembly and Packaging

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Assembly and Packaging INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION ASSEMBLY AND PACKAGING THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009 TABLE OF CONTENTS Scope....................................................................................................................................1 Difficult Challenges................................................................................................................2 Single Chip Packaging ..........................................................................................................2 Overall Requirements......................................................................................................................2 Electrical Requirements ...............................................................................................................................3 Cross Talk ....................................................................................................................................................3 Power Integrity .............................................................................................................................................3 Thermal Requirements.................................................................................................................................3 Hot spots ......................................................................................................................................................4 Mechanical Requirements............................................................................................................................4 Mechanical Modeling and Simulation ..............................................................................................4 Cost ............................................................................................................................5 Reliability ............................................................................................................................5 Chip to Package Substrate..............................................................................................................7 Wire Bonding................................................................................................................................................7 Flip Chip .......................................................................................................................................................9 Molding.......................................................................................................................................................11 Package Substrate to Board Interconnect.....................................................................................11 Lead Frames ..............................................................................................................................................11 High Density Connections..........................................................................................................................11 Package Substrates.......................................................................................................................11 For Low-Cost Applications—Laminate for PBGA ......................................................................................12 Hand-held Applications—Fine Laminate for FBGA....................................................................................12 Mobile Applications—Build-up Substrate for SiP .......................................................................................12 Cost Performance Applications—Build-up Substrate for FCBGA..............................................................12 High Performance—Low κ Dielectric Substrate for FCBGA ......................................................................13 Wafer Level Packaging .......................................................................................................14 Wafer Level Package Developments and Trends .........................................................................16 Future trends for wafer level packaging.........................................................................................16 Difficult Challenges for WLP..........................................................................................................17 Examples for Emerging Wafer Level Package Technologies........................................................17 Wafer Level Through Silicon Via (TSV) for 3D Integration ........................................................................17 Fan out WLP using Reconfigured Wafer Level Technologies .......................................................19 System Level Integration in Package ..................................................................................19 Definition of SiP ..........................................................................................................................20 Difficult Challenges for SiP ............................................................................................................21 3D Integration......................................................................................................................22 Infrastructure Needs for 3-D ICs....................................................................................................23 Wafer/device stacking ................................................................................................................................23 New stacking solutions...............................................................................................................................23 Die Connectivity ..........................................................................................................................25 SiP Thermal Management..........................................................................................................................27 Thermal Challenge of Hot Spots in SiP......................................................................................................28 Cooling Solution Design Requirements for SiP .........................................................................................28 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009 Thermal Challenges of Processor and Memory Die SiP............................................................................29 Power delivery/power integrity ...................................................................................................................29 SiP versus SoC ..........................................................................................................................29 Testing of SiP ..........................................................................................................................30 Test access ................................................................................................................................................31 Contacts .....................................................................................................................................................31 Thermal Management ................................................................................................................................31 Mechanical and Thermal Testing ...............................................................................................................31 Cost of Test ................................................................................................................................................31 SiP for Tera-scale Computing........................................................................................................32 The Need for Co-Design Tools......................................................................................................32 Collaboration, Cost, and Time to Market....................................................................................................33 Importance of Reliability for SiP .................................................................................................................33 The Need for a Systematic Approach ........................................................................................................33 The Need for Co-Design Tool Development..............................................................................................33 Generic Chip-Package-System Co-Design Tool Development Requirements..........................................34 Co-simulation of RF, Analog/mixed signal, DSP, EM, and Digital .............................................................34 Packaging for Specialized functions....................................................................................35 Optoelectronic Packaging ..........................................................................................................................35 Data Transmission .....................................................................................................................................35 High Brightness LEDs for Solid State Lighting...........................................................................................40 RF and Millimeter Wave Packaging ...........................................................................................................44 Medical and Bio Chip Packaging ...............................................................................................................45
Load more

Recommended publications
  • Custom and Multichip Packaging Contract Manufacturing
    Custom & Multichip Packaging Contract Manufacturing Micross’ contract assembly offers design and engineering support, BOM procurement, and a wide selection of package, substrate and interposer materials. Micross provides comprehensive semiconductor packaging services for multiple electronic components, including digital, mixed signal, analog, multi-chip and System-in-Package (SiP). We design, build and test hermetic QML and chip scale packaging for various markets including down-hole, aerospace, satellite and military. We combine advanced processes and product development to provide full turnkey support for prototype to volume production of flip chip and wire bond packages including single chip, multichip and SiP applications on organic substrates or ceramic substrates. By ensuring delivery of finished wafers through our relationships with silicon OCMs, and full coordination of customer BOM requirements, we offer complete supply-chain management services for micro- electronic assemblies. Micross Components can support your custom design with: Micross supplies modules and contract assembly services for multiple platforms: industrial, airborne; commercial and government satellites; • Complete turnkey product - including program missile and ordnance; C4ISR and medical. and vendor management of all elements throughout the product lifecycle • Co-development of a statement of work (SOW) Custom Multichip Packaging (MCP) is a die based system or sub-system • Co-design, starting with schematic, netlist or product definition and documentation assembled into a single package which is then mounted to the PCB. • Environmental requirements review In its simplest form factor, two or more of the same die are combined in one industry standard package that is smaller than the equivalent • Package and material selection for optimization of electrical and environmental performance, single die packages combined.
    [Show full text]
  • Introduction to System IC Design Flow
    Introduction to System IC and Design Flow Outline System-on-a-Chip (SoC) Trend SoC Integration & Challenge System-in-a-Package (SIP) IC Industry and Chip Production Flow System IC Design Flow Chip Debugging Tools and Reliability Issues 2 SoC Concept Analog Memory PCB ASIC CPU Chip System on a Board Analog IP Memory IP Chip IP IP CPU System on a Chip 3 Soc Advantages Minimize System Cost PCB, passive components Assembling Testing Compact System Size Board layout vs. chip layout Reduce System Power Consumption I/O, passive components, current levels Increase System Performance Interconnecting delay High speed parallel bus 4 Years 2002 – 2008 Worldwide Communication SoC Market Values Unit: Million U.S. Dollars Product 2002 2003 2004 2005 2006 2007 2008 Digital Cellular 7,480 9,463 12,560 15,210 15,855 17,202 19,013 LAN Wireless 138 333 492 662 777 938 1,134 Mobile Infrastructure 325 344 418 537 511 479 481 Other Mobile Comms. 378 520 673 859 1,077 1,215 1,440 LAN 140 184 248 316 348 392 446 Premises and CO Line Card 167 161 188 201 199 204 219 Broadband Remote Access 918 1,313 1,617 1,793 1,717 1,837 1,978 Public Infrastructure 304 360 481 607 667 810 934 Other Wired Comms. 428 568 811 1,128 1,175 1,365 1,515 Total Communications 10,278 13,246 17,488 21,313 22,326 24,442 27,160 Source: Dataquest (2004/06) 5 Example1: Siemens C35i Phone 13 1. Infineon E-GOLD PMB2851E, GSM Baseband controller and DSP.
    [Show full text]
  • Development of 3-D Printed Hybrid Packaging for Gaas-MEMS
    University of South Florida Scholar Commons Graduate Theses and Dissertations Graduate School June 2018 Development of 3-D Printed Hybrid Packaging for GaAs-MEMS Oscillators based on Piezoelectrically-Transduced ZnO-on-SOI Micromechanical Resonators Di Lan University of South Florida, [email protected] Follow this and additional works at: https://scholarcommons.usf.edu/etd Part of the Electrical and Computer Engineering Commons Scholar Commons Citation Lan, Di, "Development of 3-D Printed Hybrid Packaging for GaAs-MEMS Oscillators based on Piezoelectrically-Transduced ZnO- on-SOI Micromechanical Resonators" (2018). Graduate Theses and Dissertations. https://scholarcommons.usf.edu/etd/7690 This Dissertation is brought to you for free and open access by the Graduate School at Scholar Commons. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Scholar Commons. For more information, please contact [email protected]. Development of 3-D Printed Hybrid Packaging for GaAs-MEMS Oscillators based on Piezoelectrically-Transduced ZnO-on-SOI Micromechanical Resonators by Di Lan A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Jing Wang, Ph.D. Thomas M. Weller, Ph.D. Arash Takshi, Ph.D. Rasim Guldiken, Ph.D. Shengqian Ma, Ph.D. Date of Approval: June 14, 2018 Keywords: Microelectromechanical Systems, Additive Manufacturing, MMIC, Microfabrication Copyright © 2018, Di Lan DEDICATION To my wife, my parents, my advisors, my friends ACKNOWLEDGMENTS First, I would like to state my greatest appreciation to my major advisor and Professor Dr.
    [Show full text]
  • Advanced Ic Packaging Technologies, Materials, and Markets 2015 Edition
    ADVANCED IC PACKAGING TECHNOLOGIES, MATERIALS, AND MARKETS 2015 EDITION A Strategic Report Covering the Latest Technologies in IC Packaging, Enabling Portable and Other Electronics Report Coverage Report Highlights Stacked Packages Industry Outlook System-in-Packages Market Analysis and Forecasts, Interconnection Technologies 2013–2019 Through-Silicon-Vias (TSV) Multichip Packaging 2.5D and 3D Integration Technology Trends Multi-row QFNs Key Application Forecasts Fan-out WLPs Company Profiles New Venture Research A Technology Market Research Company 337 Clay St., Suite 101 [email protected]/ Nevada City, CA 95959 www.newventureresearch.com/ Tel: (530) 265-2004 Fax: (530) 265-1998 Advanced IC Packaging Technologies, Materials, and Markets, 2015 Edition Synopsis The demand for consumer electronics and mobile QFNs and WLPs), as well as advanced communications devices that keep us connected is multicomponent packages (PoPs, PiPs, and MCMs). driving electronics manufacturers to deliver ever-more Forecasts include multichip IC packaging units, compact and portable electronic systems. Today's revenue, prices, die usage and applications. users ask for products with more functionality, added performance, higher speed, and smaller form factors. Chapter 6: System in Package (SiP) Solutions & Advances in IC packaging technologies are providing Substrate Materials, presents a more in-depth look at solutions to meet these demands through a variety of the evolving multicomponent packages, and presents techniques that result in ICs that are more powerful and key market trends alongside forecasts of units and provide greater functionality, while fitting into ever revenue. This chapter also examines the substrate smaller and more highly integrated form factors. materials and embedded components used in SiP Multichip packages are on the leading edge of silicon assembly.
    [Show full text]
  • Fpga Hardware
    L2: FPGA HARDWARE 18-545: ADVANCED DIGITAL DESIGN PROJECT FALL 2011 BILL NACE Administrivia Team assignments are done Lab 1 is due Monday Project Proposals happen on Monday Reading Assignment #1 due today 13/14 students got it in to Blackboard on time David's attempt didn't get saved (?) Submit a PDF, don't fill in the web form 18-545: FALL 2011 2 Game Plan Overview Why use FPGAs? FPGA Internals Caveat: I will use Xilinx specific terminology since that’s the FPGA company you will be using. Beware that other companies use different terms 18-545: FALL 2011 3 FPGA Overview Field Programmable Gate Array Array of generic logic gates Gates where logic function can be programmed Programmable interconnection between gates Fielded systems can be programmed i.e. post-fabrication Xilinx Virtex-5 FPGA 18-545: FALL 2011 5 Design Platform Virtex-5 Development System Xilinx XC5VLX110T FPGA 17280 slices of CLB goodness 256MB DDR2 (SODIMM) DVI Video port VGA port is for input 10/100/1000 Ethernet port Audio Codec (AC97) USB2 port 16x2 LCD, RS-232 Compact Flash card slot Expansion connectors 18-545: FALL 2011 6 Game Plan Overview Why use FPGAs? FPGA Internals 18-545: FALL 2011 7 Why use FPGAs? System designers have a Goldilocks problem Off-the-shelf parts are not efficient enough Custom ASICs cost too much Need a “just right” solution ASIC Design Difficult to design Large and complex Issues in advanced processes Interconnect delay Device leakage Power density constraints Expensive to design / fabricate Mask set costs Non-recurring engineering costs Need a high-volume, high-profit market to justify costs! Energy Efficiency (MOPS/mW) Area Efficiency (MOPS/mm2) 10000 1000 Microprocessors 100 10 1 0.1 DSPs ASICs 0.01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Efficiency View An efficiency gap exists between ASICs and CPUs N.
    [Show full text]
  • Integrated Circuit Package Types
    APPENDIX C Integrated Circuit Package Types Overview With the ever-increasing levels of integration, packing more circuitry into ever smaller packages, electronic systems now rely on semiconductor devices. Anything from a few circuit components (transistors, resistors, and capacitors) to complete computer systems can be placed on a single silicon die. An integrated circuit is a package containing a single silicon (silicon germanium for RF circuits, or gallium arsenide for microwave frequency circuits) that forms either part of a larger electronic circuit or system or is a complete electronic system in its own right. When the IC forms a complete electronic system, it is commonly referred to as a system on a chip (SoC). Modern communications ICs are SoC designs. An extension to the IC is the multichip module (MCM), which contains multiple dies; for example, when sensors and circuits are to be housed in a single package but which cannot be fabricated on a single die. Originally referred to as a hybrid circuit, the MCM consists of two or more ICs and passive components on a common circuit base that are interconnected by conductors fabricated within that base. The MCM helps with size reduction problem and helps alleviate signal degradation. An extension to the MCM is the system in a package (SiP), on which devices are stacked vertically. Wire bonding to the substrate is common. An extension to the SiP is the package on a package (PoP). www.newnespress.com 2 Appendix C IC Package Types The package that the IC uses is either a through-hole package or a surface mount package, made of either plastic or ceramic.
    [Show full text]
  • 3-D Packaging: a Technology Review
    3-D Packaging: A Technology Review R. Wayne Johnson Auburn University 162 Broun Hall/ECE Dept. Auburn, AL 36849 334-844-1880 [email protected] Mark Strickland NASA/MSFC Huntsville, AL David Gerke NASA/JPL Pasadena, CA June 23, 2005 3-D PACKAGING A TECHNOLOGY REVIEW Table of Contents 2 INTRODUCTION 3 Package Stacking 8 Benefits of Package Stacking 14 Limitations of Package Stacking 14 Reliability 15 Technology Readiness Level Assessment 17 Die Stacking 17 Benefits of Die Stacking 33 Limitations of Die Stacking 34 Reliability 35 Technology Readiness Level Assessment 36 3-D Multichip Modules 37 Benefits of 3-D Multichip Modules 54 Limitations of 3-D Multichip Modules 54 Reliability 54 Technology Readiness Level Assessment 55 Wafer Stacking 56 Benefits of Wafer Stacking 60 Limitations of Wafer Stacking 60 Technology Readiness Level Assessment 63 Conclusions and Recommendations 64 References 65 2 3-D Packaging A Technology Review Introduction Traditional electronics are assembled as a planar arrangement of components on a printed circuit board (PCB) or other type of substrate. These planar assemblies may then be ‘plugged’ into a motherboard or card cage creating a ‘volume’ of electronics. This architecture is common in many military and space electronic systems as well as large computer and telecommunications systems and industrial electronics. The individual PCB assemblies can be replaced if defective or for system upgrade. Some applications are constrained by the volume or the shape of the system and are not compatible with the motherboard or card cage architecture. Examples include missiles, camcorders, and digital cameras. In these systems, planar rigid-flex substrates are folded to create complex 3-D shapes.
    [Show full text]
  • Integrating MEMS and Ics
    OPEN Microsystems & Nanoengineering (2015) 1, 15005; doi:10.1038/micronano.2015.5 © 2015 IECAS All rights reserved 2055-7434/15 www.nature.com/micronano Review Article Integrating MEMS and ICs Andreas C. Fischer, Fredrik Forsberg, Martin Lapisa, Simon J. Bleiker, Göran Stemme, Niclas Roxhed and Frank Niklaus The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the ‘More-Than- Moore’ paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated.
    [Show full text]
  • 2006 Technical Program
    International Microelectronics Assembly and Packaging Society New England Chapter 43rd Annual Symposium Technical Sessions - May 3, 2016 Symposium’s Technical Chairs Welcome Letter We’d like to welcome everyone to the 43nd Annual New England iMAPS Symposium! Thanks to all the Session Chairs we’ve compiled an engaging program of technical talks on many of today’s hot topics that will peak the interest of every Attendee. We hope you take full advantage of the opportunity to interact with the speakers and each other in a learning environment that’s only available at this unique one day symposium. Below is a brief summary to help you on your way and don’t forget to spend time in the exhibit hall, because after all without the support of the exhibitors this day wouldn’t be possible. Enjoy!!! Dmitry Marchenko Dr. Parshant Kumar RF and Microwave - Innovations and Emerging Technologies: This session is all about the innovations and emerging technologies that are driving RF and microwave packaging industry. Returning by popular demand and includes talks from industry leaders such as CST, Ametek and Draper. The topics cover issues like EM coupling between buck converters and antennas, Low Loss Additive Materials and design challenges of millimeter-wave semiconductor packaging. 3D and Beyond: This session covers the latest advancements in 2.5/3D technology. A Novel way to produce 3D chip assemblies called Quilt will be presented by IIC. Presentation by Tufts will describe liquid metal interconnects use in studies of animals and soft robots. You will learn about the latest Draper work on Printed transceivers.
    [Show full text]
  • For Your System in a Package
    Unify ASICs for your System in a Package with TEKMOS Introducing Unify ASICs Applications for System in a Package are driven by the requirements of space, power, and development time. The total solution needs to be small. It typically runs off of a battery. And it needs a quick time-to-market. The major semiconductor suppliers have developed a number of cost effective blocks that can meet 90% of the requirements of an application. It is the last 10% that is the problem. Developers typically face two approaches for the last 10%. You can build what you need out of discrete components. This is inexpensive, but Picture of Stacked Die. requires a lot of board space. Or you can take a SOC (System on a Chip) approach. This will work, BGA packages, die can be stacked side by side as but can be very expensive, since the presence of well as on top of each other. And in some cases, we wireless interfaces and ARM processors requires can also include components that we cannot put on advanced processing to accommodate the diverse the ASIC such as large capacitors, and crystals. No requirements of diverse technologies as well as matter what package we use, the customer wins by expensive NREs. And such solutions require more having a single, highly integrated device for their development time because of the chip complexity. system. Tekmos has a third approach. We create a cost Technology effective ASIC using an appropriate technology to It is a fact that the NRE costs roughly double for implement the missing 10%.
    [Show full text]
  • Pfesip EP-1 Configurable IC Card Reader/Writer Engine PF
    To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples.
    [Show full text]
  • Trends in Assembling of Advanced IC Packages Ryszard Kisiel and Zbigniew Szczepański
    Invited paper Trends in assembling of advanced IC packages Ryszard Kisiel and Zbigniew Szczepa«ski Abstract|In the paper, an overview of the current trends ical area occupancy on the PCB, about three times com- in the development of advanced IC packages will be pre- pared to QFP for this I/O range. Shorter connections of- sented. It will be shown how switching from peripheral fered by CSP reduce parasitic inductance and capacitance. packages (DIP, QFP) to array packages (BGA, CSP) and multichip packages (SiP, MCM) affects the assembly pro- Table 2 cesses of IC and performance of electronic systems. The Comparison of key features of various packages [2] progress in bonding technologies for semiconductor packages will be presented too. The idea of wire bonding, flip chip Feature QFP BGA CSP and TAB assembly will be shown together with the bound- I/O 208 225 313 aries imposed by materials and technology. The construction Pitch [mm] 0.5 1.27 0.5 of SiP packages will be explained in more detail. The paper Footprint [mm2] 785 670 252 addresses also the latest solutions in MCM packages. Height [mm] 3.37 2.3 0.8 Keywords| IC packages, SiP, wire bonding, TAB, flip chip. Package to die ratio 8 7 1 Inductance [nH] 6.7 1.3 { 5.5 0.5 { 2.1 Capacitance [pF] 0.5 { 1 0.4 { 2.4 0.05 { 0.2 1. Introduction Compared to leaded packages such as QFPs, BGA and CSP The development of the electronics industry is dominated packages are expensive. The cost is about twice as high, by communication products, which are characterised by but when cost per I/O is taken into account the prices be- rapid market introduction and fast mass-manufacturing ca- come almost the same.
    [Show full text]