INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION ASSEMBLY AND PACKAGING THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009 TABLE OF CONTENTS Scope....................................................................................................................................1 Difficult Challenges................................................................................................................2 Single Chip Packaging ..........................................................................................................2 Overall Requirements......................................................................................................................2 Electrical Requirements ...............................................................................................................................3 Cross Talk ....................................................................................................................................................3 Power Integrity .............................................................................................................................................3 Thermal Requirements.................................................................................................................................3 Hot spots ......................................................................................................................................................4 Mechanical Requirements............................................................................................................................4 Mechanical Modeling and Simulation ..............................................................................................4 Cost ............................................................................................................................5 Reliability ............................................................................................................................5 Chip to Package Substrate..............................................................................................................7 Wire Bonding................................................................................................................................................7 Flip Chip .......................................................................................................................................................9 Molding.......................................................................................................................................................11 Package Substrate to Board Interconnect.....................................................................................11 Lead Frames ..............................................................................................................................................11 High Density Connections..........................................................................................................................11 Package Substrates.......................................................................................................................11 For Low-Cost Applications—Laminate for PBGA ......................................................................................12 Hand-held Applications—Fine Laminate for FBGA....................................................................................12 Mobile Applications—Build-up Substrate for SiP .......................................................................................12 Cost Performance Applications—Build-up Substrate for FCBGA..............................................................12 High Performance—Low κ Dielectric Substrate for FCBGA ......................................................................13 Wafer Level Packaging .......................................................................................................14 Wafer Level Package Developments and Trends .........................................................................16 Future trends for wafer level packaging.........................................................................................16 Difficult Challenges for WLP..........................................................................................................17 Examples for Emerging Wafer Level Package Technologies........................................................17 Wafer Level Through Silicon Via (TSV) for 3D Integration ........................................................................17 Fan out WLP using Reconfigured Wafer Level Technologies .......................................................19 System Level Integration in Package ..................................................................................19 Definition of SiP ..........................................................................................................................20 Difficult Challenges for SiP ............................................................................................................21 3D Integration......................................................................................................................22 Infrastructure Needs for 3-D ICs....................................................................................................23 Wafer/device stacking ................................................................................................................................23 New stacking solutions...............................................................................................................................23 Die Connectivity ..........................................................................................................................25 SiP Thermal Management..........................................................................................................................27 Thermal Challenge of Hot Spots in SiP......................................................................................................28 Cooling Solution Design Requirements for SiP .........................................................................................28 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009 Thermal Challenges of Processor and Memory Die SiP............................................................................29 Power delivery/power integrity ...................................................................................................................29 SiP versus SoC ..........................................................................................................................29 Testing of SiP ..........................................................................................................................30 Test access ................................................................................................................................................31 Contacts .....................................................................................................................................................31 Thermal Management ................................................................................................................................31 Mechanical and Thermal Testing ...............................................................................................................31 Cost of Test ................................................................................................................................................31 SiP for Tera-scale Computing........................................................................................................32 The Need for Co-Design Tools......................................................................................................32 Collaboration, Cost, and Time to Market....................................................................................................33 Importance of Reliability for SiP .................................................................................................................33 The Need for a Systematic Approach ........................................................................................................33 The Need for Co-Design Tool Development..............................................................................................33 Generic Chip-Package-System Co-Design Tool Development Requirements..........................................34 Co-simulation of RF, Analog/mixed signal, DSP, EM, and Digital .............................................................34 Packaging for Specialized functions....................................................................................35 Optoelectronic Packaging ..........................................................................................................................35 Data Transmission .....................................................................................................................................35 High Brightness LEDs for Solid State Lighting...........................................................................................40 RF and Millimeter Wave Packaging ...........................................................................................................44 Medical and Bio Chip Packaging ...............................................................................................................45