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Trends in Assembling of Advanced IC Packages Ryszard Kisiel and Zbigniew Szczepański

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Trends in Assembling of Advanced IC Packages Ryszard Kisiel and Zbigniew Szczepański Invited paper Trends in assembling of advanced IC packages Ryszard Kisiel and Zbigniew Szczepa«ski Abstract|In the paper, an overview of the current trends ical area occupancy on the PCB, about three times com- in the development of advanced IC packages will be pre- pared to QFP for this I/O range. Shorter connections of- sented. It will be shown how switching from peripheral fered by CSP reduce parasitic inductance and capacitance. packages (DIP, QFP) to array packages (BGA, CSP) and multichip packages (SiP, MCM) affects the assembly pro- Table 2 cesses of IC and performance of electronic systems. The Comparison of key features of various packages [2] progress in bonding technologies for semiconductor packages will be presented too. The idea of wire bonding, flip chip Feature QFP BGA CSP and TAB assembly will be shown together with the bound- I/O 208 225 313 aries imposed by materials and technology. The construction Pitch [mm] 0.5 1.27 0.5 of SiP packages will be explained in more detail. The paper Footprint [mm2] 785 670 252 addresses also the latest solutions in MCM packages. Height [mm] 3.37 2.3 0.8 Keywords| IC packages, SiP, wire bonding, TAB, flip chip. Package to die ratio 8 7 1 Inductance [nH] 6.7 1.3 { 5.5 0.5 { 2.1 Capacitance [pF] 0.5 { 1 0.4 { 2.4 0.05 { 0.2 1. Introduction Compared to leaded packages such as QFPs, BGA and CSP The development of the electronics industry is dominated packages are expensive. The cost is about twice as high, by communication products, which are characterised by but when cost per I/O is taken into account the prices be- rapid market introduction and fast mass-manufacturing ca- come almost the same. In addition, the substrates on which pabilities. The main drivers of this development are minia- chips have to be used are generally more expensive because turisation and styling or eco design and production. The more layers and possibly microvias are needed. industry has made great strides in reducing the package size from the dual in line package (DIP) and quad flat pack (QFP) to ball grid array (BGA) and chip scale pack- 2. Packaging technology requirements age (CSP). Table 1 illustrates the current trends in IC pack- aging. Standard leadframe packages still have the largest System integration is a key element for manufacturing market share. Packages like BGA and CSP have gained future products. The idea behind system integration is increasing importance and popularity. CSPs are used more to combine individual components and subsystems into often than BGAs, in packaging, e.g., of memory prod- a functional electronic system. Assembly and packaging ucts, controllers and digital signal processors, due to their of the semiconductor products are an essential part of this smaller size. process. The most difficult challenges facing the assembly and packaging industry, according to the ITRS roadmap, Table 1 are as follows [1, 3]: Trends in IC packages, 2001{2006 [1] • Improved organic substrates. The substrates must Standard be compatible with Pb-free solder processing. Im- Package type BGA CSP (QFP) proved impedance control and lower dielectric losses Max body size [mm] 30!32 40!50 27!20 are needed to support higher frequency applications. Max number of I/Os 300!320 900!3500 400!650 The substrates must be characterised by low mois- Min lead/ball pitch [mm] 0:4!0:3 0:75!0:5 0:5!0:3 ture absorption, improved planarity and low wrapage Max package at higher process temperatures as well as low-cost 1:4!1:0 2:0!1:0 1:2!0:7 thickness [mm] embedded passives. Market share [%] 88!78 4!7 4!15 • Improved underfillers for flip chip on organic sub- US$ ct/I/O 0:8!0:4 0:9!0:6 0:9!0:4 strates. Underfiller must have improved flow, fast dispense/cure properties, better interface adhesion, and lower moisture absorption, as well as higher Table 2 compares the main features of QFP, BGA and CSP operating temperature range for automotive appli- at a comparable I/O number in the range of 200{300. It is cations and Pb-free soldering in liquid dispense obvious that switching to CSP packages reduces the phys- underfiller. 63 Ryszard Kisiel and Zbigniew Szczepa«ski • Impact of Cu/low κ on packaging. Direct wire- telecommunication equipment [3, 4]. The key single-chip- bond and bump to Cu must be possible. Mechanical package technology requirements are shown in Table 3. strength of dielectrics must be improved and bump Economic aspects are especially important here. Assem- as well as underfill technology must assure low κ di- bly and packaging costs are expected to decrease over time electric integrity. New tests to measure the critical on a cost-per-pin basis, but the chip and package pin- properties need to be developed. count is increasing more rapidly than the cost-per-pin is • New system level technologies must be capable to decreasing. integrate chips, passives and substrates. Embeded passives may be integrated into the \bumps" as well as the substrates. Bumpless area array technologies 3. Bonding technology for chip must be developed, for example for face-to-face con- packaging level nection. • Pb, Sb and Br free packaging materials. New ma- There are three chip-level interconnection technologies cur- terials and processes must meet new requirements, rently in use: including higher reflow temperature and reliability under thermal cycling. { wire bonding (WB), To fulfil these requirements special attention must be paid { flip chip (FC), to [8]: { tape automated bonding (TAB). { area array packaging (flip chip, CSP, SiP), Wire bonding is a well established bonding technology. { cost efficient and flexible substrate materials, This technique is used for over 90% of all interconnections. { thin semiconductor chips, Flip chip is another technique that has been a steadly gain { cost efficient bumping process, in importance, particularly in new applications where sys- tem performance and miniaturisation is important. It also { fine pitch and multilayer technology, offers special advantages in terms of high accuracy in chip { integration of passive components into the substrate, placement by self-adjustment when solder bumps are on { integration of optical and electrical signal transmis- the die. This is of special interest for the integration of sion, optical interfaces in electro-optical devices. { material characterization (model and measurement), A concept of TAB process was initiated in the 1960s by General Electric. In the mid-90s TAB process was widely { environmentally compatible choice of materials and used in high volume products, such as Pentium laptops processes. and high resolution printers [7]. Now it is not use so often. Such requirements are more prominent in cost-performance The comparison of the three bonding techniques, mentioned applications, such as notebooks, personal computers and above, in aspect of signal propagation delay is shown in Table 4. Table 3 Table 4 Development of selected packaging parameters in the next Typical values for lead capacitance and inductance [7] decade [3, 4] Bonding technique Capacitance [pF] Inductance min [nH] Year Wire bond 0.5 6 Parameter TAB 0.6 2 2002 2006 2010 Flip chip 0.1 0.2 Chip size [mm2] 178 206 268 Cost [cents/pin] 0.75{1.44 0.56{1.03 0.48{0.98 Core voltage [V] 1.5 0.9 0.6 Propagation time is directly proportional to the length of Package pincount 480{1320 550{1936 780{2700 interconnection, the longer the lead the greater the propa- Package thickness [mm] 1.0{1.2 0.8{1.2 0.65{0.80 gation delay and the slower the off-the-chip system speed. Performance 2320 5630 12000 on chip [MHz] 3.1. Wire bonding assembly Performance: peripheral 200/660 300/966/1062 300/1415 buses [MHz] In \standard" packaging , the interconnection between the Junction temp. ◦ 85 85 85 die and the carrier is made using the wire. Different max [ C] types of wires are used for the wire bond process: gold, Chip interconnect 35 20 20 aluminium and copper. The die is attached to the car- pitch [mm] rier face up, then a wire is bonded first to the die, then Flip chip pitch [ m] 160 130 90 m looped and bonded to the carrier (Fig. 1) [9]. Wires are 64 Trends in assembling of advanced IC packages The bump material is predominantly gold. Without the danger of solder-bridge formation, smaller pitches can be implemented with adhesive techniques. Furthermore, sub- strates can be used which cannot withstand the melting tem- perature of the eutectic lead/tin solder or lead-free alloys. Adhesive flip chip bonding, based mainly on the anisotrop- ically conductive adhesive, is the dominant technology for LC-displays assembly. The main benefits and features that flip chip can offer are: • Fig. 1. Wire bonding technology applied in BGA package. High package density without the need for lead frame. • Enhanced electrical performance as a result of short typically 1{5 mm in length and 25{35 µm in diameter. distance between chip and substrate, including min- The process used most often to realize these interconnec- imal propagation delay, minimal transmission losses tions is thermosonic bonding with gold wire. at high frequency, and low parasitic capacitance as well as inductance values. 3.2. Flip chip assembly • Low thermal resistance solder bonds serve primarily The term flip chip describes a method of establishing elec- as heat-dissipating paths, thus suitable for high-speed trical connectors between the die and the package carrier. electronic devices. The interconnection between the die and the carrier in • Power can be spread directly from the core of the die flip chip packaging is made through a conductive \bump" to laminate (substrate).
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