856 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link Makoto Saen, Kenichi Osada, Member, IEEE, Yasuyuki Okuma, Kiichi Niitsu, Member, IEEE, Yasuhisa Shimazaki, Member, IEEE, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Member, IEEE, Atsushi Hasegawa, and Tadahiro Kuroda, Fellow, IEEE Abstract—This paper describes a three-dimensional (3-D) and wireless) have been proposed [1]–[10]. A major wired-in- system integration of a full-fledged processor chip and two terconnect technique is through-silicon via (TSV) [6]–[10]. The memory chips using inductive coupling. To attain a 3-D commu- density of 3-D inter-chip connections can near that of on-chip nication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation wires when using the TSV technique. However, it increases due to unused inductors are important challenges. Therefore, cost of chip fabrication due to increase of fabrication-process we developed a new 3D-integrated wire-penetrated multi-layer complexity. On the other hand, inductive coupling [1]–[4], a structure for a shorter link distance and an open-skipped-inductor major wireless-interconnect technique, does not increase the scheme for suppressing signal degradation. In addition, to avoid process complexity because inductors for inductive coupling undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control are formed using metal layers of standard CMOS process. scheme with a pinpoint-data-capture scheme. We demonstrate Therefore, inductive coupling is an inexpensive 3D-integra- that three fabricated chips can be successfully AC-coupled using tion solution. An inductive-coupling link for high-bandwidth inductive coupling. The power and area efficiency of the link are P between one processor chip and one memory chip was reported 1 pJ/b and 0.15 mm Gbps, respectively, which are the same as [2]. Their work shows that an inductive coupling link can con- those of two-chip integration. nect a processor chip and a memory chip with high-bandwidth. Index Terms—Inductive coupling, three-dimensional system In addition to the increase in bandwidth, increase in memory integration. capacity is also necessary to improve performance of processor systems. Our technical challenge is to achieve large memory ca- I. INTRODUCTION pacity using the inductive-coupling link [1]. The simple and ef- fective solution for this purpose is to stack multiple same-sized memory chips on a processor chip. However, there are two is- HE processing performance of processor chips continues sues to address. The first is to develop 3D-stacking technology T to increase by integrating more processing cores in a to attain a shorter link distance for a smaller area and lower chip, from dual core to many core. To improve the performance power consumption of interconnect circuits. The second issue for practical applications, inter-chip bandwidth between a is to prevent signal degradation due to unused inductors. processor chip and a memory chip and memory capacity must We developed 3-D system integration techniques as solutions be also increased. to these issues. For the first issue, we developed a new 3D-in- In improving inter-chip bandwidth with conventional tegrated wire-penetrating multi-layer structure. For the second system-on-a-board implementation, long inter-chip distance issue, we developed an open-skipped-inductor scheme. In the and limited number of interconnections prevent improvement following sections, we discuss these techniques and also de- in inter-chip bandwidth. Three-dimensional (3-D) integration scribe a proposed memory-access-control scheme with a pin- is recognized as a breakthrough technology for improving the point-data-capture scheme for avoiding undefined-value propa- interconnect bandwidth. It reduces the inter-chip distance and gation in stacking multi-memories using the inductive-coupling increases the number of interconnections dynamically by ver- link. tical stacking. Several 3-D interconnection techniques (wired II. 3D INTEGRATION WITH INDUCTIVE-COUPLING Manuscript received August 24, 2009; revised November 16, 2009. Current LINKS AND WIRES version published March 24, 2010. This paper was approved by Guest Editor Masayuki Mizuno. M. Saen, K. Osada, Y. Okuma, and N. Irie are with the Central Research Lab- A. System Overview oratory, Hitachi, Ltd., Kokubunji-shi, Tokyo 185-8601, Japan (e-mail: makoto. [email protected]). In this section, we explain our 3-D integrated system. In this K. Niitsu, Y. Shimazaki, Y. Sugimori, Y. Kohama, K. Kasuga, and T. Kuroda system, a full-fledged processor chip [11] and two memory are with Keio University, Yokohama, Kanagawa 223-8522, Japan. chips (SRAM0/1) are stacked, and they are connected using Y. Shimazaki, I. Nonomura, T. Hattori, and A. Hasegawa are with Renesas Technology Corporation, Kodaira-shi, Tokyo 187-8588, Japan. inductive coupling. The processor accesses stacked memories Digital Object Identifier 10.1109/JSSC.2010.2040310 via the inductive-coupling links. 0018-9200/$26.00 © 2010 IEEE Authorized licensed use limited to: Soochow University. Downloaded on March 24,2010 at 21:18:05 EDT from IEEE Xplore. Restrictions apply. SAEN et al.: 3-D SYSTEM INTEGRATION OF PROCESSOR AND MULTI-STACKED SRAMS USING INDUCTIVE-COUPLING LINK 857 Fig. 1. Block diagram of 3D-system. Fig. 3. 3D-integration with wire-penetrated multi-layer structure. on the SRAM0 chip. Each chip is back grinded to a thickness of m for a shorter link distance. The data are vertically transmitted using the inductive-coupling links among the chips. On the other hand, the power for the SRAM0 and SRAM1 chips is supplied using conventional low-cost wire bonding. Although inductive coupling can supply power, it is inferior to wire in transmission efficiency. Such 3D-integration with hybrid connections makes integra- Fig. 2. Micrographs of chips and risks of 3D-integration. tion difficult. To attain a shorter link distance, two points need to be improved. One is to reduce the space for wire bonding as much as possible while avoiding a short between the SRAM0 A block diagram of the system is shown in Fig. 1. The wire and the back-side of the SRAM1 chip (short risk A in processor chip includes eight processor-cores (PUs), a control Fig. 2), or a short between the SRAM0 wire and the edge of circuit of inductive-coupling connection (ICCP), an on-chip in- the SRAM0 chip (short risk B in Fig. 2). The other point is to terconnect (OCIC), which is a switch fabric connecting the PUs apply wire bonding to the very thin SRAM1 chip without any to the ICCP, a transmitter circuit (Txp), a receiver circuit (Rxp), cracks (crack risk in Fig. 2). To achieve this bonding, it is neces- and inductors. Each memory chip includes a 1-MB SRAM sary to fill the narrow space with glue without any gaps despite array, a control circuit of an inductive-coupling link (ICC0/1), the existence of wire bonding. To satisfy both points, we devel- a transmitter circuit (Tx0/1), a receiver circuit (Rx0/1), and oped a new structure. inductors. An overview of the new structure is shown in Fig. 3. This The inductive-coupling links are classified into an uplink structure is based on two techniques. One is a wire-shaped con- from the processor to the memories and a downlink from the trol technique for reducing the space between stacked chips memories to the processor. The links use a source-synchronous without any shorts. A key to the wire control is to place ad- method, sourcing a clock along with data. Each link contains a ditional shaping plates on the package board. By using these 600-MHz clock signal, 16-bit data signals, and control signals. shaping plates, we can change the direction of the wire and control the wire shape. The other technique is a wire-penetra- B. 3D-Integrated Wire-Penetrated Multi-Layer Structure tion-into-glue technique for filling the space without any gaps. Microphotographs of the fabricated chips are shown in Fig. 2. This is achieved by applying a special glue, Hitachi-Chemical The processor chip is fabricated in a 90-nm-CMOS process and glue (HS series), in which the wires penetrate. A 40- m-thick the memory chips are fabricated in a 60-nm-CMOS process. A space is achieved using these techniques. good feature of 3-D integration is that chips fabricated in dif- The process flow of the wire-penetration-into-glue is de- ferent processes can be integrated. scribed. First, the SRAM0 chip is glued on the processor chip A side view of 3-D integration by stacking the chips is also which is mounted on the package board. Next, wire bonding for shown in Fig. 2. The processor chip is mounted face down on a the SRAM0 is made with the shaping plates. In addition, the package board using C4 bumps. The SRAM0 chip is glued face special glue is attached to the back side of the SRAM1. Then, up on the processor chip, and the SRAM1 chip is glued face up the SRAM1 is stacked on the SRAM0 and they are heated with Authorized licensed use limited to: Soochow University. Downloaded on March 24,2010 at 21:18:05 EDT from IEEE Xplore. Restrictions apply. 858 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 TABLE I DEGRADATION OF SIGNAL STRENGTH BY UNUSED INDUCTOR a pressure. In this process, wires penetrate the glue. After that, this integrated module is cured. Finally, wire bonding for the SRAM1 is made. As described above, this process flow does not include technical difficulties, so the wire-penetration-into-glue is manufacturable.