A New Approach to Designing Electronic Systems for Operation in Extreme Environments:

Part II - The SiGe Remote Unit

T. D. England, R.M. Diestelhorst, E.W. Kenyon, J.D. Cressler, V. Ramachandran, M. Alles, R. Reed, R. Berger, R. Garbos, B. Blalock, A. Mantooth, M. Barlow, F. Dai, W. Johnson, C. Ellis, J. Holmes, C. Webber, P. McCluskey, M. Mojarradi, L. Peltz, R. Frampton & C. Eckert Author's Addresses and Affiliations will be found on page 41.

INTRODUCTION

Electronics in space vehicles face a host of challenges from their harsh operating environment. Extremely wide temperature ranges and dangerous levels of cosmic and trapped radiation can cause catastrophic damage to unprotected circuitry. Traditionally, "warm-boxes" or "electronics vaults" have provided the shielding and heating necessary to protect crucial components. Unfortunately, these solutions come with a high cost in weight, volume, power, and complexity (Figure 1). Recently, there has been a paradigm shift that advocates moving away from centralized "warm-boxes" and toward de-centralized system-on-a-chip and system-in-a-package solutions that do not require environmental control. SiGe BiCMOS technology is one of the factors driving this Fig. 1. Two JPL workers placing the radiation vault shift because it provides excellent over-temperature onto NASA's Juno spacecraft. performance, built-in Total!Ionizing Dose (TID) and The vault has titanium walls Displacement Damage (DD) radiation tolerance, and 100% and weighs about 500 pounds [1] compliance with standard Si manufacturing processes. Consequently, in 2005, NASA began the "SiGe Integrated brought together six universities, four companies, and one Electronics fo r Extreme Environments" project. They government laboratory to develop an infrastructure to demonstrate that SiGe BiCMOS (SiGe HBT + CMOS) technology was a viable candidate for implementing extreme environment electronics, particularly targeting future missions to theMoon and Mars [2]. This team used ffiM's SiGe 5AM process to create a library of circuit Author's Current Address: blocks of all types (analog, digital, and mixed-signal) Authors' Addresses and Affiliations can be found on page 41. RF, and validated them over temperature (- 180°C to + 120°C) Manuscript received December 16,2011. Review was handled by M. DeSanctis. and against both TID and Single Event Latchup (SEL) 088518985/121 $26.00 © 2012 IEEE radiation damage [3, 4].

IEEE A&E SYSTEMS MAGAZINE, JULY2012 29 Fig. 2. X-33 Space Plane Showing Fig. 3. The original BAE Remote Health Node Distributed Locations box that was the basis for the design RHN of the SiGe Remote Electronics Unit As a final proof-of-concept, the team designed and fabricated the SiGe Remote Electronics Vnit (REV), which is SiGe TECHNOLOGY FOR made up of two ASICs, the Remote Sensor Interface (RSI) EXTREME ENVIRONMENTS . and Remote Digital Control (RDC). Contained within the RSI ASIC were a total of 16 instrumentation channels of enabling force behind the shift to localized, minimally An three different types: universal, high-speed, and charge, and a shielded electronics in space-based systems is the flexibility channel, multiplexing, Wilkinson ADC. of SiGe BiCMOS technology, specifically the SiGe HBT, to 16

1----HF::.::..:=��:;;,;;:���· configuration ACe data /gain con� and control

ACe control

Sensor Channet cootrol

Configuration Channet / gain contra and AID c�u �����==�=-____���

System Controller interface

Fig. 4. Simplified block diagrams of the Remote Sensor Interface and Remote Digital Control. For the FPGA-based RDC, the ISO 11898 transceivers were implemented using external commercial parts

This will expand on our companion paper describing tolerate the extreme conditions presented by extra-terrestrial the RSI [5] by presenting a full view of the SiGe Remote environments. As the SiGe HBT approaches cryogenic Electronics Vnit (REV) and over-temperature and temperatures, the most important device metrics for circuit radiation testing results of the RSI ASIC with an design improve current gain, transconductance,/r./MAX, and FPGA-based implementation of the RDC functionality. broadband noise [6]. Instead of spending size, weight, and Specifically, this wilt present sections on SiGe technology power to keep electronic systems heated, designers can in extreme environments, the REV legacy architecture, leverage the cold capability of the SiGe HBT to improve the RDC functionality, REV system validation methods, system metrics and operate robustly at cryogenic the over-temperature experimental qualification of the temperatures. SiGe HBTs have been shown to be robust not RSI ASIC with RDC-based FPGA, the radiation only at 77 but down to 300 mK [7-10]. Because the SiGe K qualification of the same, the packaging of the dual-ASIC, HBT is so well-suited for the low temperature regime it is Multi-Chip Module (MCM) REV, mission insertion easy to falsely assume it cannot be utilized at high opportunities for the SiGe REV, and fmally, some temperatures; however, high temperature SiGe electronics are concluding remarks. presently under development. For instance, a SiGe

30 IEEE A&E SYSTEMS MAGAZINE, JULY2012 HBT-based voltage reference in [11] has been demonstrated central vehicle management and fifty RHN for operation up to 300°C. Thus, the SiGe HBT has emerged units distributed around the periphery of the X-33 to as a viable contender for ultrawide-temperature applications. gather telemetry from a wide variety of sensors, as shown in Figure 2.

Raw Samples

Sample Rate Control

ISO-11898 Interface

System Controller

Fig. 5. Flow diagram of the sampled data fr om the ADC, through the RDC, to the system controller. ® The sample rate selection determines the accumulation Fig. 6. Cadence Screen Capture filter and oversampling ratios of the Latest Version of the RDC ASIC and how samples are put into packets The RHN unit, shown in Figure 3, weighed 5 pounds, Additionally, the SiGe HBT has a natural, built-in with a volume of just over 101 cubic inches, and dissipated resistance to TID and DD radiation effects that can be 17 W of power. It accepted inputs from as many as 40 explained by aspects of the device structure. First, against sensors through several different types of processing TID, the extrinsic base of the transistor is very heavily doped. channels via a pair of large multi-pin connectors located Second, the extrinsic base is located underneathan on one end of the box. The front-end channels were oxide/nitride composite, which is known to exhibit increased comprised of discrete analog circuits assembled into hybrid radiation immunity. In addition, the volume of the SiGe HBT modules. Following digitization, the collected information is extremely small and highly doped, making it less was transmitted to the central computers via a pair of Health susceptible to DD [12]. Previous data has shown that newer Optical Buses (HOB) employing the Fiber Distributed Data generation SiGe HBT devices are hardened against major Interface (FDDI) protocol. Each supported 25 of degradations in current gain in mid- and high-injection to the RHN boxes [15]. multiple Mrad and have even higher TID tolerance at cryogenic temperatures [13]. The SiGe HBT thus shows great RSI-WITH-FPGA REMOTE ELECTRONICS UNIT promise in being the cornerstone of space electronics due to its robustness against temperature variation and tolerance to The Remote Sensor Interface (RSI) ASIC is a radiation exposure. consolidation of the three primary channel types from the box along with analog-to-digital conversion [16]. There RHN REMOTE ELECTRONICS UNIT are a total of 16 channels, organized as twelve universal channelswith selectable Wheatstone bridge configuration BAE Remote Health Node inputs supporting sensors with a data rate up to , The SiGe Remote Electronics Unit (REU) is a approximately 200 Hz, two higher data rate (up to 5 kHz) miniaturized version of the key functionality of the Remote channelswith an asymmetric bridge configuration, and two Health Node (RHN) originally developed in the 1990s for the channels that accept piezoelectric transducer inputs. Some of NASA X-33 space plane. The X-33 program was an the channels incorporate special circuitry based on high experimental spacecraftfor thereusable launch vehicle voltage transistors on theinput stages to accommodate high program. The RHN was a key component of the Integrated voltage (up to 12 V) sensors. Vehicle HealthManagement (IVHM) system [14]. In the Each of the channels is configuredfrom the digital control X-33 platform, the IVHM system consisted of a pair of section of the RED. Each channel type includes a set of

IEEE A&E SYSTEMS MAGAZINE, JULY 2012 31 serially loaded shift registers that are loaded with The CPU design is based on the 8031 configuration settings duringthe initialization process and architecture but is implemented using NULL Convention then remain static during REU operation. An additional set of Logic (NCL) [18]. Asynchronous logic of this type has the shift registers feeds data into the digital-to-analog converters advantage of being functional across many variationtypes: that are then used to calibrate the analog channels. The process, voltage rail, temperature, etc. This particularmodule configuration registers employ Radiation Hardening By has been shown previously to function down to a voltage rail Design (RHBD) techniques to minimize the possibility of of 0.36 V or temperatures down to 4 K [19], making it ideal particle-induced data corruption. Following signal for extreme environment applications. conditioning in the form of bridge configuration and gain control, the analog signals are digitized in parallel using a Functionality l2 -bit, Wilkinson architecture, Analog-to-Digital Converter The ROC follows a certain sequence of operation, divided (ADC) and then are multiplexed in the REU Digital Control into the start-up and execution phases. After power-up and (RDC) for sample averaging. reset, it goes into start-upwhere it sets up the CAN-bus interface and broadcasts a message to all other CAN-bus devices, including the system controller, to indicate its presence on the bus. The system controller then sends commands over theCAN-bus, programming the 8031 for execution and selecting values for the RSI channel settings.

Table 1. Comparison of Simulations Times for Selected RSI Blocks

Analog EDMS Factor

RC Filter 25.56 s 1.27 s 30x

6th Order 31 min. 14 s 130x Butterworth Fig. 7. Combined RDC and Filter RSI (REU Level) EDMS Model Test Bench Wilkinson 8 hr. 33 s 870x ADC The averaged data samples undergo packetization into Controller-Area Network (CAN) bus packets [17] for transmission to the central computer, a process which includes appending a time stamp. The CAN-bus replaces During execution, the ROC sends control signals to the theFDOl optical data bus employed on the original RHN RSI's channel and ADC interfaces and receives raw digital unit. Simplified block diagrams of the RSI and ROC are samples from each of the 16 channels through the ADC. shown in Figure4. Note that the ISO 11898 transceivers FSMs then process the samples on a per-channelbasis are external to theFPGA version of the ROC because (Figure 5). An accumulation filter selects which samples to they are unique circuits, but they are embedded into the save based on the accumulation ratio defined by the ASIC implementation. programmed sample rate for thatchannel. For example, a 1:8 accumulation ratio means for every eight raw samples REMOTE DIGITAL CONTROL received from a channel, one will be kept and seven will be ignored. this way, the CAN-bus is not over-crowded with In Architecture unnecessary data. The ROC is an HDL-based, CPU andFinite-State The selected raw samples converge in oversampling, Machine (FSM) driven system that reads, processes, and the next stage of the sample pipeline. Here, samples are sends the samples from theRSI chip to a central system averaged together based on a given over-sample ratio that via the CAN-bus over an ISO 11898 physical layer. is also defined by the sample rate of each channel. As a Figure 4 includes an overview of the ROC's architecture. second example, a 32: lover-sample ratio means 32 raw addition to the CPU and CAN related circuits, the ROC samples are used to produce an averaged sample. Next, an In contains register configurableFSMs for CAN-packet FSM builds theaveraged samplesinto CAN data packets building and RSI sample processing and storage elements for for eventual transmissionto the system controller. Once CPU instructions, processed samples, and configuration data ready, those packets are transmittedover the CAN-bus to for all 16 RSI channels. the system controller.

32 IEEE A&E SYSTEMS MAGAZINE, JULY 2012 REMOTE DIGITAL CONTROL ASIC • Clockingbehavior and clockingfrequencies,

A fully-functionalRD C ASIC has been designed and is • Bandwidth and delay related behaviors, currently in fabrication. A screen capture of the ASIC layout can be seen in Figure 6. As a part of its development, a • Dynamic threshold and dynamic range ® prototype was first programmed into a Xilinx FPGA on a behaviors, and test board. It offered a hardware environment for verifying the feasibility and correctness of the overall RDC • Voltage and current relationshipsfo r sensor architecture. The FPGA itself was loaded with the RDC's bridges. HDL code; however, the FPGA did not include NCL logic, so it required a Boolean logic version of the 8031 CPU. This The approach to validating the EDMS models was simple. FPGA implementation was used alongside the RSI ASIC for Analog stimuli from the channel level test benches were the over-temperature and radiation testing presented herein. "replayed" within the corresponding EDMS model test benches. Validation of each model was complete when the results matched. Any discrepancy between results was VERIFICATION OF THE eliminated by modifying the behavior of the EDMS models, REMOTE ELECTRONICS UNIT either by including additional effects or modifying effect parameters. Verification of thetwo-ASIC (RSI + RDC) REU presented significant challenges. First, each chip was Sensor input for LSC ch2 -=----��- complex in its own right. The RSI contained nearly 300,000 5.0 .------,----��-� __. analog/mixed-signaldevices and over 167,000 nodes. Full � 4.0 � '" chip analog simulation times were measured in days, not 19 3.0 � hours. Second, the REUconstituted a true 2.0 � System-in-a-Package (SiP), integrating the two largeASICs 10 � I - SlG3�Q2 1 onto a uniquely designed substrate with numerous off-chip O.Op b-----;;�-----c;;;:;;::__-,...;;::::__-_,;;;t==== O.Op SO . rn 100m 150m 200m passive components. Next, each ASIC followed a very different design flow. The RSI, being heavily analog in Packetization of LSC _ ch2 ® J.Ok ,.-----�--�--�-=----�---., circuit content, relied on schematic capture and Cadence 2.Sk ® � Spectre simulations, while the RDC, being largely digital in .� 2.0k E content, was based on RTL code and Mentor Graphics ® � 1.5k � 100 QuestaSim simulations. A creative means of implementing � 500 • dat:J -. packHlzed system level simulations accurately and efficiently was O.Op O.Op 5O.m 100m 150m 200m 250m required. sim time(s) The team used a technique called Event-Driven Mixed­ ------Signal (EDMS) modeling [20]. The basic principle of this technique was to create analog models that could be consumed by digital simulators [21]. The team created the Fig. 8. An EDMS Model Simulation of End-To-End Data Event-Driven Mixed-Signal Design and VerificationStudio, through Low-Speed Channel 2, the Wilkinson ADC, which contains libraries of EDMS effects to graphically the Remote Digital Control ASIC and assemble analog models that ran with high fidelity on a out to the system controller over the CAN-bus digital simulator. The impact of this technique on REU level verificationwas extraordinary, in that thesimulation times With EDMS replay effects, REUlevel results could be were 100X-l,000X faster than transistor level simulations. re-used as stimulus for the channel level verification Examples are shown in Table I. ® simulations in Spectre , creating a new level of observation EDMS model fidelity was a key issue, as it intentionally into RDC and RSI interactions for both the digital and analog abstractedRSI channel level behaviors from transistor-level design teams. The RDC RTL code and test bench were detail. The team identified the major channel level behaviors merged with the RSI EDMS models in an REUlevel test required to support REU level functional verification: bench. This test bench included re-confIgurable sensor loads to rigorously exercise the REU chip-set (Figure 7). • I/O and connectivity equivalence, The active sensor models provide the means for designers to evaluate the REUin a simulation of any conceivable • Supply domain sensitivity, mission profIle. The final milestone of REUlevel verification was the successfuldemonstration of sensor waveforms • Polarity of alldigital signals, control, gain, appearing as CAN packets on the ISO 11898 interface seen calibration, in Figure 8.

IEEE A&E SYSTEMS MAGAZINE, JULY 2012 33 RSI-WITH-FPGA REMOTE ELECTRONICS UNIT speed feedthroughs for transient capture [22]. Two of these WIDE TEMPERATURE TESTING ports were fitted with customized vacuum-sealedflanges, each mounted with multiple 25-pin electrical Micro-D Over-Temperature and Radiation Test Dewar subMiniature (MDM) feedthroughs. A mechanical heat switch enables control over the amount of heat transfer between the dewarlDUT and the external world. The beam port of the dewar is flangeadaptable to match that of the broad beam line at the test facility. At the Texas A&M University Cyclotron Institute, the dewar beam port was adapted with a hermetically-sealedAramica window flange similar to the one on the beamline. The RSI daughter card and the DUT mounted on it were designed such that the center of the DUT correspondedto the central axis of the beamline. All dewar measurements were carried out at a normal angle of incidence. The DUT was cooled using a custom-designed copper cold finger that was in contact with both the DUT and the dewar cryogen vessel. Temperature sensors were placed on the cold finger andthe dewar vessel to monitor the respective temperatures simultaneously through an external Lakeshore 331S temperature controller. The controller was used to Fig. 9. The Over-Temperature Experimental Set-Up. regulate the heat applied to the system through a 50 W heater The dewar is connected to the vacuum pump attached to the dewar vessel, and thus facilitate single-event located on the left. The two MDM flanges are testing over temperature. on the right side of the dewar connecting to the in the right fo reground TEST BOARD DESIGN

Test board design for the RSI was constrained primarily by the radiation test dewar. A two-board solution was chosen with thegoal of keeping the maximum amount of the supporting commercial circuitry at room temperature. The in-dewar daughter card held the RSI andFPGA-based RDC. Outside the dewar, the motherboard contained all the and interface circuitry.

DAUGHTER CARD

The internalvolume of the test dewar and availability of low thermallyconductive, cryogenic ribbon cable drove the design process of the daughter card. Using nearly

all the available space, the board was 4. 25" x 4.00" and consisted of the RSI in a 256-pin grid array package, a ® ® Fig. 10. The RSI-with-FPGA REU In-Dewar Xilinx Spartan 3£ 1200 FPGA, three MDM cable headers Daughter Card. The dewar cold finger comes up for the primary cabling, a 3 x 12 grid of pin headers for through a hole in the middle of the board optional diagnostic signals, multiple sets of power rail and makes contact with the back side decoupling , necessary off-chip passives for the of the PGA package containing the RSI ASIC charge channels and the ADC, andoptional fixed at the inputs of the high-speed and universal channels, as seen A cryogenic dewar customized for single-event testing in Figure 10. [22] was used for c'arrying out theexperiments-reported While in the dewar, a limited number of conductors could herein, and it appears in the center of Figure9. The dewar be used between the daughter card and outside world because can be used with LN2 (boiling point -196°C) or LHe (boiling each one created a thermalshunt from the RSI, limiting the point -269°C) as cryogens, depending upon the lowest testing temperature range. Unfortunately, the temperature desired. Six hermetically-sealedports on the thermally-resistivecryogenic conductors also had a series dewar provide ample choice for a variety of electrical electrical resistance of approximately 50 so one of the n, connection configurations, such as hermetic 61-pin three cables had to be a thermally-conductive copper cable connectors for dc measurements or customized hermetic high for rail current handling. The low conductor count also meant

34 IEEE A&E SYSTEMS MAGAZINE, JULY2012 n) f1RL Resolution = (LSB f1LSBs (1) The charge channel required special consideration because precisely controlling the charge at the input node was very difficult. Instead, a sine current source was used at the input to precisely control the change in charge over time, .1Q. Taking advantage of the integral relationship between current and charge in Equation (2) and analyzing theAD C output made the calculation of Equation (3) possible.

1 A = = flQ f2! Acos(2TCft)dt -fTC o (2) Fig. 11. The RSI-with-FPGA Remote Electronics Unit

Motherboard. It was 8.6" x 7.0", and provided aU power rail and interface handling for the REU, = including five voltage regulation circuits, Resolution CiB) f1�iB (3) two ISO 11898 transceivers, and nearly 100 separate conductors to the REU Next, noise analysis information was needed. Grounding the inputs of each channel constituted an invalid state, so that only half of the16 channels were accessible for testing, another approach was required. The best strategy was to but at least two of each type were represented. create a standard DC outputon each channel and take a . During over-temperature measurements, the three internal transient measurement. For the universal and high-speed MDM cables connected from the daughter card to dewar channels, a balanced 350 Wheatstone bridge was n flanges and on the outside, another set of copper MDM connected to the input, ensuring the measured differential cables connected to the motherboard. Shorting jumperswere voltage was zero, and resulting in 600 mY at the output. For used on the100 mil daughter card headers to set theoptional the charge channel a built-in ability to short internalfeedback test signals to predefmed DC values. When out of dewar, the was used to produce a DC voltage on the output. threeMDM cables connected directly to the motherboard, Approximately five seconds worth of ADC samples were and a 26-pin ribbon cable made the diagnostic signals saved per measurement in these states. available for use on the motherboard. The standard deviation of the set of samples was taken as the AC-coupled measurement of RMS noise in units of LSBs MOTHERBOARD because the standard deviation of a set of values is equivalent to the RMS about themean of the set. Sensitivity was then The motherboard contained all of the power management defmed as the input referred noise floor of each channel. By and interface circuitry. Five differentprogr ammable voltage multiplying the values of resolution and noise, the equivalent regulators, each with sets of decoupling capacitors, ensured a output noise source can be referred back to the measured unit clean voltage supply to the daughter card. Commercial ISO in RMS, as indicated in Equations (4) and (5). 11898 transceivers were used for CAN-bus communication. Pin headers were used with a USB JTAG adapter to program theFPGA. DIP switch arrays made it possible to present (n) = Noise (LSBs) x Res. variousWheatstone bridge configurationsand load Sen. (4) resistances to the universal and high-speed channels. CA�B)

MEASUREMENT METHODS (Q) = x Sen. Noise (LSBs) Res. (5) The main measurement objective was a quantification of (LiB) resolution, noise level, and system sensitivity over RESOLUTION, NOISE temperature. Resolution was defmed as the amount of change AND SENSITIVITY RESULTS of themeasured element per Least SignificantBit (LSB) of the ADC. the case of the universal and high-speed The methods discussedin theprevious sub-section were In channels the element was resistance, and thus the resolution performed for multiple gain states during over-temperature can be expressed as in Equation (1). The ADC output was testing from 100 K to 343 K. The results of resolution saved versus fivedifferent values of the input , anda measurements areshown in Figures 12-14. Two major linear regression fitwas used to derive the resolution. characteristics are evident. The gain is remarkably flat,

IEEEA&E SYSTEMS MAGAZINE, JULY 2012 35 _80,------..." m Universal Channel -0- 1.33 VN Ga in 0.8,------, en m- Charge Channel -0- 10 VN Gain ...J -O- S VN Gain en -0-SOVN Gain 350 n Full Bridge -+-20 VN Gain ...J a 60 00.6 E Q. r:: -o -r:: .. 40 o ::] .. 0.4 o o::] III III Q) Q) a: 20 II: 0.2 Q) ~"'O-----4~--a-----t:l---aa Q) r:: a a r:: o o o o o o r:: ~ 0 o o o o r:: ~ 0 ~ 0 (J (J 100 150 200 250 300 350 100 150 200 250 300 350 Temperature (K) Temperature (K)

Fig. 12. The Universal Channel Resolution Fig. 14. The Charge Channel Resolution remained tighter than 60 mnILSB throughout remained tighter than 6 pC/LSB throughout the entire temperature range in the lowest gain state the entire temperature range in the lowest gain state and 5 mnlLSB in the highest gain state and 1.2 pC/LSB in the highest gain state

60,---~------....." 9 Universal Channel -0- 1.33 VN Gain 0.6 m- High-Speed Channel -0- 1 VN Gain en 350 n Full Bridge -o-S VN Gain ...J 50 -O-S VN Gain 350 n Full Bridge -+-10 VIV Gain en 6 -+- 20 VN Gain 0.5 a- a m .§. 40 3 - ...Jen 0.4~ r:: ~O--~~)""--0-----0-_-0o > -Q) 2 30 ...~ .!!! 0 0.3 ::] o g 20 z enQ) Q) en -3 0.2 en II: Q) 10 == II: - 6 0.1 II:== r:: o ; 0 o o .r:: -9 o (J -10.....------' 100 lS0 200 2S0 300 3S0 100 150 200 250 300 350 Temperature (K) Temperature (K)

Fig. 13. The High Speed Channel Resolution Fig. 15. The Universal Channel noise was the lowest remained tighter than 40 mnILSB throughout of all three channels and remained below 6 LSBs RMS the entire temperature range in the lowest gain state across the full temperature range. The sensitivity was and 4 mnILSB in the highest gain state better than 300 mQ RMS in all cases and better than 25 mQ RMS in the highes gain state showing little dependence on temperature over an almost 250°C temperature spread. In addition, the resolution resulting sensitivity can be seen in Figures 15-17. Except is very tight. In the case ofthe universal and high-speed for occasionally falling offat the top and bottom ends channels in the highest gain states, an LSB represents ofthe temperature range, the noise levels stay fairly less than 10 mQ. Even in the lowest gain, an LSB is uniform for each gain state and falls far below the full less than 60 mQ. For the charge channel in the high scale range of4096 LSBs. The universal channel had gain state, the resolution is approximately 0.1 pC per the best noise performance, staying below 6 LSBs over LSB, and it stays below 0.6 pC per LSB in the low gain the entire temperature range. The high-speed and charge state. channels were consistently below 30 LSBs . A 6 and 30 Along with resolution, channel noise was measured LSB noise floor would result in a single, full-scale tone over the same temperature range . The noise data and the Signal-to-Noise Ratio (SNR) of47 and 33 dB, respectively.

36 IEEE A&E SYSTEMS MAGAZINE, JULY 2012 40 ------_0.6 150 -0-1 VN Gain T High-Speed Channel V G - All Channel Types ... 30 350 n Full Bridge 0.5 1/1 I :::::�O �N ���n m Highest and Lowest Gain States I - en 120 I (f) a ....I 90 K to 300 K I m 20 0.4 ;: - en - I ....I - Q)> 90 I .s; G) G) 10 0.3� ....I (f) (f) I '0 r::: G) G) 1/1 60 Z 0 0.2 en '0 en en z T :E en a: -10 0.1 :Ea: 30 a::E

-20 o 0 .5 100 150 200 250 300 350 LET (MeV.cm2/mg) Temperature (K)

Fig. 18. A Box and Whisker Plot Showing the Fig. 16. High Speed Channel Noise Remained Below Measured Noise Levels Across All Temperature and 30 LSBs RMS across the Full Temperature Range and Channel Types for the Highest and Lowest Gain States. below 10 LSBs RMS in the highest and lowest gain states. While the data is variable, the overall trends The sensitivity was better than 220 mn RMS in all cases of higher noise at higher LETs and the jump and better than 30 mn RMS in the highest gain state between the 40 Ar and ions is apparent 84Kr

40�------__,30 REMOTE SENSOR INTERFACE -0-10 VN Gain Charge Channel IN RADIATION ENVIRONMENT 50 VIV Gain -+- 30 25_ - o 1/1 c. The RSI was subjected to TID exposure at Vanderbilt m - en 20 20� University and SEE testing over temperature at the Cyclotron ....I - Institute at Texas A&M University. A TID exposure of 100 .s;:;:::; krad revealed no observable degradation in the RSI � 10 15 'iiic operation. Noise values and supply currents were not Z'0 G) en noticeably altered between pre- and post-exposure. en 0 10 en :E a: :E 50/50 In/Pb Lid Seal -10 5 a:

-201 �------��0 100 150 200 250 300 350 Temperature (K)

Fig. 17. Charge Channel Noise Remained below 30 LSBs RMS across the Full Temperature Range. The sensitivity was better than 15 pC RMS in all cases and better than 3 pC RMS in the highest gain state In /Substrate Attach Polyimide Package Pin

Sensitivity was calculated from theproduct of the noise and resolution. It represents the input-referred noise source Fig. 19. Drawing of the Objects and Materials andcan be interpret d as themeasurement noise floor of the Used in the MCM � ' channel. Even in the lowest gain states, it stays below 0. 25 n across the 243 K temperature range. the higher gain states, OVER-TEMPERATURE SET In it improves to below 50 meaning that this REU ANALOG NOISE QUANTIZATION ron, implementationcan reliably detect any change above 50 mn resistance at any temperature between 100 and 343 K. For in To quantify the effectsof Single Event Transients (SETs) thecharge channel, sensitivity stays better than 15 pC and 5 on the RSI, the same noise measurements from the original pC in the low andhigh gain states, respectively. over-temperature characterization were performed while the

IEEE A&E SYSTEMS MAGAZINE, JULY 2012 37 Table 2. Comparison of CTE for Selected Packaging Materials

Si (SiGe Die) AIN

CTE 2.8 ppml°C 4.5 ppml°C 6.7 ppml°C

RSI was being subjected to broad beam irradiation using a variety of heavy ions and exposure temperatures. The test set-up utilized the radiation dewar described in the previous section. The RSI was exposed from 85 K to 293 K. The heavy ions used were 2�e, Ar, and J29Xe. After 40 84Kr, factoring in the energy losses in air and through the Aramica windows using TRIM [23], the resulting surface Linear Energy Transfer (LET) values were 2.5, 8.3, 29, and 57 MeV-cm2/mg, respectively. We observed an overall trend of higher noise level with increasing LET, as shown in Figure 18. The effect was observable at lower LETs, but became more significant with LETs above 20 MeV-cm2/mg. Fig. 20. Layout Capture of the Top (signal) Layer of the MCM Substrate Showing the Signal Paths HIGH TEMPERATURE SEL EXPERIMENT Between the Chips and to the Outside of the Package

The worst-case Single Event Latchup (SEL) conditions for Readiness Level (TRL) and was costly for our low volume the RSI were a non-zero angle of ion incidence at high work. Metal packages were commercially-available but had temperature under the highest LET ion possible. The RSI was an unacceptably mismatched CTE with Si. AIN would have exposed at 125°C to a fluence of 1.0 x 107 ions/cm2 of 129Xe provided a desirable CTE, but custom AIN packages were ions at three different angles of incidence: 00, 30° and 45° unavailable. In the end, a ceramic, Ah03 package was

(LET = 47.3 MeV-cm2/mg at 0°). Currents were monitored in selected as a median trade-off between cost, CTE, and real-time with an Agilent® 6624A four-channel power supply availability. set to detect any rise above critical limits. Throughout the The interconnect substrate technology was multilayer thin test, no latchup was observed; supply currents stayed within film copper and polyimide deposited and patterned on a base safe tolerance, and throughout all radiation experiments substrate [24] (see Figure 19). The polyimide was HD (TID, SET Noise, and SEL) no catastrophic failures ever Microsystems PI-2611. Electroplated Cu was selected for its occurred, indicating that the RSI is SEL immune, as intended. electrical conductivity and elongation. The AIN substrate provided an intermediate CTE between the Si die and the REV MULTI-CHIP MODULE PACKAGING Ab03 package (see Table 2). A novel indium-based metallurgy was used as both the die A Multi-Chip Module (MCM) packaging approach was and substrate attachment material. Indium remains malleable selected for the final SiGe REV dual-ASIC implementation. to cryogenic temperatures and helped relieve the strain The MCM methodology eliminates the need for PCB between the substrate and package. Thermosonic Au wire interconnects between the individual die (an interface failure bonding was used for die to substrate and substrate to opportunity) and also reduces the size and weight of the package electrical interconnection because it has better system implementation. fatigue resistance than Al wire. A metallized Ah03 lid was With an approximately 300°C operating temperature range solder sealed with 50/50 InIPb solder to provide a hermetic for lunar applications, the packaging design philosophy was package. to match the Coefficient of Thermal Expansion'(CTE) of the packaging materials wherever possible. The stress on an REU MCM SUBSTRATE LAYOUT interface is directly proportional to the differencein CTE between the materials and the change in temperature during thermal excursions. The MCM net list was determined by the connections The team considered multiple package material options: required between the analog and digital chips, the required ShN4, metal (Kovar� and ceramic (AlN and Ab03). ShN4 package I/O, connections to the passive components, and had a matched CTE with Si, but it had a low Technology power nets. In addition to the die, the package included

38 IEEE A&E SYSTEMS MAGAZINE, JULY 2012 passive components and a quartz oscillator for in-package clock generation. The substrate dimensions were determined by the cavity size of the Ah03 quad flat package and were

36.58 mm x 36.58 mm, which gave a clearance of 0.5 mm to the inside edge of the package cavity. After reviewing the net and component lists, the team decided that only a single signal layer was required and that two split planes would be included to provide low impedance power distribution. The power and ground planes were split to provide the different voltages (and return paths) required by the two SiGe die and came with the advantage of adding decoupling capacitance where they overlapped. The top (signal) layer is shown in Figure 20. The signals routed easily without crossovers or an extra metal layer due to the careful design of thetwo ASICs such that all chip interconnects could be directly connected, all package level IIOs could be routed straight to the outside, and all rail signals could be directly attached to the power and ground Fig. 21. A Photograph of an Assembled MCM REU planes. Carefulattention was also given to those planes, Attached to a PCB with the Lid Removed. The insuringthat they could be generated as solid blocks without left die is a previous RDCASIC version and the right die any extensions or extra routing. is the RSI. The in-package oscillator is in the lower left Each of the layers was separated by a 6.5 �m thick, low stress polyiroide with etched vias for interconnection. The of the Titan mission including the applicability and value of final populated and board-attached package is shown in SiGe technology to this program [25]. Figure 21. Some of the near-term opportunities for infusion of SiGe technology include:

INSERTION OPPORTUNITIES • Lunar Geophysical Network (several small landers throughout the lunar surface), The REU and underlying SiGe extreme temperature circuit library and technology developed during this work have numerous opportunities for insertion into spaceflight • Lunar South Pole-Aitken Basin Sample Return missions. While the ability of the SiGe REU to address (lander to explore surfacefloor of dark polar specific mission requirements will be based on individual craters fo r ice), needs, the desire for small Size, Weight and Power (SWaP) is almost universal, particularly in the area of spacecraft health • Mars Sample Return mission, monitoring functions. In addition, the ability to support operation outside of a controlled environment makes • Jupiter Europa Orbiter, and placement of theREUs on spacecraft far more flexible than existing solutions. • Trojan Tour and Rendezvous. The SiGe REU will be at home in planetary operations, such as in the series of robotic rovers currently used to SUMMARY explore theMartian landscape. Again, in this case the combination of small size, low weight, and low power We have presented the architecture, simulation, dissipation is highly desirable, and the additional gain in packaging, and over-temperature and radiation testing of a efficiency achieved by eliminating the need for the "warm complex, 16-channel, extreme environment capable, SiGe box" will allow for additional allocation to scientific Remote Electronics Unit containing the Remote Sensor equipment. As a result, the next generation of Mars rovers Interface ASIC that can serve a wide variety of would be an obvious insertion opportunity for SiGe extreme space-relevant needs as designed. These include future environment technology. This technology can be used not missions to the Moon and Mars, with the additional potential only for the REU, but also for other functions,'such as to operate in otherhostile environments, including lunar communications, with additions to the existing circuit library. craters and around the Jovian moon, Europa. We have SiGe technology will be equally at home on deep space expanded on the previous introduction of the RSI to show the exploration missions, such as the proposed flagship mission validity of the chip design and performance over an almost to Europa where support for cryogenic temperatures and 250 K temperature range, down to 100 K, under 100 krad radiation tolerance will be of critical importance. The Keck TID radiation exposure, with SEL immunity and operability study commissioned during 2010 explored the requirements in a high-flux SET environment.

IEEE A&E SYSTEMS MAGAZINE, JULY 2012 39 We have successfully demonstrated that a DC Design Considerations, 40, 525-541, 1993. commercially-available SiGe BiCMOS technology platform IEEE Trans. on Electron Devices, Vol. pp. can be used to support extremeenvironment electronics needs without costly, centralized "warm-boxes"and [8] J.D. Cressler, E.F. Crabbe, J.H. Comfort, J.M.C. Stork and J.Y.C. Sun, On the Profile Design and Optimization of Epitaxial Si- and "electronics vaults, " opening the possibility of dramatic SiGe-Base Bipolar Technology for 77 K Applications. II. Circuit improvements spacecraftsize, weight, and power. The in performance issues, SiGe has set the foundation for a fundamentalchange IEEE Trans. on Electron Devices, Vol. 40, pp. 542-556, 1993. REV in theway extreme environment systems are architected.

[9] AJ. Joseph, J.D. Cressler and D.M. Richey, ACKNOWLEDGMENT Operation of SiGe Heterojunction Bipolar Transistors in the Liquid-Helium Temperature Regime, 16, 268-270, 1995. This work was supported by NASA ETDP under Contract IEEE Electron DeviceLetters, Vol. pp. NNL06AA29C. We are grateful for thesupport of A. Keys, [10] M. Watson, D. Frazier, M. Beatty, D. Hope andC. Moore of L. Najafizadeh, J.S. Adams, S.D. Phillips, K.A. Moen, J.D. Cressler, S. Aslam, T.R. Stevenson and R.M. Meloy, NASA, E. Kolawa of JPL, and A. Joseph, T. Lamothe, and Sub- I-K Operation of SiGe Transistors and Circuits, themM SiGe development team. IEEE Electron Device Letters, Vol. 30, pp. 508-510, 2009.

REFERENCES [II] D.B. Thomas, L. Najafizadeh, J.D. Cressler, K.A. Moen and N. Lourenco, Optimization of SiGe bandgap-based circuits for up to [I] NASNJPL-CaltecblLMSS, 300 °c operation, Setting up Juno 's Radiation Vault, ed, 2010. Solid-State Electronics, Vol. 56, p. 9, 2010.

[12] J.D. Cressler and G. Niu, [2] A.S. Keys, J.H. Adams, M.C. Patrick, M.A. Johnson and J.D. Cressler, Silicon-Germanium Heterojunction Bipolar Transistors, A review of NASA's Radiation-Hardened Electronics for Space Boston, MA: Artech House, 2003. Environments Project, in 2008Sp ace Conf, San Diego, CA, United States, 2008. [13] A.P.G. Prakash, A.K. Sutton, R.M. Diestelhorst, G. Espinel, J. Andrews, B. Jun, J.D. Cressler, P.W. Marshall and CJ. Marshall, [3] R.M. Diestelhorst, S. Finn, L. Najafizadeh, M. Desheng, X. Pengfei, The Effects ofIrradiation Temperature on the Proton Response C. Ulaganathan, J.D. Cressler, B. Blalock, F. Dai, A. Mantooth, ofSiGe HBTs, L. Del Castillo, M. Mojarradi and R. Berger, IEEE Trans. on Nu clear Science, A monolithic, wide-temperature, charge amplification channel Vol. 53, pp. 3175-3181, 2006. for extreme environments, inIEEE Aerospace Conf, 2010, pp. 1-10. [14] R. Garbos and W. Mouyos, X-33/RLV System Health Management/Vehicle Health [4] C. Ulaganathan, N. Nambiar, B. Prothro, R. Greenwell, S. Chen, Management, BJ. Blalock, C.L. Britton, M.N. Ericson, H. Hoang, R. Broughton, in Proc. of the 1998 39th AIAAIASMEIA SCEIAHSIASC K. Cornett, G. Fu, H.A. Mantooth, J.D. Cressler and R.W. Berger, Structures, StructuralDynamics, and Ma terials Confand A SiGe BiCMOS instrumentation channel for extreme environment Exhibit and AIAAlASMEIA HS Adaptive Structures Forum, applications, Long Beach, CA, USA, 1998, pp. 1857-1864. inMidwest Sy mp. on Circuits and Sys tems, 2008, pp. 217-220.

[15] R. Garbos-Sanders, L. Melvin, B. Childers and B. Jambor, [5] R.M. Diestelhorst, T. England, R. Berger, R. Garbos, C. Ulaganathan, System health management/vehicle health management for future B. Blalock, K. Cornett, A. Mantooth, X. Geng, F. Dai, w. Johnson, manned space systems, J. Holmes, M. Alles, R. Reed, P. McCluskey, M. Moj arradi, L. Peltz, in AIAAIIEEE Digital Avionics Sy stems Conj., R. Frampton, C. Eckert and J.D. Cressler, 1997, pp. 8.5-8-8.5-17. A New Approach to Designing Electronic Systems for Operation in Extreme Environments: Part I - The SiGe Remote Sensor Interface, [16] R. Berger, R. Garbos, J. Cressler, M. Mojarradi, L. Peltz, B. Blalock, IEEE Aerospace and Electronic Systems Magazine, in press. W. Johnson, N. Guofu, F. Dai, A. Mantooth, J. Holmes, M. Alles and P. McClusky, Miniaturized Data Acquisition System for Extreme Temperature [6] J.D. Cressler, Environments, Silicon-Gennanium as an Enabling Technology fo r Extreme in IEEE Aerospace Conf, 2008, pp. 1-12. Environment Electronics, IEEE Trans. on Device and Ma terials Reliability, Vol. 10, pp. 437-448, 2010. [17] CAN Specification 2.0, ed. Stuttgart: Robert Bosch GmbH, 1991, p. 70.

[7] J.D. Cressler, J.H. Comfort, E.F. Crabbe, G.L. Patton, J.M.C. Stork, J.Y.C. Sun and B.S. Meyerson, [18] K. Meekins, D. Ferguson and M. Basta, On the Profile Design and Optimization of Epitaxial Si- and Delay insensitive NCL reconfigurahle logic, SiGe-Base Bipolar Technology for 77 K Applications. I. Transistor in IEEE Aerospace Conf, 2002, pp. 4-1961-4-1966, Vol. 4.

40 IEEE A&E SYSTEMS MAGAZINE, JULY 2012 [19] B. Hollosi, M. Barlow, F.. Guoyuan, C. Lee, D. Jia, S.C. Smith, [25] J.R. Greer, J.M. Jackson, J.I. Lunine and M.M. Moj arradi, H.A. Mantoothand M. Schupbach, (201 1), Future Missions to Titan: Scientific and Engineering Delay-insensitive asynchronous ALU for cryogenic temperature Challenges. environments, inMidwest Sy mp. on Circuits and Systems , 2008, pp. 322-325.

[20] C. Webber, J. Holmes, M. Francis, R. Berger, A. Mantooth, Author AfI'illations and Addresses: A. Arthurs, K. Cornett and J.D. Cressler, T.D. England, R. M. Diestelhorst, E. W. Kenyon and J. D. Cressler are Event driven mixed signal modelingtechniques for with the Georgia Instituteof Technology, School of Electrical and Computer System-in-Package functional verification, Engineering, 777 Atlantic Drive NW, Atlanta, GA 30332 USA; inIEEE Aerospace Conj., 2010, pp. 1-16. V. Ramachandran, M. Alles and R. Reed with Vanderbilt University, are Department of Electrical Engineering and Computer Science, VU Station B #35 1 824, 2301 Vanderbilt Place, Nashville, TN 37235, USA; [21] R.E. Harrand A.G. Stanculescu, R. Berger and R. Garbos with BAB Systems, 9300 Wellington Road, App lications of VHDL to circuit design. 201 1 0 are Boston: Kluwer Academic, 1991. Manassas, VA, USA; B. Blalock is with the University of Tennessee, Department of Electrical Engineering and Computer Science, 1508 Middle Drive, Knoxville, [22] V. Ramac M.J. Gadlage, J.R. Ahlbin, M.L. Alles, R.A. Reed, 37996 handran, TN USA; B.L. Bhuva, L.W. Massengill, J.D. Black and C.N. Foster, A. Mantooth and M. Barlow arewith the University of Arkansas, Department Application of a novel test system to characterize single-event of Electrical Engineering, 3217 Bell Engineering Center, Fayetteville, transients at cryogenic temperatures, AR 72701 USA; 2009, 1-2. in Int. SemiconductorDevice Research Symp. , pp. F. Dai, W. Johnson and C. Ellis with Auburn University, Departmentof are Electrical andComputer Engineering, 200 Broun Hall, AuburnUniversity, [23] J.F. Ziegler and J.P. Biersack, AL 36849 USA;

- J. Holmes and C. Webber with Lynguent, Inc., 700 W Research Center Srim theStopp ing and Range of Ions in Ma tter. are Ziegler Scientific Company, 2008. Boulevard, Suite 1207, Fayetteville, AR 72701 USA; P. McCluskey is with theUniversity of Maryland, Department of Mechanical Engineering, 2181 Glenn L. Martin Hall, Building 088, College Park, MD [24] S. Sivaswamy, W. Rui, C. Ellis, M. Palmer, R.W. Johnson, 20742 USA; P. McCluskey and K. Petran:a, M. Mojarradi is with Jet Propulsion Laboratory, 4800 OakGrove Drive, System-in-package fo r extreme environments, Pasadena, CA 91109 USA; inElectronic Components and Te chnology Con!. 2008, L. Peltz and R. Frampton withBoeing Phantom Works, P.O. Box 2515, pp. 2044-2050. are Seal Beach, CA 90740 USA; and C. Eckert is with the Georgia Tech Research Institute, 925 Dalney Street, Atlanta, GA 30332 USA. .4

IEEE A&E SYSTEMS MAGAZINE, JULY 2012 41