Chapter 3 : ULSI Manufacturing Technology - (c) Photolithography

2005 SOC設計概論 中山電機系 黃義佑 1 Reference

1. Semiconductor Manufacturing Technology : Michael Quirk and Julian Serda (2001) 2. 國家矽導計畫-教育部晶片法商學程教材 (2004) 3. Semiconductor Physics and Devices- Basic Principles(3/e) : Donald A. Neamen (2003) 4. Semiconductor Devices - Physics and Technology (2/e) : S. M. Sze (2002) 5. ULSI Technology : C. Y. Chang, S. M. Sze (1996)

2005 SOC設計概論 中山電機系 黃義佑 2 Photolithography

Wafer fabrication (front-end)

Wafer start Thin Films Polish

Unpatterned wafer

Completed wafer Diffusion Photo Etch

Test/Sort Implant

2005 SOC設計概論 中山電機系 黃義佑 Wafer Fabrication Process Flow 3 Photolithography Concepts

Line width Space

1:1 Mask 4:1 Reticle Photoresist

Thickness

Substrate

1. Photomask and 2. Three Dimensional Pattern in Reticle for Photoresist Microlithography (CD:critical dimension)

2005 SOC設計概論 中山電機系 黃義佑 4 Photolithography Concepts 3. Light Spectrum & Resolution (a) Section of the Electromagnetic Spectrum

Visible

Micro- Gamma rays X-rays UV Infrared waves Radio waves

f (Hz) 1022 1020 1018 1016 1014 1012 1010 10 8 10 6 10 4

(m) λ 10-14 10-12 10-10 10-8 10-6 10-4 10-2 10 0 10 2 10 4

157 193 248 365 405 436 λ (nm) VUV DUV DUV i h g 2005 SOC設計概Common論 UV wavelengths used in optical lithography. 中山電機系 黃義佑 5 Photolithography Concepts 3. Light Spectrum & Resolution (b) Important Wavelengths for Photolithography Exposure

UV Wavelength Wavelength UV Emission Source (nm) Name 436 g-line Mercury arc lamp 405 h-line Mercury arc lamp 365 i-line Mercury arc lamp Mercury arc lamp or 248 Deep UV (DUV) Krypton Fluoride (KrF) excimer laser 193 Deep UV (DUV) Argon Fluoride (ArF) excimer laser

157 Vacuum UV (VUV) Fluorine (F2) excimer laser

2005 SOC設計概論 中山電機系 黃義佑 6 Photolithography Concepts 4. Importance of Mask Overlay Accuracy

Top view of CMOS inverter The masking layers determine the accuracy by which subsequent processes can be performed.

Different types overlay misalignment affect the overlay budget. Misalignment is caused by poor alignment between the mask and the wafer.

The photoresist mask pattern prepares individual layers for proper placement, orientation, and size of structures to be etched or implanted. A large overlay budget essentially reduces the circuit density, which limits device PMOSFET NMOSFET feature sizes and, therefore, IC performance.

Small sizes2005 and lowSOC tolerances設計概論 do not provide much room中山電機系 for error. 黃義佑 Cross section of CMOS inverter 7 Photolithography Concepts 5. Photolithography Processes (a) Negative Lithography

Areas exposed to light become crosslinked and resist the UltravioUltravioletlet lightlight developer chemical. Chrome island Island on glass mask Exposed area of photoresist Window Photoresist Shadow on photoresist

PhotoresistPhotoresist OxideOxide OxideOxide SiliconSilicon ssubstrateubstrate SiliconSilicon ssubstrateubstrate Resulting pattern after the resist is developed. 2005 SOC設計概論 中山電機系 黃義佑 8 Photolithography Concepts 5. Photolithography Processes (b) Positive Lithography

UltravioUltravioletlet lightlight Areas exposed to light are Chrome island Shadow on dissolved. on glass mask photoresist Island Window

Photoresistphotoresist Exposed area of photoresist PhotoresistPhotoresistphotoresist OxideOxideoxide OxideOxideoxide SiliconSiliconsilicon ss ubstrateubstratesubstrate SiliconSiliconsilicon sssubstrateubstrateubstrate Resulting pattern after the resist is developed. 2005 SOC設計概論 中山電機系 黃義佑 9 Relationship Between Mask and Resist

Desired photoresist structure Island of photoresist to be printed on wafer Substrate

Chrome Quartz

Window Island

Mask pattern required when Mask pattern required when using negative photoresist using positive photoresist 2005 SOC設計概(opposite論 of intended structure) (same as intended structure) 中山電機系 黃義佑 10 Clear Field and Dark Field Masks

Clear Field Mask Dark Field Mask

Simulation of metal interconnect lines Simulation of contact holes (positive resist lithography) (positive resist lithography) 2005 SOC設計概論 中山電機系 黃義佑 11 Eight Steps of Photolithography

UV Light

Resist HMDS λ Mask

λ

1) Vapor prime 2) Spin coat 3) Soft bake 4) Alignment and Exposure

5) Post-exposure 6) Develop 7) Hard bake 8) Develop inspect bake 2005 SOC設計概論 中山電機系 黃義佑 12 Automated Wafer Track for Photolithography

Wafer stepper (Alignment/Exposure system) Vapor Resist Develop Edge-bead Load station prime coat and rinse removal Transfer station

Wafer Transfer System

Soft bake Cool plate Cool plate Hard bake

Photo courtesy of Advanced Micro Devices, TEL Track Mark VIII

2005 SOC設計概論 中山電機系 黃義佑 13 1. Vapor Prime

Resist liftoff Puddle Spin wafer to formation remove excess liquid

Effect of Poor Resist Adhesion HMDS Puddle Dispense and Spin Due to Surface Contamination

Promotes Good Photoresist-to-Wafer Chamber cover Adhesion Primes Wafer with Hexamethyldisilazane, HMDS Wafer Followed by Dehydration Bake Hot plate Ensures Wafer Surface is Clean and Dry Exhaust 2005 SOC設計概論 HMDS Hot Plate Dehydration Bake and Vapor Prime 中山電機系 黃義佑 14 2. Spin Coat

1) Resist 2) Spin-up 3) Spin-off 4) Solvent dispense evaporation

Process Summary: Photoresist Wafer is held onto vacuum chuck dispenser Dispense ~5ml of photoresist Slow spin ~ 500 rpm Ramp up to ~ 3000 to 5000 rpm Quality measures: time speed thickness Vacuum chuck uniformity 2005 SOC設計概論 particles and defects To vacuum Spindle connected to 中山電機系 黃義佑 pump spin motor 15 3. Soft bake

Chamber cover Characteristics of Soft Bake: • Improves Photoresist-to-Wafer Adhesion • Promotes Resist Uniformity on Wafer • Improves Line width Control During Etch Wafer • Drives Off Most of Solvent in Photoresist • Typical Bake Temperatures are 90 to 100°C – For About 30 Seconds – On a Hot Plate Hot plate – Followed by Cooling Step on Cold Plate Solvent exhaust Soft Bake on Vacuum Hot Plate

2005 SOC設計概論 中山電機系 黃義佑 16 4. Alignment and Exposure

Reticle Pattern Transfer to Resist

UV light source

Shutter Alignment laser

Shutter is closed during focus and alignment and Reticle (may contain one or removed during wafer exposure more die in the reticle field)

Projection lens (reduces the size of reticle field for presentation to the wafer Single field exposure, includes: surface) focus, align, expose, step, and repeat process Wafer stage controls position of wafer in 2005 SOC設計概論 X, Y, Z, θ) 中山電機系 黃義佑 17 Layout and Dimensions of Reticle Patterns

Resulting layers 5 6

4

3

2 7

1) STI etch 2) P-well implant 3) N-well implant 4) Poly gate etch 8 1

Top view

5) N+ S/D implant 6) P+ S/D implant 7) Oxide contact etch 8) Metal etch

2005 SOC設計概論 Cross中山電機系 section 黃義佑 18 Optics- Resolution of Features

k = process factor that represents specific applications (0.6~0.8) NA = numerical aperture of the exposure system

Calculating Resolution 0.1 for a given λ, NA and k 0.25 0.5 k = 0.6

1.0 Illuminator, λ The dimensions of linewidths and spaces must be equal. As feature sizes decrease, it is more difficult to Mask 2.0 separate features from each other. k λ R = λ ΝΑ R Lens, NA NA 365 nm 0.45 486 nm i-line 365 nm 0.60 365 nm 193 nm 0.45 257 nm R DUV Wafer 2005 SOC設計概論 193 nm 0.60 193 nm 中山電機系 黃義佑 19 Optics - Depth of Focus (DOF)

Illuminator, λ

λ ΝΑ R DOF 365 nm 0.45 486 nm 901 nm Mask i-line 365 nm 0.60 365 nm 507 nm 193 nm 0.45 257 nm 476 nm DUV 193 nm 0.60 193 nm 268 nm Lens, NA Center of focus -- DepthDepth ofof focusfocus Photoresist

Wafer DOF ++ Film

Resolution Versus Depth of Focus for Varying NA Lens λ DOF = 2 - 2(NA) Depth of focus Center of focus Photoresist 2005 SOC設計概論Depth of Focus (DOF): Film 中山電機系 黃義佑 + 20 Photolithography Equipment (a) Contact / Proximity Aligner System

Mercury arc lamp

Illuminator

Alignment scope (split Mask vision) Mask stage (X, Y , Z , θ)

Wafer

Wafer stage Vacuum 2005 SOC設計概(X, Y,論 Z, θ) Proximity aligner : gap = 2.5~25 µm chuck 中山電機系 黃義佑 Used with permission from Canon USA, 21 Photolithography Equipment

(b) Scanning Projection Aligner (Scanner) : 1978~1982

Mercury arc lamp Illuminator Wafer assembly

Mask Scan directio n e) tiv ec bly refl m ( sse ion s a ect ic Proj opt Exposure light (narrow slit of UV gradually scans entire mask field onto wafer)

The major challenge of scanner was making a good 1X mask that contained all the chips on2005 the SOCwafer.設計概 If論 the chip had submicron feature sizes, then the mask also 中山電機系 黃義佑 22 had submicron dimensions. Photolithography Equipment

(c) Step-and-Repeat Aligner (Stepper): 1983~1990s

Steppers have their distinct name because the tool projects only one exposure field (which may be one or more chips on the wafer), and then steps to the next location on the wafer to repeat the exposure. A stepper use a reticle, which contains the pattern in an exposure field corresponding to one or more die. A mask is not used in a stepper since a mask contains the entire die matrix. The optical projection exposure system of steppers uses refractive optics to project the reticle image onto the wafer. 2005 SOC設計概論 中山電機系 黃義佑 Used with permission from Canon USA, FPA-3000 i5 (original drawing by FG2, Austin, TX) 23 Photolithography Equipment Stepper Exposure Field

UV light An advantage of optical steppers is their ability to use a reduction Reticle field size lens. Traditionally, I-line stepper 20 mm × 15mm, reticle are sized 4X, 5X, or 10X 4 die per field larger than the actual image to be patterned (initially steppers used 10X reticles and then later 5:1 reduction lens 5X and 4X).

Image exposure on Serpentine wafer 1/5 of reticle field stepping 4 mm × 3 mm, pattern 4 die per exposure 2005 SOC設計概論 中山電機系 黃義佑 Wafer 24 Photolithography Equipment

Benefit: (d) Step-and-Scan System : 2000s 1. The exposure field is increased for large chip sizes. The lens field only has to be a Scan narrow slit, permitting a smaller Stepper Step and Scan lens system. Image Field Image Field 2. The ability to adjust (single exposure) focus throughout a scan (called on –the- fly focus), permitting compensation for Reticle Scan Reticle lens defects and changes in wafer UV UV flatness. This improved control of 5:1 lens focus during a scan 4:1 lens yields improved CD Wafer Wafer uniformity control Stepping direction Scan across the exposure field.2005 SOC設計概論 Wafer Exposure Field for Step-and-Scan 中山電機系 黃義佑 25 Light Sources

„ Ultraviolet (UV) light

„ Deep ultraviolet (DUV) light

„ Ion beam

Minimum linewidth and exposure wavelength

2005 SOC設計概論 中山電機系 黃義佑 26 Comparison of Reticle Versus Mask Reticle Mask Parameter (Pattern for Step-and-Repeat (Pattern for 1:1 Mask-Wafer Transfer) Exposure) Easier to pattern submicron dimensions on wafer due to larger Difficult to pattern submicron dimensions on Critical Dimension pattern size on reticle (e.g., 4:1, mask and wafer without reduction optics. 5:1). Small exposure field that requires Exposure Field Exposure field is entire wafer. step-and-repeat process. Optical reduction permits larger Mask has same critical dimensions as wafer – Mask Technology reticle dimensions – easier to more difficult to print. print. Requires sophisticated automation Potentially higher (not always true if equipment Throughput to step-and-repeat across wafer. is not automated). Adjusts for individual die Global wafer alignment, but no individual die Die alignment & focus alignment & focus. alignment & focus. Improved yield but no reticle defect permitted. Reticle defects Defects are not repeated multiple times on a Defect density are repeated for each field wafer. exposure. Stepper compensates during initial global pre-alignment No compensation, except for overall global focus Surface flatness 2005 SOC設計概m論easurements or during die-by- and alignment. 中山電機系 黃義佑die exposures. 27 Principles of Electron Beam Lithography E-beam mask writer

Electronics Console Work Station Height detection TFE electron beam column Vacuum Electron Stage 9-track assembly control beam position magnetic module control control tape drive Automatic loading chamber Data direct Work stage Servo Control Transfer TFE control Height computer electron deflection computer and drive Beam control Printer/Plotter source Operator and Super and deflection control console dynamic flash correction HTM Work table Dynamic corrections Work chamber, load chamber, vibration isolation, ion pump, and vacuum system

Direct-Write method: transferring a high- Utility Console resolution pattern Temperature Air and Cassette directly to the reticle control nitrogen clamping control control surface Roughing Backing pump pump Coolant flow Water control chiller

2005 SOC設計概論 中山電機系 黃義佑 28 Alignment

Overlay accuracy is the measure of the alignment system’s ability to overlay the reticle pattern onto the wafer pattern. Overlay budget describes the maximum relative displacement between a patterned layer and the previously defined layer. In general, the overlay budget is about one-third of the critical dimension. For 0.15µm design rules, the overlay budget is expected to be 50nm. −∆Y Perfect overlay accuracy Shift in registration

+Y +Y

-X +X -X +X

-Y ∆X -Y

Reticle pattern Wafer pattern

2005 SOC設計概論 中山電機系 黃義佑 Overlay Budget 29 Alignment

For steppers and step- and-scan systems, 32 31 30 29 Stop each reticle pattern is aligned and exposed at 23 24 25 26 27 28 multiple locations as the aligner steps 22 21 20 19 18 17 across the wafer. Each field corresponds to 11 12 13 14 15 16 the reticle pattern of a single large chip or 1098765 several smaller chips.

12 34 A grid is the particular Start path that the photo tool follows to step across the wafer2005 and SOC expose設計概論 the individual中山電機系 fields. 黃義佑 Grid of Exposure Fields on Wafer 30 Alignment Marks

RA, Reticle alignment marks, L/R ++ + FAR RAR GA, Wafer global alignment marks, L/R + GA + FA, Wafer fine alignment marks, L/R +

FAL/R + + GAR + FAL

RAL 1st Mask + GAL

Notch, coarse FAR alignment For 2nd 1st mask layer mask FAL/R + + { + From 1st mask

FAL 2nd Mask

2nd mask layer

2005 SOC設計概論 中山電機系 黃義佑 31 5. Post-Exposure Bake (PEB) & 6. Photoresist Development PEB is necessary for chemically amplified DUV resists to catalyze critical resist chemical reactions. PEB is also required for conventional i-line resists (reduce standing wave effect & improve adhesion ) Typical PEB Temperatures 100 to 110°C on a hot plate PEB process is immediately after Exposure process.

Development Process Summary: Soluble areas of photoresist are Develop dissolved by developer chemical dispenser Visible patterns appear on wafer - windows - islands Quality measures: - line resolution - uniformity Vacuum chuck - particles and defects To vacuum pump Spindle 2005 SOC設計概論 connected to 中山電機系 黃義佑 spin motor 32 Develop

Photoresist Development Problems

Resist Substrate

X X √ X Under Incomplete Correct Severe develop develop develop overdevelop

2005 SOC設計概論 中山電機系 黃義佑 33 Development of Positive Resist

Resist exposed to light dissolves in the Unexposed develop chemical. positive resist Resist Development Parameters Developer Temperature Developer Time Developer Volume Normality Rinse Crosslinked Exhaust Flow resist Wafer Chuck 2005 SOC設計概論 中山電機系 黃義佑 34 Resist Development with Continuous Spray

Spray Vapor Resist Develo Edge-bead Load Station Prime Coat p-Rinse Removal Transfer Station

Wafer Transfer System

Vacuum chuck To vacuum pump Spindle connected to spin motor Soft Cool Cool Hard Bake Plate Plate Bake

(a) Wafer track system (b) Developer spray dispenser

2005 SOC設計概論 中山電機系 黃義佑 35 Puddle Resist Development

Puddle formation Developer dispenser

(a) Puddle dispense (b) Spin-off excess developer

2005 SOC設計概論 中山電機系 黃義佑 (c) DI H2O rinse (d) Spin dry 36 7. Hard Bake

A Post-Development Thermal Bake Evaporate Remaining Solvent Improve Resist-to-Wafer Adhesion Higher Temperature (120 to 140°C) than Soft Bake

Photoresist Characteristics of Hard Bake: – Post-Development Exposure – Evaporates Residual Solvent in Photoresist – Hardens the Resist – Improves Resist-to-Wafer Adhesion – Prepares Resist for Subsequent Processing – Higher Temperature than Soft Bake, but not to Point Where Softened Resist Flow at High Resist Softens and Flows Temperature 2005 SOC設計概論 Resist中山電機系 Hardening 黃義佑 with Deep UV 37 8. Develop Inspect Post-Develop Inspection to Find Defects Find Defects before Etching or Implanting Prevents Scrap Characterizes the Photo Process by Providing Feedback Regarding Quality of the Lithography Process Develop Inspect Rework Flow Typically an Automated Operation

2005 SOC設計概論 中山電機系 黃義佑 Automated Inspection Tool for Develop Inspect 38 Develop Inspect Rework Flow

UV light Resist Mask HMDS

1. Vapor prime 2. Spin coat 3. Soft bake 4. Align and expose 5. Post-exposure bake

O2

Rejected wafers

PlasmaPlasma Strip and clean 8. Develop inspect 7. Hard bake 6. Develop

Rework

2005 SOC設計概論 中山電機系 黃義佑 Ion implant Passed wafers Etch 39