(UW) Lecture Notes on Photolithography Why Lithography?
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Three-Dimensional Integrated Circuit Design: EDA, Design And
Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change. -
Paper 73-3 Has Been Designated As a Distinguished Paper at Display Week 2018
Distinguished Student Paper 73-3 / T. Ji Paper 73-3 has been designated as a Distinguished Paper at Display Week 2018. The full- length version of this paper appears in a Special Section of the Journal of the Society for Information Display (JSID) devoted to Display Week 2018 Distinguished Papers. This Special Section will be freely accessible until December 31, 2018 via: http://onlinelibrary.wiley.com/page/journal/19383657/homepage/display_week_2018.htm Authors that wish to refer to this work are advised to cite the full-length version by referring to its DOI: https://doi.org/10.1002/jsid.640 SID 2018 DIGEST Distinguished Student Paper 73-3 / T. Ji Tingjing Ji- Full Color Quantum Dot Light-Emitting Diodes Patterned by Photolithography Technology Full Color Quantum Dot Light-Emitting Diodes Patterned by Photolithography Technology Tingjing Ji (student), Shuang Jin, Bingwei Chen, Yucong Huang, Zijing Huang, Zinan Chen, Shuming Chen*, Xiaowei Sun Department of Electrical and Electronic Engineering, Southern University of Science and Technology, Shenzhen, PR China, 518055 *Corresponding author: [email protected] Abstract the traditional patterning processes. The QLED device achieved Photolithography is a high resolution and mature patterning maximum electroluminescence intensity of 23 770 cd/m2. [13] technique which has been widely used in semiconductor industry. For display application, a pixel consists of red (R), green (G) and In this work, we use photolithography to fine pattern the QD blue (B) side-by-side sub-pixels, which thereby requires a high layers. Because it is difficult to etch the QD layer, lift-off is used resolution patterning of the light-emission layers. -
Patterning of Quantum Dots by Dip-Pen and Polymer Pen Nanolithography
Nanofabrication 2015; 2: 19–26 Research Article Open Access Soma Biswas*, Falko Brinkmann, Michael Hirtz, Harald Fuchs Patterning of Quantum Dots by Dip-Pen and Polymer Pen Nanolithography Abstract: We present a direct way of patterning CdSe/ lithography and photolithography, these direct techniques ZnS quantum dots by dip-pen nanolithography and do not rely on resist layers and multi-step processing, but polymer pen lithography. Mixtures of cholesterol and allow the precise deposition of ink mixtures. Spot sizes in phospholipid 1,2-dioleoyl-sn-glycero-3 phosphocholine commercially widespread inkjet printing and other related serve as biocompatible carrier inks to facilitate the transfer spotting techniques are usually in the range of 50 to 500 of quantum dots from the tips to the surface during µm [5–7], while high resolution approaches (µCP, DPN and lithography. While dip-pen nanolithography of quantum PPL) reach sub-µm features. dots can be used to achieve higher resolution and smaller Microcontact printing utilises a predesigned pattern features (approximately 1 µm), polymer pen poly(dimethylsiloxane) (PDMS) stamp that is first coated lithography is able to address intermediate pattern scales with ink and subsequently pressed onto the surface in the low micrometre range. This allows us to combine manually. A total area up to cm2 can be patterned retaining the advantages of micro contact printing in large area and a lateral resolution of approximately 100 nm [8]. Dip-pen massive parallel patterning, with the added flexibility in nanolithography (Figure 1a) employs an atomic force pattern design inherent in the DPN technique. microscopy tip (AFM) as a quill pen. -
Recommendation to Handle Bare Dies
Recommendation to handle bare dies Rev. 1.3 General description This application note gives recommendations on how to handle bare dies* in Chip On Board (COB), Chip On Glass (COG) and flip chip technologies. Bare dies should not be handled as chips in a package. This document highlights some specific effects which could harm the quality and yield of the production. *separated piece(s) of semiconductor wafer that constitute(s) a discrete semiconductor or whole integrated circuit. International Electrotechnical Commission, IEC 62258-1, ed. 1.0 (2005-08). A dedicated vacuum pick up tool is used to manually move the die. Figure 1: Vacuum pick up tool and wrist-strap for ESD protection Delivery Forms Bare dies are delivered in the following forms: Figure 2: Unsawn wafer Application Note – Ref : APN001HBD1.3 FBC-0002-01 1 Recommendation to handle bare dies Rev. 1.3 Figure 3: Unsawn wafer in open wafer box for multi-wafer or single wafer The wafer is sawn. So please refer to the E-mapping file from wafer test (format: SINF, eg4k …) for good dies information, especially when it is picked from metal Film Frame Carrier (FFC). Figure 4: Wafer on Film Frame Carrier (FFC) Figure 5: Die on tape reel Figure 6: Waffle pack for bare die Application Note – Ref : APN001HBD1.3 FBC-0002-01 2 Recommendation to handle bare dies Rev. 1.3 Die Handling Bare die must be handled always in a class 1000 (ISO 6) clean room environment: unpacking and inspection, die bonding, wire bonding, molding, sealing. Handling must be reduced to the absolute minimum, un-necessary inspections or repacking tasks have to be avoided (assembled devices do not need to be handled in a clean room environment since the product is already well packed) Use of complete packing units (waffle pack, FFC, tape and reel) is recommended and remaining quantities have to be repacked immediately after any process (e.g. -
From Sand to Circuits
From sand to circuits By continually advancing silicon technology and moving the industry forward, we help empower people to do more. To enhance their knowledge. To strengthen their connections. To change the world. How Intel makes integrated circuit chips www.intel.com www.intel.com/museum Copyright © 2005Intel Corporation. All rights reserved. Intel, the Intel logo, Celeron, i386, i486, Intel Xeon, Itanium, and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. 0605/TSM/LAI/HP/XK 308301-001US From sand to circuits Revolutionary They are small, about the size of a fingernail. Yet tiny silicon chips like the Intel® Pentium® 4 processor that you see here are changing the way people live, work, and play. This Intel® Pentium® 4 processor contains more than 50 million transistors. Today, silicon chips are everywhere — powering the Internet, enabling a revolution in mobile computing, automating factories, enhancing cell phones, and enriching home entertainment. Silicon is at the heart of an ever expanding, increasingly connected digital world. The task of making chips like these is no small feat. Intel’s manufacturing technology — the most advanced in the world — builds individual circuit lines 1,000 times thinner than a human hair on these slivers of silicon. The most sophisticated chip, a microprocessor, can contain hundreds of millions or even billions of transistors interconnected by fine wires made of copper. Each transistor acts as an on/off switch, controlling the flow of electricity through the chip to send, receive, and process information in a fraction of a second. -
Projection Photolithography-Liftoff Techniques for Production of 0.2-Pm Metal Patterns
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 11, NOVEMBER 1981 1375 Projection Photolithography-Liftoff Techniques for Production of 0.2-pm Metal Patterns MARK D. FEUER AND DANIEL E. PROBER, MEMBER, IEEE GLASS FILTER Abstract-A technique whichallows the useof projection photo- \ yPHOTORESIST lithography with the photoresist liftoff process, for fabrication of sub- micrometer metal patterns, is described. Through-the-substrate (back- \II a projection) exposure of the photoresist produces the undercut profiles necessary forliftoff processing. Metal lines andsuperconducting microbridges of 0.2-pm width have been fabricated with this technique. I Experimental details and process limits are discussed. II OBJECTIVE IMMERSION OIL ECENT DEVELOPMENTS inmicrolithography have SUBSTRATE - (d) R made possible the production ofa variety of devices with PHOTORESIST %- I-l submicrometer (submicron) dimensions [ 11 , [2] , offering the (a) advantages of higherspeed and packing density.For many Fig. 1. Schematicdiagram of back-projectionand metal-liftoff pro- Josephson-effect devices in particular, submicron dimensions cedure. (a) Exposure system, employing a Zeiss optical microscope. Image of the mask is projected through the substrate, which is shown are essential for achieving optimalperformance over awide in sideview. (b) Schematic contours of constant exposure intensity. range of operatingconditions [3] . Forsubmicron pattern (c) After photoresist development and metallization. (d) After liftoff. transfer, liftoff processing [ 11 generally -
Summarizing CPU and GPU Design Trends with Product Data
Summarizing CPU and GPU Design Trends with Product Data Yifan Sun, Nicolas Bohm Agostini, Shi Dong, and David Kaeli Northeastern University Email: fyifansun, agostini, shidong, [email protected] Abstract—Moore’s Law and Dennard Scaling have guided the products. Equipped with this data, we answer the following semiconductor industry for the past few decades. Recently, both questions: laws have faced validity challenges as transistor sizes approach • Are Moore’s Law and Dennard Scaling still valid? If so, the practical limits of physics. We are interested in testing the validity of these laws and reflect on the reasons responsible. In what are the factors that keep the laws valid? this work, we collect data of more than 4000 publicly-available • Do GPUs still have computing power advantages over CPU and GPU products. We find that transistor scaling remains CPUs? Is the computing capability gap between CPUs critical in keeping the laws valid. However, architectural solutions and GPUs getting larger? have become increasingly important and will play a larger role • What factors drive performance improvements in GPUs? in the future. We observe that GPUs consistently deliver higher performance than CPUs. GPU performance continues to rise II. METHODOLOGY because of increases in GPU frequency, improvements in the thermal design power (TDP), and growth in die size. But we We have collected data for all CPU and GPU products (to also see the ratio of GPU to CPU performance moving closer to our best knowledge) that have been released by Intel, AMD parity, thanks to new SIMD extensions on CPUs and increased (including the former ATI GPUs)1, and NVIDIA since January CPU core counts. -
And Nanolithography Techniques and Their Applications
Review on Micro- and Nanolithography Techniques and their Applications Alongkorn Pimpin* and Werayut Srituravanich** Department of Mechanical Engineering, Faculty of Engineering, Chulalongkorn University, Pathumwan, Bangkok 10330, Thailand E-mail: [email protected]*, [email protected]** Abstract. This article reviews major micro- and nanolithography techniques and their applications from commercial micro devices to emerging applications in nanoscale science and engineering. Micro- and nanolithography has been the key technology in manufacturing of integrated circuits and microchips in the semiconductor industry. Such a technology is also sparking revolutionizing advancements in nanotechnology. The lithography techniques including photolithography, electron beam lithography, focused ion beam lithography, soft lithography, nanoimprint lithography and scanning probe lithography are discussed. Furthermore, their applications are summarized into four major areas: electronics and microsystems, medical and biotech, optics and photonics, and environment and energy harvesting. Keywords: Nanolithography, photolithography, electron beam lithography, focused ion beam lithography, soft lithography, nanoimprint lithography, scanning probe lithography, dip-pen lithography, microsystems, MEMS, nanoscience, nanotechnology, nano-engineering. ENGINEERING JOURNAL Volume 16 Issue 1 Received 18 August 2011 Accepted 8 November Published 1 January 2012 Online at http://www.engj.org DOI:10.4186/ej.2012.16.1.37 DOI:10.4186/ej.2012.16.1.37 1. Introduction For decades, micro- and nanolithography technology has been contributed to the manufacturing of integrated circuits (ICs) and microchips. This advance in the semiconductor and IC industry has led to a new paradigm of the information revolution via computers and the internet. Micro- and nanolithography is the technology that is used to create patterns with a feature size ranging from a few nanometers up to tens of millimeters. -
Techniques and Considerations in the Microfabrication of Parylene C Microelectromechanical Systems
micromachines Review Techniques and Considerations in the Microfabrication of Parylene C Microelectromechanical Systems Jessica Ortigoza-Diaz 1, Kee Scholten 1 ID , Christopher Larson 1 ID , Angelica Cobo 1, Trevor Hudson 1, James Yoo 1 ID , Alex Baldwin 1 ID , Ahuva Weltman Hirschberg 1 and Ellis Meng 1,2,* 1 Department of Biomedical Engineering, University of Southern California, Los Angeles, CA 90089, USA; [email protected] (J.O.-D.); [email protected] (K.S.); [email protected] (C.L.); [email protected] (A.C.); [email protected] (T.H.); [email protected] (J.Y.); [email protected] (A.B.); [email protected] (A.W.H.) 2 Ming Hsieh Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089, USA * Correspondence: [email protected]; Tel.: +1-213-740-6952 Received: 31 July 2018; Accepted: 18 August 2018; Published: 22 August 2018 Abstract: Parylene C is a promising material for constructing flexible, biocompatible and corrosion- resistant microelectromechanical systems (MEMS) devices. Historically, Parylene C has been employed as an encapsulation material for medical implants, such as stents and pacemakers, due to its strong barrier properties and biocompatibility. In the past few decades, the adaptation of planar microfabrication processes to thin film Parylene C has encouraged its use as an insulator, structural and substrate material for MEMS and other microelectronic devices. However, Parylene C presents unique challenges during microfabrication and during use with liquids, especially for flexible, thin film electronic devices. In particular, the flexibility and low thermal budget of Parylene C require modification of the fabrication techniques inherited from silicon MEMS, and poor adhesion at Parylene-Parylene and Parylene-metal interfaces causes device failure under prolonged use in wet environments. -
Fundimentals of Photolithography
FUNDIMENTALS OF PHOTOLITHOGRAPHY One of the most widely used methods for creating nanoscale circuit components is Photolithography. The word lithography is derived from the Greek words lithos (stone) and graphein (to write) and finds its roots in a process invented by Aloys Senefelder in 1796. By treating a piece of limestone with certain chemicals, Senefelder was then able to transfer an image carved into the stone onto a piece of paper. This was done by coating certain parts of the porous limestone with a water repellant substance. When ink was applied to the stone it would only adhere to the untreated hydrophilic areas, and hence the image carved into the rock could be transferred repeatedly onto paper. Senefelder's technique is still used in some artistry applications today. As time progressed and technology improved, lithography methods evolved. In the 1820's a French scientist by the name of Nicephore Niepce developed the first photoresist, a component fundamental to photolithography. A photoresist is a substance that undergoes a chemical reaction when it is eXposed to light. Niepce's photoresist was a material known as Bitumen of Judea, a kind of naturally occurring asphalt. A sheet of stone, metal, or glass was coated with a thin layer of this bitumen, which became less soluble where it was eXposed to light. Areas that were uneXposed could then be removed using a solvent, and the resultant exposed areas of the sheet were etched using a chemical bath. After the remaining photoresist was removed, the sheet could then be used as a printing plate. Photolithography today is in many ways similar to the original process invented by Niepce. -
Photolithography for the Investigation of Nanostructures
Photolithography for the Investigation of Nanostructures ---------------------------------------------------------- A Thesis Presented to the Honors Tutorial College, Ohio University ---------------------------------------------------------- In Partial Fulfillment of the Requirements for Graduation from the Honors Tutorial College with the degree of Bachelor of Science in Physics ---------------------------------------------------------- Helen M. Cothrel April 2015 This thesis has been approved by the Honors Tutorial College and the Department of Physics and Astronomy ________________________________________________ Dr. Eric Stinaff Professor, Physics and Astronomy Thesis adviser ________________________________________________ Dr. David Drabold Distinguished Professor, Physics and Astronomy Honors Tutorial College Director of Studies, Physics and Astronomy ________________________________________________ Dr. Jeremy Webster Dean, Honors Tutorial College 2 Table of Contents List of Figures ................................................................................................................. 4 Abstract ........................................................................................................................... 8 Introduction and Background ....................................................................................... 10 Photolithography ....................................................................................................... 11 Quantum Dots .......................................................................................................... -
Molecular Scale Imaging with a Smooth Superlens
Molecular Scale Imaging with a Smooth Superlens Pratik Chaturvedi1, Wei Wu2, VJ Logeeswaran3, Zhaoning Yu2, M. Saif Islam3, S.Y. Wang2, R. Stanley Williams2, & Nicholas Fang1* 1Department of Mechanical Science & Engineering, University of Illinois at Urbana- Champaign, 1206 W. Green St., Urbana, IL 61801, USA. 2Information & Quantum Systems Lab, Hewlett-Packard Laboratories, 1501 Page Mill Rd, MS 1123, Palo Alto, CA 94304, USA. 3Department of Electrical & Computer Engineering, Kemper Hall, University of California at Davis, One Shields Ave, Davis, CA 95616, USA. * Corresponding author Email: [email protected] RECEIVED DATE Abstract We demonstrate a smooth and low loss silver (Ag) optical superlens capable of resolving features at 1/12th of the illumination wavelength with high fidelity. This is made possible by utilizing state-of-the-art nanoimprint technology and intermediate 1 wetting layer of germanium (Ge) for the growth of flat silver films with surface roughness at sub-nanometer scales. Our measurement of the resolved lines of 30nm half-pitch shows a full-width at half-maximum better than 37nm, in excellent agreement with theoretical predictions. The development of this unique optical superlens lead promise to parallel imaging and nanofabrication in a single snapshot, a feat that are not yet available with other nanoscale imaging techniques such as atomic force microscope or scanning electron microscope. λ = 380nm 250nm The resolution of optical images has historically been constrained by the wavelength of light, a well known physical law which is termed as the diffraction limit. Conventional optical imaging is only capable of focusing the propagating components from the source. The evanescent components which carry the subwavelength information exponentially decay in a medium with positive permittivity (ε), and positive permeability (µ) and hence, are lost before making it to the image plane.