Powering Electronics from the USB Port

Power Management Texas Instruments Incorporated Powering electronics from the USB port

By Robert Kollman, Senior Applications Manager, Power Management, DMTS, and John Betten, Applications Engineer, Member Group Technical Staff Introduction quiescent current to a total of 500 µA for a low-power The USB interface can provide power to low-power device and 2.5 mA for a high-power device. It often peripherals but must adhere to the USB 2.0 specification requires the use of switches to power down portions of (Reference 1). Table 1 provides an overview of the the peripheral’s electronics. requirements placed on the peripheral equipment. The The USB 1.0 specification has been active since its host equipment provides a 5-V supply capable of, in the release in November 1995. Products that were delivered to worst case, only 2.25 W of power. In some cases, this is the 1.0 specification had no official logo associated with clearly not enough for the peripheral, and an alternate them. Many times the products did not fully meet the power source such as a wall adapter or off-line power current-limit requirements, which usually was not a supply is used. In other cases, 2.25 W is much more than problem with the product connected to a PC. However, is needed; and low-cost, linear regulators can be used to problems did arise when there were multiple products generate the supply voltages for the peripherals. However, connected in a hub arrangement. With the release of the in many cases this power limit necessitates the use of 2.0 specification, certified products will be marked with a higher-efficiency power-supply designs and complicates logo. The certification promises to be more rigorous, and the system trade-offs of cost, efficiency, and size. This designers should expect to meet the requirements of the article discusses these issues. new specification. Inrush limit and power segmentation Table 1. USB power requirements at a glance There are two possible configurations for USB products— PARAMETER REQUIREMENT a single peripheral connected directly to a host, or a set Low-power device 4.4 to 5.25 V of peripherals connected through hubs to the host. For a Voltage 4.75 to 5.25 V at single peripheral, the current-limiting requirements usually High-power device upstream connector are not an issue unless a large input capacitor is placed Maximum quiescent across the power-supply voltage for hold-up. If hubs are Low-power device 500 µA current used, current limiting will definitely be required due to the Maximum low-power current 100 mA unknown nature of the peripherals that will be plugged into the hub. Maximum high-power current 500 mA The current limits can be implemented in two manners, Maximum power draw 2.25 W one using discrete power devices with external control Maximum input capacitor 10 µF circuits, and the other with the switches integrated into Maximum inrush 50 µC the controllers. In higher-power applications, the discrete approach usually yields a lower-cost solution. However, in lower-power applications, an integrated approach is very Another unique requirement of the USB power interface attractive. With the low voltages and currents involved in is the different current draws allowed. When a device is the USB, a number of manufacturers are developing ICs first connected to the USB, its bypass capacitor could be specifically targeted for these markets. Figure 1 on the charged abruptly and create a glitch on the host equipment next page presents a typical circuit. The first output is supply. The USB specification resolves this problem by an adjustable linear regulator that can be configured for limiting the initial power surge in two ways. The peripheral 0.9- to 3.3-V output, which powers the hub controller and device is allowed only a small (<10-µF) bypass capacitor, other electronics. The second is a switched output that and the charge drawn from the bus is limited to 50 µC powers the peripherals connected to the hub. The inte- over a specified time. Larger capacitors can be used if grated approach provides a number of desirable features. inrush limiting is provided. Once the USB is connected, The device is much more rugged than a discrete approach there are further limits on current draw. The host first because a thermal limit monitors the pass-element recognizes the peripheral as low-power, allowing it to draw temperature and shuts down if an over-temperature is less than 100 mA of current. The peripheral can ask the detected. Two-level current limiting is provided in the host to recognize it as a high-power device in a process switch to prevent glitching of the host power bus. Initial called “enumeration.” Once enumeration is completed and power-up current is limited to 100 mA until the output permission is granted, the allowed peripheral current is reaches 93% of the input voltage; then, once the USB increased to 500 mA. The USB spec also includes a suspend controller is enumerated, the current limit is raised to mode that supports remote wake-up. This mode limits 500 mA, typical of the high-power peripherals.

Analog and Mixed-Signal Products www.ti.com/sc/analogapps 2Q 2002 Analog Applications Journal Texas Instruments Incorporated Power Management

Figure 1. Internal switch power segmentation and limiting

U1 TPS2140PWP 1 14 SWPG SWPLDN Bus 2 13 Power Power SWIN SWOUT to Other + 3 12 Peripherals C1 SWIN SWOUT C3 4 11 0.1 µF 4.7 µF LDOIN LDOOUT 5 10 + SWENA LDOPLDN C4 C2 6 9 4.7 µF LDOENA ADJ 0.1 µF 7 8 R2 GND LDOPG PWP 332 kΩ Power

Switch 15 to Hub Enable Control R1 C6 100 kΩ 0.1 µF + C5 4.7 µF

Table 2. Power-management options POWER SWITCH OVER- OVERALL MANAGER RESISTANCE CIRCUIT AREA TEMPERATURE RELATIVE COST IMPLEMENTATION (mΩ) (in2) PROTECTION (%) Internal switch 100 0.30 Yes 80 External switch 50 0.5 No 100

Table 2 compares the two approaches, internal versus external switch approach uses multiple semiconductor external switches or pass elements. The pass elements packages compared with the single package of the inte- have higher resistance in the internal switch approach, grated switch. Each of the packages has its own overhead which occupies less than 60% of the external switch of assembly and test, making the overall system-level costs approach. However, the silicon die area is more costly in about equivalent. the internal switch because more mask levels are involved in the IC’s device structure than in a simple MOSFET. Powering low-voltage digital electronics Typically, the IC will use over 20 mask levels compared Generating low voltages, such as 3.3 V, from the USB can with 8–10 levels of the MOSFET. The higher level of inte- be done in several ways. Regardless of the configuration gration eliminates at least two semiconductor packages used, the output current for a 3.3-V output is limited to and the resulting poor interconnect efficiency. In addition, 0.65 A (assuming 95% efficiency) due to the 2.25-W input the higher level of integration provides a higher reliability power limitation. The options to provide these lower volt- as bond wires and solder joints are eliminated. Reliability ages include linear regulators, switching power supplies, is further enhanced with the over-temperature protection and charge pumps. Within switching power supplies, there of the internal switch. With the external switch, there is are two further subgroups, synchronous and conventional. no cost-effective method to measure MOSFET tempera- The synchronous is more efficient and costly and will be ture to protect it from shorted loads. Current foldback and used to get as much power from the USB as possible. power cycling techniques can help but do not provide the The linear regulator is the lowest-cost and highest- robustness of the thermal shutdown. The last column of density option for generating lower voltages from the 5-V the table presents a cost comparison between the two USB. When there is no power issue, it will be the circuit approaches. The costs are almost the same and would of choice. However, when power becomes an issue, bear a closer examination on a particular requirement. switching regulators can more efficiently power the Generally, the reason the costs are so close is that the

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peripheral. Figure 2 shows one of the lowest-cost buck design, allowing lower on resistance devices to be used switching regulator options available. In this circuit, the compared with integrated FET controllers, and possibly switching of the FET, Q2, is controlled to “buck” the achieving greater efficiency. average voltage presented to the output filter, which then In Figure 2, a large percentage of the overall power loss smooths the switching waveform. The drawback of this is dissipated in the freewheeling diode D2. In Figure 3 this circuit is that the lack of controller integration requires an diode is replaced with an N-channel FET, making this external FET and drive circuit, which makes the circuit circuit a synchronous buck converter, which significantly relatively large. An external FET provides flexibility in the improves the converter efficiency. Efficiency improvements

Figure 2. Low-cost, non-synchronous buck regulator

5 V IN C1 + 470 µF Q1 6.3 V C2 U1 R1 100 pF TL5001D 499 Ω 2N3904 2 VCC R2 6 3 2 1 DTC 30.1 kΩ 3 1 COMP OUT C3 4 D1 Q2 L1 0.033 µF 4 TPS1101 FB MBRM140 47 µH 7 5 8765 RT SCP 3.3 V 8 GND C5 D2 + R4 R3 C4 470 µF Ω MBRS340T3 R5 100 k 100 kΩ 1 µF 6.3 V 43.2 kΩ R6 C6 10 kΩ 1000 pF

Figure 3. External-switch synchronous buck regulator

Q1 L1 Si3443DV 5.0 µH 3.3 V 5 VIN 4 6 5 + C1 C2 C3 3 2 22 µF 1 120 µF 22 µF 6.3 V 4 V 6.3 V U1 R1 TPS43000 1 kΩ 1 16 SYNC/SD SWN R2 2 15 Ω CCS SWP 1 2 5 6 37.4 k 3 14 RT VP C4 4 13 3 D1 CCM PDRV 0.47 µF Q2 5 12 ZHCS2000 BUCK GND 4 Si3442DV 6 11 PFM NDRV 7 10 COMP VOUT 8 9 FB VIN

C7 C5 C6 C8 270 pF C9 0.47 µF 0.47 µF 3.0 pF R3 5.76 kΩ R4 560 pF R5 115 kΩ 32.4 kΩ R6

100 kΩ

Analog and Mixed-Signal Products www.ti.com/sc/analogapps 2Q 2002 Analog Applications Journal Texas Instruments Incorporated Power Management

Figure 4. Step-down charge pump Figure 5. Boost regulator

5 VIN U1 C1 4.7 µF TPS60501DGS R1 6.3 V 1 10 499 kΩ EN FB 2 L1 PG GND 9 U1 TPS6734D 15 µH 3 8 1 8 C2F– C1F– C2 EN VCC 4 7 .01 µF C1 C2F+ OUT C2 2 7 1 µF 5 6 1 µF REF FB VIN C1F+ 3 6 16 V 16 V SS OUT 12 V C3 4 5 D1 5 VIN 3.3 V .01 µF COMP GND MBRS130T3 C3 C4 4.7 µF 22 µF C5 6.3 V 6.3 V C4 10 µF 1000 pF 16 V

can be realized over a wide load range with this circuit. At solution. The controller utilizes internal FETs that connect very light loads, pulse skipping can decrease gate-drive two flying capacitors in various series or parallel configu- losses. When the output voltage drops 2% below the nomi- rations, dumping their energy to the output. The input nal voltage set point, the converter senses it and switches voltage and the load are used to set the internal FET until the output reaches an upper threshold; it then puts configuration automatically. At loads heavier than 150 mA, itself in sleep mode until the load discharges the output the controller acts as an LDO and stops using the switched capacitor to the lower threshold again. This circuit provides capacitors altogether. Output current is limited to a maxi- excellent efficiency but is more costly than the one in mum of 0.25 A, which limits this circuit to low-power Figure 2. Its circuit area is also slightly smaller, mainly applications. Efficiency is between 80 and 90% for light because the controller can operate at frequencies of up to loads between 1 mA and 50 mA, but drops off to approxi- 1 MHz, which allows the inductor and input/output capaci- mately 65% above that when operating in LDO mode. The tors to be noticeably smaller. cost of Figure 4 is one of the lowest, due to the low cost of Integrating the top FET, bottom FET, drive circuit, and the ceramic capacitors. feedback compensation into the controller provides for a Table 3 provides a summary of the low-voltage step-down small, integrated, and efficient converter solution. This is options discussed. Efficiency, cost, and circuit area are becoming a very popular solution because it is generally also listed for reference. So what’s the right choice? Linear simple to design and has a very short design cycle time. regulators, when you can afford the losses. Then take a Software is available that aids in the design, making it look at charge pumps and determine their losses based on possible for novices to design power supplies. Controllers conversion ratios. Finally, evaluate non-synchronous and such as the TPS5431x and TPS5461x SWIFTTM series pro- then synchronous regulators. In each case, the system vide such integration, but their cost is higher due to the cost and size increase, but more power is available for the added performance and features. load. A second trade-off in the switching power supplies Circuit area is often a critical design parameter. The step- involves deciding between internal and external FETs. down charge pump in Figure 4 represents an extremely The cost is usually lowest with external FETs; while the small solution. Four ceramic capacitors and the charge design time, component count, and size will be smaller pump controller are the only components required for this with internal FETs. Powering higher-voltage analog Table 3. Low-voltage (5-V to 3.3-V) regulator options Higher-legacy voltages, such as 5 V OVERALL and 12 V, are often required to power TYPICAL RELATIVE analog circuits. The loading on these INTERNAL EFFICIENCY COST AREA 2 outputs is typically not as heavy as on TOPOLOGY SWITCH (%) (%) (in ) their digital voltage counterparts— Linear Y 66 40 0.1 usually less than 100 mA. The circuit Non-synchronous buck N 87 100 1.2 in Figure 5 is a boost regulator that Non-synchronous buck Y 85 150 1.1 provides 12 V and will provide up to Synchronous buck N 96 200 1.0 120 mA while operating over the 5-V Synchronous buck Y 95 250 0.7 USB output voltage range. In this Charge pump* Y 60 to 90 70 0.15

*Current is limited to 0.25 A, and efficiency is largely dependent on input voltage. 31

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Figure 6. Synchronous SEPIC converter

5 VIN

L1 R1 C2 C1 Ω 1 µF 22 µF 47 µH 10 6.3 V C3 1 µF R2 U1 86.6 kΩ R3 UCC39421PW 1 kΩ 5 6 7 8 1 16 D1 RSEN RSEL 2 15 B240 Q1 VOUT COMP 4 IRF7404 3 14 RECT FB 4 13 PGND PFM 1 2 3 5 6 7 8 5 VOUT 5 12 R4 CHRG GND 169 kΩ 6 11 VPUMP RT C4 Q2 4 7 10 R5 68 pF IRF7401 CP SYNC/SD 28 kΩ 8 9 1 2 3 VIN ISENSE C6 C7 C5 L2 4700 pF 22 µF 100 µF R6 6.3 V 47 µH 169 kΩ 6.3 V R7 C8 C9 0.1 Ω 1 µF 1 µF D2 0.25 W BAT54

3.01 kΩ

design, the FET is integrated into the controller along with Figure 7. Synchronous buck converter with auxiliary output winding the feedback resistor network, reducing total parts count to a minimum. A drawback to this Q1 approach is that the circuit IRLMS6702 5 V block provides no current limit. If the 12-V output is shorted to U1 TPS62000DGS C1 ground, there is nothing in the 1 10 10 µF 5 V VIN PGND 6.3 V VIN, L1, D1 path to limit current. IN 2 9 FC L 3.3 V An alternative topology, the 3 8 L1 GND EN SEPIC, can overcome this short- C2 C3 4 7 10 µH C4 PG SYNC R1 coming. Also, the SEPIC conver- 4.7 µF 0.1 µF 5 6 825 kΩ 10 µF sion ratio extends above and 6.3 V FB ILIM 6.3 V below the input voltage as compared with the boost, whose R2 ratio just includes voltage greater 130 kΩ than VIN. Since the USB voltage can range from 4.5 V to 5.5 V, the SEPIC converter in Figure 6 makes an excellent choice for a 5-V output. This SEPIC uses a synchronous rectifier Q1 to high RMS ripple-current rating and a low ESR to minimize reduce the losses in the output diode and improve effi- the output ripple voltage. Ceramic capacitors are usually ciency by several percent. Diode D1 conducts only during chosen due to their high ripple-current rating and low cost. the on/off transitions of Q1 to prevent the intrinsic diode Figure 7 shows an option for providing dual-output volt- of Q1 from conducting. Additional benefits include low- ages from a single synchronous buck converter. When the input ripple currents and inherent current limiting. On the bottom-side FET (internal to TPS62000) conducts, FET negative side, the addition of the dc blocking capacitor C3 Q1 turns on, and output cap C1 charges with an additional is required. Since the blocking capacitor and output capaci- voltage developed across the secondary of L1. The level of tors must handle large pulsing currents, they require a the auxiliary voltage is determined by the turns ratio

Analog and Mixed-Signal Products www.ti.com/sc/analogapps 2Q 2002 Analog Applications Journal Texas Instruments Incorporated Power Management

Table 4. Higher-voltage regulator options OVERALL TYPICAL RELATIVE INTERNAL CURRENT EFFICIENCY COST AREA TOPOLOGY SWITCH LIMIT (%) (%) (in2) 5-V to 12-V boost N N 86 280 0.7 5-V to 12-V boost Y N 85 320 0.6 5-V to 5-V SEPIC* N Y 89 560 1.0 5-V to 5-V SEPIC Y Y 85 550 0.9 3.3-V to 5-V charge pump** Y Y 65 to 75 200 0.2 Sync buck w/aux winding✝ Y-Sync buck Y 95 100 0.3 N-Aux * Synchronous operation **TPS60133 charge pump controller, 0.3-A maximum output current ✝ Cost and area of auxiliary output only between the two windings of L1. The voltage across C1 is synchronous and non-synchronous operation, as well as in stacked on the 3.3-V regulated output; so, for a 5-V auxiliary an internal versus external switch, as in the buck regulator. output, an additional 1.7 V needs to be developed across L1’s secondary. A turns ratio of 2:1 will work well in this USB-powered DSL modem power supply example application. For low current levels, the voltage drops The circuit in Figure 8 (next page) is an example of a developed across the internal bottom FET and Q1 (which complete USB power supply with 3.3-V, 5-V, and 12-V turn on in phase with each other) are small and often can- outputs. With the 3.3-V powered at 0.32 A, the 5-V at cel each other out. These FET drops may not significantly 0.05 A, and the 12-V at 0.05 A, the overall efficiency is add to the output-voltage tolerance error, and good regu- 89.5%, which allows the input power to remain below the lation can be achieved. 2.25-W maximum limit. In operation, only the 3.3-V output Table 4 presents a comparison of some of the options is allowed to power up at turn-on, with the 5-V and 12-V for generating higher voltages for analog loads. Here again, enable pins being held low by the bus controller. No more the decision involves a trade-off between cost, performance, than 100 mA is drawn off the 3.3-V output during power- and loss. If power is not a problem, the first choice to up in low-power mode. Enumeration then comes from the consider is a charge pump. When loss becomes an issue, a bus controller to allow the 5-V and 12-V to power up. A switching regulator may become warranted. The first boost topology was used for both the 5-V and 12-V outputs, circuit to consider, particularly if a buck regulator is being with the 5-V power stage input powered from the 3.3-V used, is the auxiliary winding scheme of Figure 7. It adds output. The controller chosen for both boost regulators minimal cost and degrades efficiency the least. Next come was the low-cost TL1451A dual controller. The approach the SEPIC and boost regulator. The need for short-circuit taken for this design example is geared toward low cost protection will determine which approach will be favored. and high efficiency rather than small area. Figure 9 shows Usually a boost will be chosen for its higher efficiency if a photograph of the completed hardware, which measures current limiting is not needed or can be accommodated 1.5" × 2". elsewhere in the system. There are also trade-offs in

Figure 9. DSL modem power supply

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Figure 8. USB-powered DSL modem power supply

U1 5 VIN TPS62000DGS J1 L1 1 1 10 10 µH 4.5 - 5.5 VIN VIN PGND J2 2 2 9 GND FC L 3.3 V @ 500 mA 3 8 4 GND EN 5 V @ 100 mA C1 C2 4 7 R3 C4 3 Ω GND 4.7 µF 0.1 µF PG SYNC 825 k 10 µF 2 5 6 R5 6.3 V FB ILIM 6.3 V 12 V @ 100 mA 130 kΩ 1

C5 R6 C6 R7 0.1 µF 100 kΩ Ω 0.1 µF 100 k 4 4 Q2 Q1 3 3 IRLMS6802 IRLMS6802 R8 R9 Ω Ω 10 k 1 2 5 6 10 k 1 2 5 6

Q3 5-V & 12-V 2N7002 Q4 Enable 2N7002 C9 C7 R10 C8 R11 4.7 µF Ω 0.1 µF 10 kΩ 0.1 µF 10 k 6.3 V L2 3.8 µH

R13 84.5 kΩ C11 Q5 1 µF R14 MMBT3904 D1 Ω 1 2 5 6 MBRS130T3 C13 R15 499 C12 0.1 µF 28.0 kΩ 10 µF Q7 U2 1 kΩ 3 16 V IRLMS2002 TL1451ACNS Q6 4 MMBT3906 16 9 R16 VREF VCC C14 11 Q8 0.1 µF 2DTC R17 MMBT3906 C16 R22 12 8 499 Ω R20 2FB GND .01 µF 100 kΩ 13 C15 R21 12.7 kΩ 2IN– 12.7 kΩ 14 10 0.1 µF 2IN+ 2OUT 6 1DTC C18 R25 5 7 C17 1FB 1OUT L3 R23 R18 .01 µF 100 kΩ 4 4.7 µF 20 kΩ Ω 1IN– 10 µH 1 k 3 6.3 V 1IN+ R24 R27 2 15 20 kΩ R19 20 kΩ RT SCP Ω 1 C19 20 k CT Q9 R28 1 µF R29 MMBT3904 D2 Ω 1 2 5 6 13.3 k C20 499 Ω MBRS130T3 C21 C22 1 µF R26 C24 10 µF 3 Q11 1 kΩ 1 µF 150 pF R30 16 V IRLMS2002 Q10 4 1 kΩ MMBT3906 Q12 R31 MMBT3906 499 Ω R34 R32 10 kΩ 84.5 kΩ

Conclusion Reference The design of a power supply powered from the USB port 1. USB Implementers Forum Inc., “Universal Serial Bus is heavily driven by the 2.25 W of available input power Specification Revision 2.0,” www.usb.org and the peripheral load requirements. The design process should involve a very careful analysis of load currents Related Web sites followed by a program to minimize them. Once the loads www.ti.com/sc/device/partnumber have been determined, the power-supply engineer should Replace partnumber with TL1451A, TL5001, TPS2140, develop multiple block diagrams with the topologies TPS6734, TPS43000, TPS54310, TPS54610, TPS54611, described in this article to develop the lowest-cost, most TPS60130, TPS60500, TPS62000 or UCC39421 power- and area-compliant approach. The array of inte- www.usb.org grated circuits to support these designs is very diverse; the designer has the options of striving for maximum integration, minimum cost, and ease of use.

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