Mc74hc4851a, Mc74hc4852a

MC74HC4851A, MC74HC4852A

Analog Multiplexers/ Demultiplexers with Injection Current Effect Control www.onsemi.com Automotive Customized

These devices are pin compatible to standard HC405x and MC1405xB analog mux/demux devices, but feature injection current SOIC−16 SOIC−16 WIDE effect control. This makes them especially suited for usage in D SUFFIX DW SUFFIX automotive applications where voltages in excess of normal logic CASE 751B CASE 751G voltage are common. The injection current effect control allows signals at disabled analog input channels to exceed the supply voltage range without affecting 1 TSSOP−16 QFN16 the signal of the enabled analog channel. This eliminates the need for DT SUFFIX MN SUFFIX external diode/resistor networks typically used to keep the analog CASE 948F CASE 485AW channel signals within the supply voltage range. The devices utilize low power silicon gate CMOS technology. The Channel Select and Enable inputs are compatible with standard MARKING DIAGRAMS CMOS outputs. 16 16

Features HC485xAG HC4851A AWLYWW AWLYWWG • Injection Current Cross−Coupling Less than 1 mV/mA (See Figure 10) 1 SOIC−16 1 • Pin Compatible to HC405X and MC1405XB Devices SOIC−16 WIDE • Power Supply Range (VCC − GND) = 2.0 to 6.0 V 16 • In Compliance With the Requirements of JEDEC Standard No. 7 A HC48 5xA • Chip Complexity: 154 FETs or 36 Equivalent Gates ALYWG 4851 G ALYWG • NLV Prefix for Automotive and Other Applications Requiring G 1 Unique Site and Control Change Requirements; AEC−Q100 TSSOP−16 QFN16* Qualified and PPAP Capable *V4851 marking used for • These Devices are Pb−Free, Halogen Free and are RoHS Compliant NLV74HC4851AMN1TWG

x = 1 or 2 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location)

ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.

13 X0 14 X1 FUNCTION TABLE − MC74HC4851A 15 X2 Control Inputs ANALOG 12 INPUTS/ X3 MULTIPLEXER/ 3 COMMON Select 1 DEMULTIPLEXER X OUTPUTS X4 OUTPUT/ Enable CBA ON Channels 5 INPUT X5 L L L L X0 2 X6 L L L H X1 4 X7 L L H L X2 11 A L L H H X3 CHANNEL 10 L H L L X4 SELECT B 9 L H L H X5 INPUTS C L H H L X6 6 ENABLE L H H H X7 PIN 16 = VCC H X X X NONE PIN 8 = GND Figure 1. MC74HC4851A Logic Diagram Single−Pole, 8−Position Plus Common Off X4 VCC VCC X2 X1 X0 X3 A B C 116 X6 215X2 1615 14 13 12 11 10 9 X 314X1 X7 413X0 GND X5 512X3 ENABLE 611A N 710B 12 345678 C 89 X4 X6 X X7 X5 Enable NC GND GND C Figure 2. MC74HC4851A 16−Lead Pinout (Top View) Figure 3. MC74HC4851A QFN Pinout

FUNCTION TABLE − MC74HC4852A

Control Inputs Select Enable BA ON Channels 12 X0 L L L Y0 X0 14 X1 13 L L H Y1 X1 15 X SWITCH X X2 L H L Y2 X2 11 X3 L H H Y3 X3 ANALOG COMMON H X X NONE INPUTS/OUTPUTS 1 OUTPUTS/INPUTS Y0 X = Don’t Care 5 3 Y1 Y 2 Y SWITCH Y2 4 Y3 VCC X2 X1 X X0 X3 A B 10 CHANNEL‐SELECT A 1615 14 13 12 11 10 9 9 PIN 16 = V INPUTS B CC PIN 8 = GND 6 ENABLE

Figure 4. MC74HC4852A Logic Diagram Double−Pole, 4−Position Plus Common Off 12 345678 Y0 Y2 Y Y3 Y1 Enable NC GND Figure 5. MC74HC4852A 16−Lead Pinout (Top View)

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol Parameter Value Unit This device contains protection circuitry to guard against damage VCC Positive DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V due to high static voltages or electric Vin DC Input Voltage (Any Pin) (Referenced to GND) –0.5 to VCC + 0.5 V fields. However, precautions must be taken to avoid applications of any I DC Current, Into or Out of Any Pin ±25 mA voltage higher than maximum rated PD Power Dissipation in Still Air, SOIC Package† 500 mW voltages to this high−impedance cir- TSSOP Package† 450 cuit. For proper operation, Vin and Vout should be constrained to the Tstg Storage Temperature Range –65 to +150 °C range GND v (Vin or Vout) v VCC. TL Lead Temperature, 1 mm from Case for 10 Seconds °C Unused inputs must always be SOIC or TSSOP Package 260 tied to an appropriate logic voltage level (e.g., either GND or VCC). Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of Unused outputs must be left open. these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/°C from 65° to 125°C TSSOP Package: −6.1 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit

VCC Positive DC Supply Voltage (Referenced to GND) 2.0 6.0 V

Vin DC Input Voltage (Any Pin) (Referenced to GND) GND VCC V

VIO* Static or Dynamic Voltage Across Switch 0.0 1.2 V

TA Operating Temperature Range, All Package Types –55 +125 °C

tr, tf Input Rise/Fall Time VCC = 2.0 V 0 1000 ns (Channel Select or Enable Inputs) VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. *For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Guaranteed Limit VCC Symbol Parameter Condition V −55 to 25°C ≤85°C ≤125°C Unit

VIH Minimum High−Level Input Voltage, Ron = Per Spec 2.0 1.50 1.50 1.50 V Channel−Select or Enable Inputs 3.0 2.10 2.10 2.10 4.5 3.15 3.15 3.15 6.0 4.20 4.20 4.20

VIL Maximum Low−Level Input Voltage, Ron = Per Spec 2.0 0.50 0.50 0.50 V Channel−Select or Enable Inputs 3.0 0.90 0.90 0.90 4.5 1.35 1.35 1.35 6.0 1.80 1.80 1.80

Iin Maximum Input Leakage Current on Digital Pins Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA (Enable/A/B/C)

ICC Maximum Quiescent Supply Current Vin(digital) = VCC or GND 6.0 2 20 40 mA (per Package) Vin(analog) = GND

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DC CHARACTERISTICS — Analog Section Guaranteed Limit ° ≤ ° ≤ ° Symbol Parameter Condition VCC −55 to 25 C 85 C 125 C Unit

Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to 2.0 1700 1750 1800 W GND (Note 1); IS ≤ 2.0 mA 3.0 1100 1200 1300 (Note 2) 4.5 550 650 750 6.0 400 500 600

DRon Delta “ON” Resistance Vin = VIL or VIH; VIS = VCC/2 2.0 300 400 500 W (Note 1); IS ≤ 2.0 mA (Note 2) 3.0 160 200 240 4.5 80 100 120 6.0 60 80 100

Ioff Maximum Off−Channel Leakage Current, Vin = VCC or GND mA Any One Channel 6.0 ±0.1 ±0.1 ±0.1 Common Channel ±0.1 ±0.1 ±0.1

Ion Maximum On−Channel Leakage Vin = VCC or GND mA Channel−to−Channel 6.0 ±0.1 ±0.1 ±0.1

1. VIS is the input voltage of an analog I/O pin. 2. IS is the currebnt flowing in or out of analog I/O pin.

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol Parameter VCC −55 to 25°C ≤85°C ≤125°C Unit

tPHL, Maximum Propagation Delay, Analog Input to Analog Output 2.0 160 180 200 ns tPLH 3.0 80 90 100 4.5 40 45 50 6.0 30 35 40

tPHL, Maximum Propagation Delay, Enable or Channel−Select to Analog Output 2.0 260 280 300 ns tPHZ,PZH 3.0 160 180 200 tPLH, 4.5 80 90 100 tPLZ,PZL 6.0 78 80 80

Cin Maximum Input Capacitance Digital Pins 10 10 10 pF (All Switches Off) Any Single Analog Pin 35 35 35 (All Switches Off) Common Analog Pin 40 40 40

CPD Power Dissipation Capacitance Typical 5.0 20 pF

INJECTION CURRENT COUPLING SPECIFICATIONS (VCC = 5V, TA = −55°C to +125°C) Symbol Parameter Condition Typ Max Unit

VDout Maximum Shift of Output Voltage of Enabled Analog Channel Iin* ≤ 1 mA, RS ≤ 3,9 kW 0.1 1.0 mV Iin* ≤ 10 mA, RS ≤ 3,9 kW 1.0 5.0 Iin* ≤ 1 mA, RS ≤ 20 kW 0.5 2.0 Iin* ≤ 10 mA, RS ≤ 20 kW 5.0 20

* Iin = Total current injected into all disabled channels.

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1100 1100 1000 1000 900 900 -55°C 800 800 +25°C 700 700 +125°C 600 600 500 500 -55°C 400 400 +25°C , ON RESISTANCE (OHMS) , ON RESISTANCE , ON RESISTANCE (OHMS) , ON RESISTANCE 300 300

on °

on +125 C R R 200 200 100 100 0 0 0.0 0.4 0.8 1.2 1.6 2.0 0.0 0.6 1.2 1.8 2.4 3.0

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 6. Typical On Resistance VCC = 2V Figure 7. Typical On Resistance VCC = 3V

660 440 600 400 540 360 480 320 -55°C 420 280 +25°C 360 -55°C 240 +125°C 300 200 +25°C 240 +125°C 160 , ON RESISTANCE (OHMS) , ON RESISTANCE , ON RESISTANCE (OHMS) , ON RESISTANCE 180 120 on on R R 120 80 60 40 0 0 0.0 0.9 1.8 2.7 3.6 4.5 0.0 1.2 2.4 3.6 4.8 6.0

Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND

Figure 8. Typical On Resistance VCC = 4.5V Figure 9. Typical On Resistance VCC = 6V

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External DC P.S. Vin2 / Iin2 meas. here. VCC = 5 V

Current Source 4 16 HP4155C Smu #2 X7

Vin1 = 4.9 V (Smu3) RS X0 13 3 X Vout Iin1 measure here Vm1 connected here. Vm2 connected here.

6 NOTES: Rs = 3.9 KW or 20 KW. 8 NOTES: Vm1 & Vm2 are internal NOTES: HP4155C Voltmeters.

GND or VSS

Figure 10. Injection Current Coupling Specification

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5V 6V 5V VCC

VCC HC4051A Microcontroller Sensor Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 (8x Identical Circuitry) Common Out A/D - Input

Figure 11. Actual Technology Requires 32 passive components and one extra 6V regulator to suppress injection current into a standard HC4051 multiplexer

5V VCC

VCC HC4851A Microcontroller Sensor Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 (8x Identical Circuitry) Common Out A/D - Input

Figure 12. MC74HC4851A Solution Solution by applying the HC4851A multiplexer

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PLOTTER VCC

PROGRAMMABLE V POWER MINI COMPUTER DC ANALYZER 16 CC SUPPLY VEE OFF - + A VCC VCC NC OFF COMMON O/I DEVICE UNDER TEST

VIH 6 ANALOG IN COMMON OUT 8

GND

Figure 14. Maximum Off Channel Leakage Current, Figure 13. On Resistance Test Any One Channel, Test Set−Up Set−Up

VCC

VCC VCC VCC V 16 A 16 EE ANALOG I/O OFF ON V A N/C CC VEE COMMON O/I OFF COMMON O/I OFF VCC ANALOG I/O

VIH 6 VIL 6

8 8

Figure 15. Maximum Off Channel Leakage Current, Figure 16. Maximum On Channel Leakage Current, Common Channel, Test Set−Up Channel to Channel, Test Set−Up

VCC VCC 16 VCC ON/OFF COMMON O/I CHANNEL TEST 50% ANALOG I/O SELECT POINT OFF/ON GND CL*

tPLH tPHL

6 ANALOG 50% OUT 8

CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 17. Propagation Delays, Channel Select Figure 18. Propagation Delay, Test Set−Up Channel to Analog Out Select to Analog Out

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VCC 16 COMMON O/I ANALOG I/O TEST VCC ON ANALOG POINT IN 50% CL* GND tPLH tPHL 6

ANALOG 8 OUT 50%

*Includes all probe and jig capacitance

Figure 19. Propagation Delays, Analog In Figure 20. Propagation Delay, Test Set−Up to Analog Out Analog In to Analog Out

tf tr POSITION 1 WHEN TESTING tPHZ AND tPZH V 1 POSITION 2 WHEN TESTING tPLZ AND tPZL 90% CC ENABLE 50% 2 V 10% CC GND W VCC 16 10k tPZL tPLZ HIGH 1 ANALOG I/O IMPEDANCE ON/OFF TEST ANALOG 50% 2 POINT OUT 10% CL* VOL t t PZH PHZ ENABLE 6 90% VOH ANALOG OUT 50% 8 HIGH IMPEDANCE Figure 21. Propagation Delays, Enable to Figure 22. Propagation Delay, Test Set−Up Analog Out Enable to Analog Out

VCC

VCC A 16 COMMON O/I NC ANALOG I/O

VCC 6

8 11

CHANNEL SELECT

Figure 23. Power Dissipation Capacitance, Test Set−Up

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Gate = VCC Disabled Analog Mux Input (Disabled) Common Analog Output Vin > VCC + 0.7V Vout > VCC

P+ P+ + + +

N - Substrate (on VCC potential)

Figure 24. Diagram of Bipolar Coupling Mechanism Appears if Vin exceeds VCC, driving injection current into the substrate

11 A INJECTION 13 CURRENT X0 CONTROL

INJECTION 14 10 CURRENT X1 B CONTROL

INJECTION 15 CURRENT X2 CONTROL

INJECTION 12 CURRENT X3 CONTROL 9 C INJECTION 1 CURRENT X4 CONTROL

INJECTION 5 6 CURRENT X5 ENABLE CONTROL

INJECTION 2 CURRENT X6 CONTROL

INJECTION 4 CURRENT X7 CONTROL

INJECTION 3 CURRENT X CONTROL

Figure 25. Function Diagram, HC4851A

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10 A INJECTION 13 CURRENT X0 CONTROL

INJECTION 14 9 CURRENT X1 B CONTROL

INJECTION 1315 CURRENT X2 CONTROL

INJECTION 12 CURRENT X3 CONTROL

INJECTION 3 CURRENT X CONTROL

INJECTION 1 CURRENT Y0 CONTROL

INJECTION 5 CURRENT Y1 CONTROL 6 ENABLE INJECTION 2 CURRENT Y2 CONTROL

INJECTION 4 CURRENT Y3 CONTROL

INJECTION 3 CURRENT Y CONTROL

Figure 26. Function Diagram, HC4852A

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ORDERING INFORMATION

Device Package Shipping† MC74HC4851ADG 48 Units / Rail SOIC−16 MC74HC4851ADR2G 2500 Units / Tape & Reel (Pb−Free) NLVHC4851ADR2G* 2500 Units / Tape & Reel

MC74HC4851ADTR2G TSSOP−16 2500 Units / Tape & Reel NLVHC4851ADTR2G* (Pb−Free)

MC74HC4851ADWR2G SOIC−16 WIDE 1000 Units / Tape & Reel NLVHC4851ADWR2G* (Pb−Free)

NLV74HC4851AMNTWG*# QFN16 3000 Units / Tape & Reel NLV74HC4851AMN1TWG*# (Pb−Free) 3000 Units / Tape & Reel

MC74HC4852ADG 48 Units / Rail SOIC−16 MC74HC4852ADR2G 2500 Units / Tape & Reel (Pb−Free) NLV74HC4852ADR2G* 2500 Units / Tape & Reel

MC74HC4852ADTR2G TSSOP−16 2500 Units / Tape & Reel NLVHC4852ADTR2G* (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. #MN suffix is with pull−back lead, MN1 is without pull−back lead. Refer to ’Detail A’ of case outline on page 16.

www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS

QFN16, 2.5x3.5, 0.5P CASE 485AW−01 1 ISSUE O DATE 11 DEC 2008 SCALE 2:1

NOTES: D A 1. DIMENSIONING AND TOLERANCING PER B L L ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS b APPLIES TO PLATED PIN ONE TERMINAL AND IS MEASURED BETWEEN REFERENCE L1 0.15 AND 0.30 MM FROM TERMINAL.

ÉÉÉ 4. COPLANARITY APPLIES TO THE EXPOSED DETAIL A PAD AS WELL AS THE TERMINALS. ÉÉÉ ALTERNATE TERMINAL MILLIMETERS CONSTRUCTIONS DIM MIN MAX

ÉÉÉ E A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF EXPOSED Cu MOLD CMPD b 0.20 0.30

2X 0.15 C ÇÇÇ D 2.50 BSC

D2 0.85 1.15 ÇÇÇ ÉÉÉ E 3.50 BSC 2X 0.15 C TOP VIEW E2 1.85 2.15

ÉÉÉDETAIL B e 0.50 BSC ALTERNATE K 0.20 --- A CONSTRUCTIONS DETAIL B L 0.35 0.45 0.10 C (A3) L1 --- 0.15 A1 GENERIC MARKING 16X 0.08 C DIAGRAM* NOTE 4 XXXX C SEATING SIDE VIEW PLANE ALYWG G 0.15 C A B XXXX = Specific Device Code D2 A = Assembly Location 16X L K 8 L = Wafer Lot Y = Year 10 0.15 C A B DETAIL A W = Work Week G = Pb−Free Package E2 (Note: Microdot may be in either location) *This information is generic. Please refer to 16X b device data sheet for actual part marking. 2 0.10 C A B Pb−Free indicator, “G” or microdot “ G”, 15 0.05 C may or may not be present. 1 NOTE 3 e SOLDERING FOOTPRINT* e/2 3.80 BOTTOM VIEW 2.10

0.50 PITCH 2.80 1.10

1 PACKAGE 16X 16X OUTLINE 0.60 0.30 DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98AON36347E Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: QFN16, 2.5X3.5, 0.5P PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

SOIC−16 CASE 751B−05 ISSUE K SCALE 1:1 DATE 29 DEC 2006 −A− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. −B− P 8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION M S 180.25 (0.010) B SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES DIM MIN MAX MIN MAX G A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F F 0.40 1.25 0.016 0.049 K R X 45_ G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 C K 0.10 0.25 0.004 0.009 M 0 ____ 7 0 7 −T− SEATING P 5.80 6.20 0.229 0.244 PLANE M J R 0.25 0.50 0.010 0.019 D 16 PL 0.25 (0.010)M T B S A S

STYLE 1: STYLE 2: STYLE 3: STYLE 4: PIN 1. COLLECTOR PIN 1. CATHODE PIN 1. COLLECTOR, DYE #1 PIN 1. COLLECTOR, DYE #1 2. BASE 2. ANODE 2. BASE, #1 2. COLLECTOR, #1 3. EMITTER 3. NO CONNECTION 3. EMITTER, #1 3. COLLECTOR, #2 4. NO CONNECTION 4. CATHODE 4. COLLECTOR, #1 4. COLLECTOR, #2 5. EMITTER 5. CATHODE 5. COLLECTOR, #2 5. COLLECTOR, #3 6. BASE 6. NO CONNECTION 6. BASE, #2 6. COLLECTOR, #3 7. COLLECTOR 7. ANODE 7. EMITTER, #2 7. COLLECTOR, #4 8. COLLECTOR 8. CATHODE 8. COLLECTOR, #2 8. COLLECTOR, #4 9. BASE 9. CATHODE 9. COLLECTOR, #3 9. BASE, #4 10. EMITTER 10. ANODE 10. BASE, #3 10. EMITTER, #4 11. NO CONNECTION 11. NO CONNECTION 11. EMITTER, #3 11. BASE, #3 12. EMITTER 12. CATHODE 12. COLLECTOR, #3 12. EMITTER, #3 13. BASE 13. CATHODE 13. COLLECTOR, #4 13. BASE, #2 14. COLLECTOR 14. NO CONNECTION 14. BASE, #4 14. EMITTER, #2 SOLDERING FOOTPRINT 15. EMITTER 15. ANODE 15. EMITTER, #4 15. BASE, #1 8X 16. COLLECTOR 16. CATHODE 16. COLLECTOR, #4 16. EMITTER, #1 6.40

STYLE 5: STYLE 6: STYLE 7: 16X 1.12 PIN 1. DRAIN, DYE #1 PIN 1. CATHODE PIN 1. SOURCE N‐CH 2. DRAIN, #1 2. CATHODE 2. COMMON DRAIN (OUTPUT) 1 16 3. DRAIN, #2 3. CATHODE 3. COMMON DRAIN (OUTPUT) 4. DRAIN, #2 4. CATHODE 4. GATE P‐CH 5. DRAIN, #3 5. CATHODE 5. COMMON DRAIN (OUTPUT) 16X 6. DRAIN, #3 6. CATHODE 6. COMMON DRAIN (OUTPUT) 0.58 7. DRAIN, #4 7. CATHODE 7. COMMON DRAIN (OUTPUT) 8. DRAIN, #4 8. CATHODE 8. SOURCE P‐CH 9. GATE, #4 9. ANODE 9. SOURCE P‐CH 10. SOURCE, #4 10. ANODE 10. COMMON DRAIN (OUTPUT) 11. GATE, #3 11. ANODE 11. COMMON DRAIN (OUTPUT) 12. SOURCE, #3 12. ANODE 12. COMMON DRAIN (OUTPUT) 13. GATE, #2 13. ANODE 13. GATE N‐CH 1.27 14. SOURCE, #2 14. ANODE 14. COMMON DRAIN (OUTPUT) PITCH 15. GATE, #1 15. ANODE 15. COMMON DRAIN (OUTPUT) 16. SOURCE, #1 16. ANODE 16. SOURCE N‐CH 89

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42566B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOIC−16 PAGE 1 OF 1

SOIC−16 WB CASE 751G−03 ISSUE D DATE 12 FEB 2013 1 SCALE 1:1

D A q NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 16 9 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. M 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

B 5. DIMENSION B DOES NOT INCLUDE DAMBAR

_ PROTRUSION. ALLOWABLE DAMBAR H

M PROTRUSION SHALL BE 0.13 TOTAL IN E X 45 8X EXCESS OF THE B DIMENSION AT MAXIMUM

h MATERIAL CONDITION. 0.25 MILLIMETERS DIM MIN MAX 1 8 A 2.35 2.65 A1 0.10 0.25 16X B B B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 M S S 0.25T A B E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0 _ 7 _ A L

14X GENERIC e C SEATING MARKING DIAGRAM* A1 T PLANE 16

SOLDERING FOOTPRINT XXXXXXXXXXX 16X 0.58 XXXXXXXXXXX AWLYYWWG

XXXXX = Specific Device Code 11.00 A = Assembly Location WL = Wafer Lot 1 YY = Year WW = Work Week G = Pb−Free Package 16X *This information is generic. Please refer to 1.62 1.27 PITCH device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, DIMENSIONS: MILLIMETERS may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42567B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SOIC−16 WB PAGE 1 OF 1

TSSOP−16 CASE 948F−01 16 ISSUE B DATE 19 OCT 2006 1 SCALE 2:1

16X K REF NOTES: 0.10 (0.004)M T U S V S 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 0.15 (0.006) T U S K 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD K1 FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT ÉÉÉ 16 9 ÇÇÇ EXCEED 0.15 (0.006) PER SIDE. 2X L/2 J1 4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION. ÉÉÉ ÇÇÇ INTERLEAD FLASH OR PROTRUSION SHALL B SECTION N−N NOT EXCEED 0.25 (0.010) PER SIDE. L 5. DIMENSION K DOES NOT INCLUDE DAMBAR −U− J PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL PIN 1 IN EXCESS OF THE K DIMENSION AT IDENT. N MAXIMUM MATERIAL CONDITION. 1 8 0.25 (0.010) 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE M DETERMINED AT DATUM PLANE −W−. 0.15 (0.006) T U S A MILLIMETERS INCHES N DIM MIN MAX MIN MAX −V− A 4.90 5.10 0.193 0.200 F B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 DETAIL E D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 C −W− J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 0.10 (0.004) K1 0.19 0.25 0.007 0.010 H DETAIL E L 6.40 BSC 0.252 BSC −T− SEATING ____ PLANE D G M 0 8 0 8

GENERIC SOLDERING FOOTPRINT MARKING DIAGRAM* 7.06 16 XXXX 1 XXXX ALYW 1

XXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year 0.65 W = Work Week PITCH G or G = Pb−Free Package

*This information is generic. Please refer to device data sheet for actual part marking. 16X 16X 0.36 Pb−Free indicator, “G” or microdot “ G”, 1.26 DIMENSIONS: MILLIMETERS may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASH70247A Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: TSSOP−16 PAGE 1 OF 1

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