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Design of Cardic Processor Efficiently by Usingverilog Hdl K ISSN 2277-2685 IJESR/October 2014/ Vol-4/Issue-10/762-766 K. Spoorthi et al./ International Journal of Engineering & Science Research DESIGN OF CARDIC PROCESSOR EFFICIENTLY BY USINGVERILOG HDL K. Spoorthi*1, Syed Jalal Ahmed 2 1M.Tech Scholar, Department of ECE, JBIET, Hyderabad, TS, India 2Assoc. Prof, Department of ECE, JBIET, Hyderabad, TS, India ABSTRACT In this paper, the efficacy of this approach is studied for the implementation on FPGA. For this study, both non pipelined and 2 level pipelined CORDIC with 8 stages and using two schemes–one using adders in all the stages and another using multiplexers in the second and third stages. In the literature, multiplexer has been proposed for the ASIC implementation of unrolled CORDIC (Coordinate Rotation Digital Computer) processor. A 16 bit CORDIC for generating the sine/cosine functions is implemented using all the four schemes on both Xilinx Virtex 6 FPGA(XC6VLX240) and Altera Cyclone II FPGA(EP2C20F484C7). From the implementation results, it is found that the non-pipelined and pipelined CORDICs using multiplexer requires 1.6, 1.4 times lower area in Xilinx FPGA and 1.8, 1.6 times lower area in Altera FPGA than that using only adders. This is achieved without reduction in speed. CORDIC unit uses only shifts and adds to perform a wide range of functions including vector rotations, certain trigonometric, hyperbolic, linear and logarithmic functions. It is used in diverse applications such as mathematical coprocessor units, calculators, waveform generators, universal modulator, demodulator digital filters carrier as well as bit time recovery circuits and digital modems. CORDIC algorithm is very well suited for VLSI implementation. Extension: The scheme for reducing the area of the CORDIC using multiplexer is proposed. The area is reduced by removing some of the stages in the proposed work. Extension to this work in the future would involve study and implementation of different architectures of CORDIC. Languages Used: Verilog HDL Tools Required: XILINX 13.2. 1. INTRODUCTION All of the trigonometric functions can be computed or derived from functions using vector rotations, as will be discussed in the following sections. Vector rotation can also be used for polar to rectangular and rectangular to polar conversions, for vector magnitude, and as a building block in certain transforms such as the DFT and DCT. The CORDIC algorithm provides an iterative method of performing vector rotations by arbitrary angles using only shifts and adds. The algorithm, credited to Volder, is derived from the general rotation transform. The block diagram of unrolled CORDIC with 8 stages even though adders and shifters were originally used for the implementation of CORDIC, a novel scheme which uses multiplexer (MUX) for few stages of unrolled CORDIC is proposed [1-3] and is studied by implementation on ASIC. In this scheme, the first stage is removed and adders at the 2nd and 3rd stages are replaced by multiplexers. This methodology achieves less area compared to original unrolled CORDIC. FPGAs such as Virtex 6 and Cyclone II have fixed logic blocks which contain various functional blocks such as look up tables, fast carry logic and flip flops [5]. The objective of this paper is to study how an FPGA based unrolled CORDIC using multiplexer performs compared to those using adders. 2. OVERVIEW OF CORDIC ALGORITHM The CORDIC algorithm is an iterative method ofperforming vector rotations by arbitrary angles usingshifts and adds. In the rotation mode, CORDIC may beused for converting a vector in polar form to rectangularform. In *Corresponding Author www.ijesr.org 762 K. Spoorthi et al./ International Journal of Engineering & Science Research the vector mode, it converts a vector inrectangular form to polar form. Both the modes arederived from the general rotation transform [3]. Equation (1) and (2) rotates a vector in a Cartesian plane by an angle θ to another vector with the coordinates . The rotation may be achieved by performing a series of successively smaller elementaryrotations . Rotation of the vector by an angle can be rewritten as The computational complexity of (5), (6) can be reduced by rewriting these equations as To get the final coordinate values, we should perform divide by . The value of for i=0,1,2,…,N is chosen such that tan is . This reduces the multiplication by the tan to simple shift operation.As the iteration increases, becomes smaller and smaller [2]. We may terminate the iteration when the differencebetween θ = becomes very small for some value of N. The remaining angle by which the vector needs to be rotated after completion of i iterations is indicated by the parameter and is defined by (10) is considered to be positive when the rotation required is anticlockwise and is negative otherwise. The direction of this rotation depends on the The computation of may be simplified as follows: Since cos =1 for very smaller values of , may be computed for N=8 and may be used for any value of N>8. Copyright © 2013 Published by IJESR. All rights reserved 763 K. Spoorthi et al./ International Journal of Engineering & Science Research Fig 1: An example of three vector rotations, corresponding to a three stage CORDIC The vector vi gives the approximated values of sine and cosine after three rotations. All equations of CORDIC algorithm can be implemented by only additions, subtractions and shifts; therefore CORDIC algorithm does not require multipliers. 3. UNROLLED CORDIC IN ROTATION MODE In rotation mode, CORDIC can simultaneously compute the sine and cosine of the input angles. In this mode, we set the y component of the input vector to zero, x component to 1/k and the angle accumulator is initialized with the desired rotation angle θ [5]. The output of angle accumulator decreases or increases depending on the most significant bit of the output of the previous stage. Fig 2: Block Diagram of CORDIC CORDIC is used for converting a vector in polar form to rectangular form. It is very well suited for VLSI implementation. Even though adders and shifters were originally used for the implementation of CORDIC, a novel scheme which uses multiplexer (MUX) for few stages of unrolled CORDIC is proposed [6]. Even though adders and shifters were originally used for the implementation of CORDIC, a novel scheme which uses multiplexer (MUX) for few stages of unrolled CORDIC is proposed. In this scheme, the first stage is removed and adders at the 2nd and 3rd stages are replaced by multiplexers. Copyright © 2013 Published by IJESR. All rights reserved 764 K. Spoorthi et al./ International Journal of Engineering & Science Research Fig 3: The circuit of second stage using Mux with MSB select line A 16 bit CORDIC for generating the sine/cosine functions with and without two level pipelining are implemented using both MUX based approach and also one using shifters and adders.The scheme for reducing the area of the CORDIC using multiplexer is proposed for the ASIC implementation. The output of the second stage is fixed. So we can implement the second stage using two MUX’s and choosing select line as the MSB bit of the previous angle accumulator output. Table 1: Multiplexes required for eliminating different stages The pipelined CORDIC use registers in between each iteration stage. The advantage of pipelined unrolled CORDIC over the unrolled CORDIC is its higher frequency of operation. This property can be used in high speed applications. The number of registers depends on the number of stages in pipelining and there will be an increase in area. The advantage ofpipelined unrolled CORDIC over the unrolled CORDIC isits higher frequency of operation. This property can be usedin high speed applications. The number of registers dependson the number of stages in pipelining and there will be anincrease in area. The first output of an N-stage pipelinedCORDIC core is obtained after N clock cycles. Thereafter,outputs will be generated during every clock cycle. In thispaper, pipelined registers are placed after fourth and seventhstages. 4. RESULTS A 16 bit CORDIC for generating the sine/cosine functions with and without two level piplining are implemented using both mux based aproach and also one using shifters and adders. The implementation resuls on Xilinx Virtex 6 FPGA (XC6VLX240) and Altera Cyclone. II FPGA (EP2C20F484C7 devices. It is found that the nonpipelined and pipelined CORDICs using multiplexer requires 1.6, 1.4 times lower area in Xilinx Virtex 6 FPGA and 1.8, 1.6 times lower area in Altera cyclone II than that using only adders. This is achieved without reduction in speed. Table 2: Implementation results of Xlilnx virtex 6 FPGA Copyright © 2013 Published by IJESR. All rights reserved 765 K. Spoorthi et al./ International Journal of Engineering & Science Research Table 3: Implementation results on Altera cyclone II FPGA The Implementation statistical result of all the four schemeson Xilinx Virtex 6 is represented in column chart. 5. CONCLUSION A 16 bit CORDIC for generating the sine/cosine functions with and without two level pipelining are implemented using both MUX based approach and also one using shifters and adders. This is achieved without reduction in speed. REFERENCES [1] Volder JE. The CORDIC Trigonometric Computing Technique. IRE Transactions on Electroni computer 1959; EC-8: 330-334. [2] Walther J. A unified algorithm for elementary functions. Proc. Spring Joint Comp. Con 1971; 38: 379-385 [3] Nilsson P. Complexity reduction in unrolled CORDIC architectures. Electronics, circuits, and systems. ICECS 2009; 868-871. [4] Vankka J, Kosunen M, Hubach J, Halonen K.. A CORDICbased multicarrier QAM modulator. Global Telecommunications Conference. GLOBECOM' 1999; 1: 173-177. [5] Chen A, McDanell R, Boytim M, Pogue R. Modified CORDIC demodulator implementation for digital IF- sampled receiver. Global Telecommunications Conference GLOBECOM 1995; 2: 1450-1454.
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