Decoder B Select -*~ Multiplexer ,1 1 Multiplexer [-*-A Select B Bus -- 4 a Bus Destination Select ALU Function Select

Tele 2060

A Simple Processor Architecture

Decoder B Select -*~ Multiplexer ,1 1 Multiplexer [-*-A Select B Bus -- 4 A Bus Destination Select ALU Function Select

Shifter Shift Select Output Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design -1 University of' Pittsburgh

Tele 2060 ALU

Performs.Arithmentic Functions Performs Logic Functions Function is Selected by Control Status Bits o C - Carry o V - Overflow o Z = I If Resultant Contains All Zeros o S - Sign Bit of the Result Decoder Selects Destination for the Resultant

Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 2 University of Pittsburgh Tele 2060 ALU

Inputs o Operands o Input Carry o Operation Select o Add o Subtract o AND v OR o XOR o Mode (Arithmetic or Logic) Select Outputs o Resultant o Output Carry

Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 3 University of Pittsburgh

Tele 2060 ALU Function Table

Operation Select S2 S1 SO Cin Operation Function 0 0 0 0 F=A Transfer A 0 0 0 1 F=A+1 Increment A 0 0 1 0 F=A+B Add A and B 0 0 1 1 F=A+B+1 Add A and B With Carry 0 1 0 0 F=A+B' Add A and One's Compement of B 0 1 0 1 F=A+B'+1 Subtract B From A 0 1 1 0 F=A-1 Decrement A 0 1 1 1 F=A Transfer A 1 0 0 0 F=AB AND 1 0 1 0 F=A+B OR 1 1 0 0 F=A XOR B Exclusive OR 1 1 1 0 F=A' Complement

Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 4 1Iniversity of Pittsburgh Tele 2060 ALU Components

" Arithmetic o Parallel Add o One Full Adder per Bit o Selection Logic " Logic o Gates o Multiplexer

Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 5 University «f Pittsburgh

Tele 2060

Arithmetic-Logic Unit and Processor Design - 6 University of Pittsburgh Tele 2060

Arithmetic-Logic Unit and Processor Design - 7 University of Pittsburgh

Tele 2060 Internal Structure of ALU

Cn-1

Multiplexer

Stage

So S1 S2

Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 8 University o(' Pittsburgh

Tele 2060 Shifter

General o Extension of Shift Register Circuit is Possible o This Requires Several Clock Pulses o This is Time Consuming Alternate Approach (Figure 7-18, p. 246 of Mano) o Use Multiplexers o Wire to Cause Shift Effect o Control Determines Nature of Shift o Thus, a Single Clock Cycle is Used

Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 9 University of Pittsburgh Tele 2060 Control Unit Requirements

" MUX A Selector " MUX B Selector " ALU Operation Selector " Shift Selector " Destination Selector

Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design -10 University Of Pittsburgh Tele 2060 Control Word

" Number and Organization of Bits Required to Control ALU " Bit Requirements o A: A Bus Select (Seven Registers Plus Input) : 3 bits o B: B Bus Select (Seven Registers Plus Input) : 3 bits o D: Destination Select (Seven Registers): 3 bits o F: ALU Control (Four bits) o H: Shift Control (Three bits) o TOTAL =16 bits o Thus, 16 Bits Can Be Used to Perform All Microoperations

Martin B.H. Weiss Tele 2060 Control Word Encoding

0 Operation (F) Code Cin = 0 Cin =1 A B D H 0 0 0 F=A F=A+1 Input Input None No Shift 001 F=A+B F=A+B+1 R1 R1 R1 SHL 010 F=A+B' F=A+B'+1 R2 R2 R2 SHR 011 F=A-1 F=A R3 R3 R3 Bus=O 100 F=AB R4 R4 R4 101 F=A+B R5 R5 R5 ROL 110 F=A XOR B R6 R6 R6 ROR 111 F=A' R7 R7 R7

Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design -12 University of Pittsburgh Tele 2060 Microoperations and Microprograms

Example Microoperation o RV- R2 - R3 o Symbolically: R2,R3,R1,F=A-B,No Shift o Control Word = 010 0110010101000 = 4CA8 (H) Clearly, Many Microoperations Are Possible Control Memory o Location of Available Microoperations o Width of Control Memory = Control Word Microprograms Can be Written Using a Sequence of Microoperations

Martin B.H. Weiss Tele 2060 Addressing Modes

Direct o the address is contained in the address field o the size of the memory is limited by the size of the address field Indirect o Content of the Memory Location Contained in the Address Field Points to The Actual Address o Allows for a Larger Memory Because the Address Fields Can Be Larger o Allows for Efficient Address Manipulation Indexed o Content of the Memory Field is Added to the Contents of the Index Register o Allows for Flexible Relative Addressing Martin B.H. Weiss Tele 2060 Control System Design

" A Programmer Needs a Logical Structure and Instructions " A Hardware Designer has Microoperations " The Bridge Between These is a Microprogram

Martin B.H. Weiss Computer Organization - 10 University of Pittsburgh Tele 2060 Structure of a Microprogrammed Control Unit

Control Input Word Next Control Control Control 10. Address Address Memory Data Generator Register (ROM) Register

Martin B.H. Weiss Computer Organization - 11 University of Pittsburgh

Tele 2060 Example

" General o 16 Bits for Processor Control (Bits 1-16; A,B,D,F,H As Before) o One Bit for Address Source Selection (bit 17) o Three Bits For Status Bit Select (Bits 18-20) o Six Bits for the Next Address (Bits 21-26) " 26=64 Microinstructions Are Possible " CAR Can be Loaded or Incremented, Depending on the Condition

Martin B.H. Weiss Computer Organization - 12 University of Pittsburgh

Tele 2060

Example

1-16

Control ,, Control 17 Mux Address Memory no Register 18-20 External Address I I 1 1 21-26

Incre-I Load ment Input Control * Data Word Multiplexer 01CC'ZZ'SV Processor Unit

j' Output Data Martin B.H. Weiss Computer Organization - 13 University of Pittsburgh

Tele 2060 A Simple Computer Design

Clock

CPU Memory E:3~1iE3

Interrupt

Read/Write

Martin B.H. Weiss Computer Organization -14 University of Pittsburgh Tele 2060 A Simple Computer Design

" I/O Interface " 16 Bit Data Bus " 16 Bit Address Bus

Martin B.11. Weiss Computer Organization - 15 Universitv of 1'itttihnrgh Tele 2060 CPU Components

Input _V Desti- nation Fourteen Registers Decoder (16 Bits) s s

ALSU V S Z C (16 Bits)

Output

Martin B.H. Weiss Computer Organization -16 University of Pittsburgh Tele 2060 CPU Components

" ALSU " Registers " Internal Busses " Status Bits

Martin B.H. Weiss Computer Organization -17 University of Pittsburgh Tele 2060 ALSU

" Two 16 Bit Input Busses " Four Units Multiplexed Together " Each Unit Always Operates on Both Operands " The Operation is Determined by the Selection Lines So and Sl " Operation is Selected by a 4:1 Multiplexer (S2 and S) " 16 Operations are Possible on the Output " Example 0110 => F=A B " Requires a Five Bit Control Word

Martin B.H. Weiss Computer Organization -18

Tele 2060

Computer Organization - 19 University of Pittshorgh Tele 2060 Registers

Fourteen Total Registers PC Six General Purpose Registers Seven Special Purpose Registers o Index Register o Stack Pointer o Source Register o Destination Register o Temporary Register o Two Constant Registers (Zero and N=16)

Martin B.H. Weiss Computer Organization - 20 University of Pittslwrph Tele 2060 Three Internal Busses

" One for Each Operand o Attached to One of the Registers via a Multiplexer o One Mux for Each Operand Bus " One For the Result o Destination is One of the Registers o May Also Be External

Martin B.H. Weiss Computer Organization - 21 University of Pittslatiroh Tele 2060 Control Word

" 17 Bits Long

" Five Bits for ALSU (Four Control + Cin) " Four Bits for Mux A " Four Bits for Mux B " Four Bits for Destination Decoder

Martin B.H. Weiss Computer Organization - 22 University of Pittsburgh Tele 2060

Computer Organization - 23 University of l'ittsliurgh Tele 2060 CPU

Components o Processor Unit o Memory o Control Unit o Buffers/Registers o Busses Busses o External to the Processor o Data Bus (16 bits) u Direction Must be Mediated o Read/Write Line (From/To Memory)) o Address Bus (16 bits)

Martin B.11. Weiss Computer Organization - 24 Tele 2060 CPU Buffers and Registers

" Data Input Register o Input to IR or Processor o Data from Memory or From the Outside World " Data Output Register - Output to Memory or Oustide World " Address Register - Current Memory Address " Instruction Register - OPcode of the Current Instruction

Martin B.H. Weiss Computer Organization - 25 University of Pittsburgh

Tele 2060 Control Unit Organization

SBR Increment

Address MUX CAR Control Memory

IR (8-15) ppcode Map

Martin B .H. Weiss Computer Organization - 26 ITniversity of Pittsburgh Tele 2060 Control Unit

Components o Subroutine Register o OPCode Map o Incrementer o Address Mux o Control Address Register o Control Memory Subroutine Register o Used in Subroutine Call o Stores Return Address

Martin B.I-I. Weiss University or Pittsburgh

Tele 2060 Control Unit

Opcode Map o Maps OPcode Into Control Memory Address o May be a ROM Incrementer - Increments Address Address Mux o Selects Source of Address o Controlled by Control Memory (CS field) Control Address Register - Holds the Memory Address Control Memory - Contains the Microcode

Martin B.H. Weiss Computer Organization - 28 University of Pittsburgh

Tele 2060

Instruction Types

Indirect Bits SI DI Type 0 10 1 o1 'oPCo4e I I SRI I ~st I Register to Register

I Type 1 0 1 O ~o4e S Dial): I I e Memory to Register ~ . . t . . ~...... A4em r d r o *or

Type 2 1 0 O o e 0 0 0 0 0 0 0 0 Branch U,qm- r- d- r- o- Word

Type 3 11 1,,O11 ogle, - 0, 0, 0, 0, 0, 0, 001 Implied

Martin B.II. Weiss Computer Organization - 29 University of Pittsburgh Tele 2060 Type 1

Memory-Register Two Word Instruction (Except for One Operand Instructions with Operand in Register) Format o Bits 0-2: Register o Bit 3: Indirect Bit o Bits 4-5: Addressing Mode o Immediate : W is the Operand o Direct o Indirect o Index o Bit 6-7: Source/Destination and Number of Operands o Memory or Register o One or Two Operands

Martin R.H. Weiss Computer Organization - 31 University of Pittsburgh

Tele 2060 Type 1

" Format o Bits 8-13 : OPCode o Bits 14-15: 01 (Indicates Memory-Register Operation) o Second Word for Memory Address or Intermediate Operand

Martin B.H. Weiss Computer Organization - 32 University of Pittsburgh Tele 2060 Type 2

" Branch " Two Word Instruction " Format o Bits 0-7: 0 o Bits 8-13: OPCode o Bits 14-15: 10 (Indicates Branch Operation) " Second Word Contains the Branch Address

Martin B .H. Weiss

Tele 2060 Type 3

Implied Mode Operand Either Does Not Exist or is Implicit in the Instruction Example: NOP One Word Format o Bits 0-7: 0 o Bits 8-13 : OP code o Bits 14-15: 11

Martin B.H. Weiss Computer Organization - 34 University of Pittsburgh

Tele 2060 An Assembly Language Instruction : ADD

Adds Two Numbers May be Type 0 or Type 1 o Type 0 if the Operands are in Registers o Type 1 if One of Them is in Memory Example of Type 0: ADD R5,R2 o Operation : R2<- R2+R5 o Machine Code (0952H) o Bits 0-2: 010 (Register 2) o Bit 3: Indirect Bit = 0 (Direct) o Bits 4-6: 101 (Register 5) o Bit 7: Indirect Bit = 0 (Direct) o Bits 8-13: OPCode = 001001 o Bits 14-15: 00 (Indicates Register-Register Operation) o Note That All Type 1 ADD Instructions Have 09H As First Byte Martin B.H. Weiss Computer Organization - 35 Tele 2060 Alternate Form of ADD

" If We Used Indirect in R2: ADD R5,(R2) o Operation : M[R2] M[R2]+R5 o Machine Code: o Bits 0-2: 010 (Register 2) o Bit 3: Indirect Bit =1 (Direct) o Bits 4-6: 101 (Register 5) o Bit 7: Indirect Bit = 0 (Direct) o Bits 8-13: OPCode = 001001 o Bits 14-15: 00 (Indicates Register-Register Operation) o Alternatively : 095AH

Martin B.11. 'Weiss Computer Organization - 36 University of Pittsburgh Tele 2060 Example of a Type 1 Addition: ADD TEMP,R2

" R2 I-- R2+M[TEMP] " Machine Code o Bits 0-2: 010 o Bit 3: Indirect bit = 0 o Bits 4-5: Addressing Mode = 00 o Bit 6-7: Source/Destination and Number of Operands 00 o Bits 8-13: OPCode = 001001 o Bits 14-15: 01 " Machine Code: 4902H

Martin B.H. Weiss Tele 2060 Notes

" Many Other Instructions Exist as Well " We Will Examine the Intel 8080 Later " The Software That Translates Assembly Code to Machine is an Assembler

Martin B.H. Weiss Computer Organization - 38 Tele 2060 Microinstructions

23 bits 17 for ALSU o Operand A Select (4) o Operand B Select (4) o Destination Select (4) o ALSU Function Select (5) Six for Other Functions o Two for Control Sequence o Distinguishes Microinstruction Formats o Controls the Address Mux in the Control Unit o Four for Miscellaneous Microoperations

Martin B.H. Weiss Computer Organization - 39 University of Pittsburgh Tele 2060 Example: R2'--R2+R5

Refer to Mano, Figure 10-8(b) (p. 349) Control Sequence (CS) = 00 Register Select "A" (AS) = 0010 Register Select "B" (BS) = 0101 Destination Select (DS) = 0010 Function Control (FC) = 00010 Miscellaneous (MS) = 0000 Hex code: 04A620 Microprograms Map OPcode Semantics into Microoperation Sequences

Martin B .H. Weiss

Tele 2060 Microprogram Flowchart for Type 0 ADD

ADD (Type 0)

Source Source Indirect Direct ARE- R(S) A SRE- R(S)

SRE- DIR

Destination Destination Indirect Direct A R(D) E- SR + R(D)

-- DOR <-4SR + DIR Check forFInterrupt

WRITE and Check for Interrupt

Martin 13 .H. Weiss Computer Organization - 41 University of Pittsburgh Tele 2060 Program Status Word (PSW)

General o Contains Important CPU Status Indications o Need Sufficient Information to Restore Processor Context (Status) Typical Contents o Program Counter o Stack Pointer o Accumulator value o Index Register(s) o Processor Status Register o Instruction Register

Martin 11.11. Weiss Computer Organization - 42 University of Pittsburgh Tele 2060 Stack

" Special Type of Memory " Operations o PUSH o POP

Martin B.H. Weiss Computer Organization - 43 University of Pitifimrgh Tele 2060 Input/Output for Communications

Memory

Is Data Bus Address Bus CPU IMEE=EEEce Control

Interface11011011011Interface Interface Interface

Disk Keyboard Display Storage

Martin B.li. Weiss Computer Organization - 44 University of Pittsburgh Tele 2060 Serial Communications Devices

Transmit Shift Register Control

Address Bus Control Transmit Holding Regi

Data Bus Day Receive Holding Register Buffer ZZZZZZZ IrmkTM-. ve ~nui negis~er

Martin B.H. Weiss Computer Organization - 45 University of Pittsburgh Tele 2060 Computer Architecture - Intel 8080

Defines Only the CPU Physical Features o 40 Pin DIP Package (See Handout) o S Bit Data Bus o 16 Bit Address Bus o Control Pins

Martin B.H. Weiss Computer Organization - 46 University of Pittsburgh

Tele 2060 Logical Features

" 8 Bit ALU " Registers o ACC o PC o Stack Pointer o IR o 6 Working Registers o Used in Pairs o B-C o D-E o H-L 0 2 Temporary Registers Organization (See Handout)

Alai-tin B.H. Weiss Computer Organization - 47 University of Pittsburgh

Tele 2060 Instruction Format

" 8 Bit Opcode " 256 Instructions " 8080 Instructions (See Handout) " 8080 Microinstructions (See Handout)

Martin B.H. Weiss Computer Organization - 48 [University of Pittsburgh Tele 2060 Summary of Digital and Computer Section

" Digital Computers Consist of Sequential and Combinational Circuits " General Purpose Devices That Can Be Programmed " Control is Often Implemented Via Microprograms

High Level Assembly Machine Micro- Electrical Language Code Code Program Signals Code Code

Comb. & Seq. Circuits

Intended Results

Martin B.fi. Weiss Tele 2060

Computer Organization - 50 University of Pittsburgh