Tele 2060 A Simple Processor Architecture Register 1 Register 2 Register 7 Decoder B Select -*~ Multiplexer ,1 1 Multiplexer [-*-A Select B Bus -- 4 A Bus Destination Select ALU Function Select Shifter Shift Select Output Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design -1 University of' Pittsburgh Tele 2060 ALU Performs.Arithmentic Functions Performs Logic Functions Function is Selected by Control Status Bits o C - Carry o V - Overflow o Z = I If Resultant Contains All Zeros o S - Sign Bit of the Result Decoder Selects Destination for the Resultant Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 2 University of Pittsburgh Tele 2060 ALU Inputs o Operands o Input Carry o Operation Select o Add o Subtract o AND v OR o XOR o Mode (Arithmetic or Logic) Select Outputs o Resultant o Output Carry Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 3 University of Pittsburgh Tele 2060 ALU Function Table Operation Select S2 S1 SO Cin Operation Function 0 0 0 0 F=A Transfer A 0 0 0 1 F=A+1 Increment A 0 0 1 0 F=A+B Add A and B 0 0 1 1 F=A+B+1 Add A and B With Carry 0 1 0 0 F=A+B' Add A and One's Compement of B 0 1 0 1 F=A+B'+1 Subtract B From A 0 1 1 0 F=A-1 Decrement A 0 1 1 1 F=A Transfer A 1 0 0 0 F=AB AND 1 0 1 0 F=A+B OR 1 1 0 0 F=A XOR B Exclusive OR 1 1 1 0 F=A' Complement Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 4 1Iniversity of Pittsburgh Tele 2060 ALU Components " Arithmetic o Parallel Add o One Full Adder per Bit o Selection Logic " Logic o Gates o Multiplexer Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 5 University «f Pittsburgh Tele 2060 Arithmetic-Logic Unit and Processor Design - 6 University of Pittsburgh Tele 2060 Arithmetic-Logic Unit and Processor Design - 7 University of Pittsburgh Tele 2060 Internal Structure of ALU Cn-1 0 Multiplexer Stage So S1 S2 Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 8 University o(' Pittsburgh Tele 2060 Shifter General o Extension of Shift Register Circuit is Possible o This Requires Several Clock Pulses o This is Time Consuming Alternate Approach (Figure 7-18, p. 246 of Mano) o Use Multiplexers o Wire to Cause Shift Effect o Control Determines Nature of Shift o Thus, a Single Clock Cycle is Used Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design - 9 University of Pittsburgh Tele 2060 Control Unit Requirements " MUX A Selector " MUX B Selector " ALU Operation Selector " Shift Selector " Destination Selector Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design -10 University Of Pittsburgh Tele 2060 Control Word " Number and Organization of Bits Required to Control ALU " Bit Requirements o A: A Bus Select (Seven Registers Plus Input) : 3 bits o B: B Bus Select (Seven Registers Plus Input) : 3 bits o D: Destination Select (Seven Registers): 3 bits o F: ALU Control (Four bits) o H: Shift Control (Three bits) o TOTAL =16 bits o Thus, 16 Bits Can Be Used to Perform All Microoperations Martin B.H. Weiss Tele 2060 Control Word Encoding 0 Operation (F) Code Cin = 0 Cin =1 A B D H 0 0 0 F=A F=A+1 Input Input None No Shift 001 F=A+B F=A+B+1 R1 R1 R1 SHL 010 F=A+B' F=A+B'+1 R2 R2 R2 SHR 011 F=A-1 F=A R3 R3 R3 Bus=O 100 F=AB R4 R4 R4 101 F=A+B R5 R5 R5 ROL 110 F=A XOR B R6 R6 R6 ROR 111 F=A' R7 R7 R7 Martin B.H. Weiss Arithmetic-Logic Unit and Processor Design -12 University of Pittsburgh Tele 2060 Microoperations and Microprograms Example Microoperation o RV- R2 - R3 o Symbolically: R2,R3,R1,F=A-B,No Shift o Control Word = 010 0110010101000 = 4CA8 (H) Clearly, Many Microoperations Are Possible Control Memory o Location of Available Microoperations o Width of Control Memory = Control Word Microprograms Can be Written Using a Sequence of Microoperations Martin B.H. Weiss Tele 2060 Addressing Modes Direct o the address is contained in the address field o the size of the memory is limited by the size of the address field Indirect o Content of the Memory Location Contained in the Address Field Points to The Actual Address o Allows for a Larger Memory Because the Address Fields Can Be Larger o Allows for Efficient Address Manipulation Indexed o Content of the Memory Field is Added to the Contents of the Index Register o Allows for Flexible Relative Addressing Martin B.H. Weiss Tele 2060 Control System Design " A Programmer Needs a Logical Structure and Instructions " A Hardware Designer has Microoperations " The Bridge Between These is a Microprogram Martin B.H. Weiss Computer Organization - 10 University of Pittsburgh Tele 2060 Structure of a Microprogrammed Control Unit Control Input Word Next Control Control Control 10. Address Address Memory Data Generator Register (ROM) Register Martin B.H. Weiss Computer Organization - 11 University of Pittsburgh Tele 2060 Example " General o 16 Bits for Processor Control (Bits 1-16; A,B,D,F,H As Before) o One Bit for Address Source Selection (bit 17) o Three Bits For Status Bit Select (Bits 18-20) o Six Bits for the Next Address (Bits 21-26) " 26=64 Microinstructions Are Possible " CAR Can be Loaded or Incremented, Depending on the Condition Martin B.H. Weiss Computer Organization - 12 University of Pittsburgh Tele 2060 Example 1-16 Control ,, Control 17 Mux Address Memory no Register 18-20 External Address I I 1 1 21-26 Incre-I Load ment Input Control * Data Word Multiplexer 01CC'ZZ'SV Processor Unit j' Output Data Martin B.H. Weiss Computer Organization - 13 University of Pittsburgh Tele 2060 A Simple Computer Design Clock CPU Memory E:3~1iE3 Interrupt Read/Write Martin B.H. Weiss Computer Organization -14 University of Pittsburgh Tele 2060 A Simple Computer Design " I/O Interface " 16 Bit Data Bus " 16 Bit Address Bus Martin B.11. Weiss Computer Organization - 15 Universitv of 1'itttihnrgh Tele 2060 CPU Components Input _V Desti- nation Fourteen Registers Decoder (16 Bits) s s ALSU V S Z C (16 Bits) Output Martin B.H. Weiss Computer Organization -16 University of Pittsburgh Tele 2060 CPU Components " ALSU " Registers " Internal Busses " Status Bits Martin B.H. Weiss Computer Organization -17 University of Pittsburgh Tele 2060 ALSU " Two 16 Bit Input Busses " Four Units Multiplexed Together " Each Unit Always Operates on Both Operands " The Operation is Determined by the Selection Lines So and Sl " Operation is Selected by a 4:1 Multiplexer (S2 and S) " 16 Operations are Possible on the Output " Example 0110 => F=A B " Requires a Five Bit Control Word Martin B.H. Weiss Computer Organization -18 Tele 2060 Computer Organization - 19 University of Pittshorgh Tele 2060 Registers Fourteen Total Registers PC Six General Purpose Registers Seven Special Purpose Registers o Index Register o Stack Pointer o Source Register o Destination Register o Temporary Register o Two Constant Registers (Zero and N=16) Martin B.H. Weiss Computer Organization - 20 University of Pittslwrph Tele 2060 Three Internal Busses " One for Each Operand o Attached to One of the Registers via a Multiplexer o One Mux for Each Operand Bus " One For the Result o Destination is One of the Registers o May Also Be External Martin B.H. Weiss Computer Organization - 21 University of Pittslatiroh Tele 2060 Control Word " 17 Bits Long " Five Bits for ALSU (Four Control + Cin) " Four Bits for Mux A " Four Bits for Mux B " Four Bits for Destination Decoder Martin B.H. Weiss Computer Organization - 22 University of Pittsburgh Tele 2060 Computer Organization - 23 University of l'ittsliurgh Tele 2060 CPU Components o Processor Unit o Memory o Control Unit o Buffers/Registers o Busses Busses o External to the Processor o Data Bus (16 bits) u Direction Must be Mediated o Read/Write Line (From/To Memory)) o Address Bus (16 bits) Martin B.11. Weiss Computer Organization - 24 Tele 2060 CPU Buffers and Registers " Data Input Register o Input to IR or Processor o Data from Memory or From the Outside World " Data Output Register - Output to Memory or Oustide World " Address Register - Current Memory Address " Instruction Register - OPcode of the Current Instruction Martin B.H. Weiss Computer Organization - 25 University of Pittsburgh Tele 2060 Control Unit Organization SBR Increment Address MUX CAR Control Memory IR (8-15) ppcode Map Martin B .H. Weiss Computer Organization - 26 ITniversity of Pittsburgh Tele 2060 Control Unit Components o Subroutine Register o OPCode Map o Incrementer o Address Mux o Control Address Register o Control Memory Subroutine Register o Used in Subroutine Call o Stores Return Address Martin B.I-I. Weiss University or Pittsburgh Tele 2060 Control Unit Opcode Map o Maps OPcode Into Control Memory Address o May be a ROM Incrementer - Increments Address Address Mux o Selects Source of Address o Controlled by Control Memory (CS field) Control Address Register - Holds the Memory Address Control Memory - Contains the Microcode Martin B.H. Weiss Computer Organization - 28 University of Pittsburgh Tele 2060 Instruction Types Indirect Bits SI DI Type 0 10 1 o1 'oPCo4e I I SRI I ~st I Register to Register I Type 1 0 1 O ~o4e S Dial): I I e Memory to Register ~ .