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INFORMATION to USERS While the Most Advanced Technology Has INFORMATION TO USERS While the most advanced technology has been used to photograph and reproduce this manuscript, the quality of the reproduction is heavily dependent upon the quality of the material submitted. For example: • Manuscript pages may have indistinct print. In such cases, the best available copy has been filmed. • Manuscripts may not always be complete. In such cases, a note will indicate that it is not possible to obtain missing pages. • Copyrighted material may have been removed from the manuscript. In such cases, a note will indicate the deletion. Oversize materials (e.g., maps, drawings, and charts) are photographed by sectioning the original, beginning at the upper left-hand comer and continuing from left to right in equal sections with small overlaps. Each oversize page is also filmed as one exposure and is available, for an additional charge, as a standard 35mm slide or as a 17”x 23” black and white photographic print. Most photographs reproduce acceptably on positive microfilm or microfiche but lack the clarity on xerographic copies made from the microfilm. For an additional charge, 35mm slides of 6”x 9” black and white photographic prints are available for any photographs or illustrations that cannot be reproduced satisfactorily by xerography. 8703584 Ling, Yong-Long Calvin HIERARCHICAL MULTIPROCESSOR ARCHITECTURE DESIGN IN VLSI FOR REAL-TIME ROBOTIC CONTROL APPLICATIONS The Ohio State University Ph.D. 1986 University Microfilms International300 N. Zeeb Road, Ann Arbor, Ml 48106 PLEASE NOTE: In ?.ll cases this material has been filmed in the best possible way from the available copy. Problems encountered with this document have been identified here with a check mark V . 1. Glossy photographs or pages_____ 2. Colored illustrations, paper or print_______ 3. Photographs with dark background_____ 4. Illustrations are poor copy______ 5. Pages with black marks, not original copy ______ 6. Print shows through as there is text on both sides of page_______ 7. Indistinct, broken or small print on several pages \/ 8. Print exceeds margin requirements______ 9. Tightly bound copy with print lost in spine_______ 10. Computer printout pages with indistinct print_______ 11. Page(s) ____________ lacking when material received, and not available from school or author. 12. Page(s) ____________ seem to be missing in numbering only as text follows. 13. Two pages numbered . Text follows. 14. Curling and wrinkled pages ______ 15. Dissertation contains pages with print at a slant, filmed as received __________ 16. Other____________________________ _________________ ____________________________ University Microfilms International HIERARCHICAL MULTIPROCESSOR ARCHITECTURE DESIGN IN VLSI FOR REAL-TIME ROBOTIC CONTROL APPLICATIONS A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of the Ohio State University by Yong-Long Calvin Ling, B.S.Physics, M.S.E.E. * * * * * The Ohio State University 1986 Dissertation Committee: Approved by: Professor Karl W. Olson Professor David E. Orin Adviser Department of Electrical Professor Steven Bibyk Engineering To my mother 11 ACKNOWLEDGEMENTS I would like to thank my advisor, Professor Karl W. Olson, for his guidance and support throughout my dissertation work. I would also like to thank Professor David E. Orin for his support and many helpful comments. I appreciate Professor Stephen Bibyk for serving on my reading committee. Many thanks to Barbara Elberfeld and Blaine Lilly Jr. for their efforts to edit this dissertation. Kathryn Lilly and Jonathan Chao deserve special thanks for answering so many questions and for their works which made my research work so much easier. I would like to thank my family for their encouragement and support through­ out these years. My wife, who has been so patient and has provided me with constant, loving support, deserves my most special thanks of all. This dissertation research is sponsored by the National Science Foudation. I VITA April 16, 1952 ...... ........................ .........Boru—Taiwan, Republic of China 1974 .........................................................B.S.Physics, Fu-Jen Catholic University, Taiwan, Republic of China 1979 .........................................................M.S.E.E., The Ohio State University, Columbus, Ohio 1979-1984 ................................................Project Engineer, Municipal Electric Company, City of Columbus, Ohio 1984 ....................................................... Graduate Student, Department of Electrical Engineering, The Ohio State University, Columbus, Ohio iv TABLE OF CONTENTS ACKNOWLEDGEMENTS iii V IT A iv L IST O F F IG U R E S ix LIST OF TABLES xvi I. INTRODUCTION 1 1.1 Introduction .......................................................................................... 1 1.2 Organization ....................................................................................... 4 II. SURVEY OF PREVIOUS WORK 7 2.1 Introduction .......................................................................................... 7 2.2 Parallel Algorithms and Parallel Architectures ............................. 9 2.3 VLSI Computer Processor Architecture ....................................... 12 2.4 Multiprocessor Systems for Robotic Applications ....................... 18 2.5 Special Purpose VLSI Processors for Real-time Robotic Control 19 2.6 Summary ............................................................................................. 21 III. LAYERED MULTIPROCESSOR SYSTEM ARCHITECTURE DESIGN FOR REAL-TIME ROBOTIC CONTROL APPLI­ C A T IO N S 22 3.1 Introduction ................................................................................... 22 3.2 Architectural Considerations for Real-Time Robotic Control . 23 3.3 Layered Multiprocessor Architecture for Real-Time Robotic Con­ trol Applications ....................................................................................... 34 3.4 VLSI Implementation - the Robotic Vector Processor (RVP) and Robotic Scalar Processor (RSP) .......................................................... 45 3.5 S u m m a ry ...................................................................................... 46 IV. ARCHITECTURE OF ROBOTIC VECTOR PROCESSOR 48 4.1 Introduction ................................................................................... 48 4.2 RVP Block D ia g ra m ................................................................... 49 4.3 FPP Architectural D e sig n ......................................................... 51 4.4 RVP Instruction S e t ................................................................... 60 4.5 RVP Parallelism ............................................................................... 63 4.6 RVP Control and Data Communications for the Formation of Synchronized SIMD Structures ..............................................................68 4.7 S u m m a ry ...................................................................................... 69 V. ARCHITECTURE OF ROBOTIC SCALAR PROCESSOR 70 5.1 Introduction .................................................. 70 5.2 Common M emory .......................................................................... 71 5.3 Scalar Processor Unit ...................................................................... 74 5.4 Vector S equencer ......................................................................... 86 5.5 RSP-to-RSP Comm unications ................................................... 90 5.6 Parallel Execution of Scalar Computations, Vector Computa­ tions, and Communications 92 5.7 S u m m a ry ...................................................................................... 93 vi VI. THE ROBOTIC VECTOR PROCESSOR DESIGN AND VLSI LAYOUT IN CMOS 97 6.1 Introduction ......................................................................................... 97 6.2 RVP Clocking S ch em e ...................................................................... 97 6.3 RVP C o n tr o l ...................................................................................... 98 6.4 Dual Port Register File ................................................................... 98 6.5 Floating Point A dder ......................................................................... 104 6.6 Floating Point M ultiplier ............................... 114 6.7 Shift and Broadcast N e tw o rk ......................................................... 120 6.8 I/O Channel ......................................................................................... 123 6.9 VLSI Layout, Simulation, Testing of R V P ................................... 123 6.10 S u m m a ry ............................................................................................. 152 VII. PARALLEL IMPLEMENTATION OF THE ROBOTIC CON­ TROL APPLICATIONS 154 7.1 Introduction ......................................................................................... 154 7.2 Basic Floating Point Operations Implemented by R S P ............ 155 7.3 Basic Vector Operations Implemented by RVP ......................... 156 7.4 Implementation of Robotic Control With One RSP and One, Two, and Four RVPs ............................................................................... 160 7.5 Multirate Implementation With Multiple RSPs and RVPs . 196 7.6 S u m m a ry ............................................................................................. 206 VIII. SUMMARY AND CONCLUSIONS 214 8.1 Research Contributions .....................................................................
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