DOCSLIB.ORG

The 32-Bit PA-RISC Run-Time Architecture Document, V. 1.0 for HP

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
The 32-Bit PA-RISC Run-Time Architecture Document, V. 1.0 for HP The 32-bit PA-RISC Run-time Architecture Document HP-UX 11.0 Version 1.0 (c) Copyright 1997 HEWLETT-PACKARD COMPANY. The information contained in this document is subject to change without notice. HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential damages in connection with furnishing, performance, or use of this material. Hewlett-Packard assumes no responsibility for the use or reliability of its software on equipment that is not furnished by Hewlett-Packard. This document contains proprietary information which is protected by copyright. All rights are reserved. No part of this document may be photocopied, reproduced, or translated to another language without the prior written consent of Hewlett-Packard Company. CSO/STG/STD/CLO Hewlett-Packard Company 11000 Wolfe Road Cupertino, California 95014 By The Run-time Architecture Team 32-bit PA-RISC RUN-TIME ARCHITECTURE DOCUMENT 11.0 version 1.0 -1 -2 CHAPTER 1 Introduction 7 1.1 Target Audiences 7 1.2 Overview of the PA-RISC Runtime Architecture Document 8 CHAPTER 2 Common Coding Conventions 9 2.1 Memory Model 9 2.1.1 Text Segment 9 2.1.2 Initialized and Uninitialized Data Segments 9 2.1.3 Shared Memory 10 2.1.4 Subspaces 10 2.2 Register Usage 10 2.2.1 Data Pointer (GR 27) 10 2.2.2 Linkage Table Register (GR 19) 10 2.2.3 Stack Pointer (GR 30) 11 2.2.4 Space Registers 11 2.2.5 User-Readable Control Registers (CR 26 and CR 27) 11 2.2.6 General Registers Summary 12 2.3 External Naming Conventions 12 2.4 Conventions for Accessing Data 13 2.4.1 Static Variables 13 2.4.2 C-Style Common 14 2.4.3 Fortran-Style Common 14 2.4.4 COBOL-Style Common 14 2.4.5 Pascal Outer Block Globals 14 2.4.6 Constants and Literals 14 2.4.7 Automatic Variables 14 2.4.8 Position-Independence 15 2.5 Conventions for Calling Procedures 15 2.5.1 Stack Frame Layout and Marker 15 2.5.2 Stack frame after dynamic memory allocation 19 2.5.3 Parameter Passing and Return Values 21 2.5.4 Type Checking and Floating-Point Parameter Relocation 29 2.5.5 Standard Procedure Calls 32 2.5.6 Indirect Procedure Calls 36 2.5.7 Millicode Procedure Calls 38 2.6 Program Startup 39 CHAPTER 3 Relocatable Object Files 41 3.1 Object File Header 43 3.2 Compilation Unit Records 50 3.3 Space Dictionary 52 3.4 Subspace Dictionary 55 3.5 String Areas 62 3.6 Fixup Requests 62 3.6.1 Fixup Rounding Modes 64 3.6.2 Interpretation of rounding mode and field selector 65 3.6.3 Examples of applying the rounding mode 67 32-bit PA-RISC RUN-TIME ARCHITECTURE DOCUMENT version 1.0 -3 3.6.4 Apply Fixups on instructions 68 3.6.5 List of fixup requests 69 3.6.6 Fixup opcodes, lengths and parameters 75 3.6.7 Parameter Relocation Bits (rbits1, rbits2) 78 3.7 Symbol Table 80 CHAPTER 4 Relocatable Libraries 97 4.1 Archive Header 98 4.2 Library Symbol Table Header Record 100 4.3 Library Symbol Table Format 104 4.3.1 Symbol Directory 104 4.3.2 SOM Directory 113 4.3.3 Free Space List 114 CHAPTER 5 Executable Files 117 5.1 Object File Header 117 5.2 Auxiliary Headers 117 5.2.1 Loader Auxiliary Headers 120 5.2.2 Other Auxiliary Headers 121 5.3 Symbol Table 123 5.4 Stack Unwind Table 124 5.5 Recover Table 124 5.6 Auxiliary Unwind Table 124 CHAPTER 6 HP-UX Specifics 125 6.1 HP-UX Auxiliary Header 125 6.2 Program Startup 127 6.2.1 Sample Assembly Listing of crt0 code 128 6.3 Shared Libraries 141 6.3.1 Shared Library Memory Model 141 6.3.2 Linkage Table 141 6.3.3 The DL Header and Other Tables 143 6.3.4 Version Auxiliary Header 148 6.3.5 Import List 148 6.3.6 Export Table 149 6.3.7 Export Table Extension 152 6.3.8 Shared Library List 153 6.3.9 Module Table 155 6.3.10 Shared Library Unwind Info 156 6.3.11 String Table 158 6.3.12 Dynamic Relocation Records 158 6.3.13 Loading Shared Libraries 161 6.3.14 Intra-library Version Control 163 6.3.15 Library-Level Versioning 164 6.3.16 Import and Export Stubs 167 6.4 System Calls 168 -4 HP Proprietary CHAPTER 7 Symbolic Debug Information 171 7.1 The Debug Information Organization 171 7.2 Compilation Unit Headers 172 7.2.1 Basic typedef and structure definitions 172 7.2.2 XDB Header structure definition: 174 7.3 Name and Type Tables 175 7.3.1 File-class ("File") DNTT Entries 175 7.3.2 Code-class ("Scoping") DNTT Entries 176 7.3.3 Storage-class ("Name") DNTT Entries 183 7.3.4 Type-class ("Type") DNTT Entries 187 7.3.5 General ("overall") DNTT Entry Format 203 7.4 Static Analysis Information 205 7.4.1 XREF Table (XT) Entry Format 205 7.4.2 Static Analysis Support DNTT Entries 207 7.5 Source Line Table 208 7.5.1 SLT Entry Format 208 7.5.2 SLT Types and Data Structure 209 7.6 Value Table (VT) 211 7.7 Ordering of Table Entries 211 7.8 Postprocessing 212 7.9 Debug Format Changes for Debugging of Optimized Code (DOC) 216 7.9.1 Debug Format Changes 216 7.9.2 Object File Format Details 217 7.9.3 Building the Line Tables 218 7.9.4 Debug Format Changes 219 7.9.5 Line Number Table Definition 222 7.9.6 View/modify globals and arguments when safe 224 CHAPTER 8 Stack Unwind Library 227 8.1 Overview 227 8.2 Requirements for Stack Unwinding 228 8.2.1 Unwinding Across an Interrupt Marker 229 8.2.2 Unwinding from Stubs on HP-UX 229 8.2.3 Unwinding from Millicode 229 8.2.4 Instances in Which Unwinding May Fail 230 8.2.5 Callee-Saves Register Spill 230 8.2.6 Sample entry and exit code 230 8.3 Role of Stubs in Unwinding 232 8.3.1 The Stub Unwind Types 233 8.3.2 Unwinding from Parameter Relocation Stub 234 8.4 External Interface 236 8.4.1 The Unwind Descriptor 236 8.4.2 Unwind Utility Routines 240 8.4.3 Initialize a Stack Unwind 247 8.4.4 Unwind Examples: Using U_get_previous_frame 248 8.5 Setjmp and longjmp jmp_buf 256 8.6 Process Context 258 32-bit PA-RISC RUN-TIME ARCHITECTURE DOCUMENT version 1.0 -5 8.6.1 Ada Exception handling 258 8.6.2 C++ Exception handling 273 -6 HP Proprietary CHAPTER 1 Introduction This document describes the runtime architecture for PA-RISC systems running either the HP-UX or the MPE/iX operating system. Other operating systems running on PA-RISC may also use this runtime architecture or a variant of it. The runtime architecture defines all the conventions and formats necessary to compile, link, and execute a program on one of these operating systems. Its purpose is to ensure that object modules produced by many different compilers can be linked together into a single application, and to specify the interfaces between compilers and linker, and between linker and operating system. The runtime architecture applies only to hardware platforms based on PA-RISC Revi- sion 2.0. The runtime architecture does not specify the application programming interface (API), the set of services provided by the operating system to the program. Thus, observing the runtime architecture does not automatically lead to a program that will run on all PA-RISC platforms. It does, however, allow many of the development tools to be shared to a large extent among the various operating systems. When combined with a particular API, this runtime architecture leads to an application binary interface (ABI). In other words, an ABI can be regarded as the composition of an API, a hardware description, and a runtime architecture for that hardware. 1.1 Target Audiences This document is intended for a variety of readers. If you are a systems programmer, you will find information in this document describing the format of an executable object file, the memory model and startup environment 32-bit PA-RISC RUN-TIME ARCHITECTURE DOCUMENT 11.0 version 1.0 1-7 Introduction assumed by a valid program, and the architected interface between a program and the services provided by your operating system. If you develop compilers or other development tools, you will find information in this document about calling conventions and other coding conventions, the object file for- mat, interfaces to the linker, symbolic debug format, and other details important to pro- gram translation. If you are an application programmer, this document can help you learn about the low- level details of how programs execute on PA-RISC. If you need to write assembly code, process object files, examine the stack, or perform dynamic linking, you will find the necessary information in this document. 1.2 Overview of the PA-RISC Runtime Architecture Document Chapter 2 describes the coding conventions used by compilers and by assembly- language programmers. This includes details of the virtual memory model, usage of processor registers, external name conventions, addressing data, procedure calling and parameter passing, and the program startup environment.
Load more

Recommended publications
  • Processor-103
    US005634119A United States Patent 19 11 Patent Number: 5,634,119 Emma et al. 45 Date of Patent: May 27, 1997 54) COMPUTER PROCESSING UNIT 4,691.277 9/1987 Kronstadt et al. ................. 395/421.03 EMPLOYING ASEPARATE MDLLCODE 4,763,245 8/1988 Emma et al. ........................... 395/375 BRANCH HISTORY TABLE 4,901.233 2/1990 Liptay ...... ... 395/375 5,185,869 2/1993 Suzuki ................................... 395/375 75) Inventors: Philip G. Emma, Danbury, Conn.; 5,226,164 7/1993 Nadas et al. ............................ 395/800 Joshua W. Knight, III, Mohegan Lake, Primary Examiner-Kenneth S. Kim N.Y.; Thomas R. Puzak. Ridgefield, Attorney, Agent, or Firm-Jay P. Sbrollini Conn.; James R. Robinson, Essex Junction, Vt.; A. James Wan 57 ABSTRACT Norstrand, Jr., Round Rock, Tex. A computer processing system includes a first memory that 73 Assignee: International Business Machines stores instructions belonging to a first instruction set archi Corporation, Armonk, N.Y. tecture and a second memory that stores instructions belong ing to a second instruction set architecture. An instruction (21) Appl. No.: 369,441 buffer is coupled to the first and second memories, for storing instructions that are executed by a processor unit. 22 Fied: Jan. 6, 1995 The system operates in one of two modes. In a first mode, instructions are fetched from the first memory into the 51 Int, C. m. G06F 9/32 instruction buffer according to data stored in a first branch 52 U.S. Cl. ....................... 395/587; 395/376; 395/586; history table. In the second mode, instructions are fetched 395/595; 395/597 from the second memory into the instruction buffer accord 58 Field of Search ...........................
    [Show full text]
  • The 32-Bit PA-RISC Run- Time Architecture Document
    The 32-bit PA-RISC Run- time Architecture Document HP-UX 10.20 Version 3.0 (c) Copyright 1985-1997 HEWLETT-PACKARD COMPANY. The information contained in this document is subject to change without notice. HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OFMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential damages in connection with furnishing, performance, or use of this material. Hewlett-Packard assumes no responsibility for the use or reliability of its software on equipment that is not furnished by Hewlett-Packard. This document contains proprietary information which is protected by copyright. All rights are reserved. No part of this document may be photocopied, reproduced, or translated to another language without the prior written consent of Hewlett- Packard Company. CSO/STG/STD/CLO Hewlett-Packard Company 11000 Wolfe Road Cupertino, California 95014 By The Run-time Architecture Team CHAPTER 1 Introduction This document describes the runtime architecture for PA-RISC systems running either the HP-UX or the MPE/iX operating system. Other operating systems running on PA-RISC may also use this runtime architecture or a variant of it. The runtime architecture defines all the conventions and formats necessary to compile, link, and execute a program on one of these operating systems. Its purpose is to ensure that object modules produced by many different compilers can be linked together into a single application, and to specify the interfaces between compilers and linker, and between linker and operating system.
    [Show full text]
  • Design of the RISC-V Instruction Set Architecture
    Design of the RISC-V Instruction Set Architecture Andrew Waterman Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2016-1 http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.html January 3, 2016 Copyright © 2016, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California, Berkeley Committee in charge: Professor David Patterson, Chair Professor Krste Asanovi´c Associate Professor Per-Olof Persson Spring 2016 Design of the RISC-V Instruction Set Architecture Copyright 2016 by Andrew Shell Waterman 1 Abstract Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman Doctor of Philosophy in Computer Science University of California, Berkeley Professor David Patterson, Chair The hardware-software interface, embodied in the instruction set architecture (ISA), is arguably the most important interface in a computer system. Yet, in contrast to nearly all other interfaces in a modern computer system, all commercially popular ISAs are proprietary.
    [Show full text]
  • A Lisp Oriented Architecture by John W.F
    A Lisp Oriented Architecture by John W.F. McClain Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degrees of Master of Science in Electrical Engineering and Computer Science and Bachelor of Science in Electrical Engineering at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY September 1994 © John W.F. McClain, 1994 The author hereby grants to MIT permission to reproduce and to distribute copies of this thesis document in whole or in part. Signature of Author ...... ;......................... .............. Department of Electrical Engineering and Computer Science August 5th, 1994 Certified by....... ......... ... ...... Th nas F. Knight Jr. Principal Research Scientist 1,,IA £ . Thesis Supervisor Accepted by ....................... 3Frederic R. Morgenthaler Chairman, Depattee, on Graduate Students J 'FROM e ;; "N MfLIT oARIES ..- A Lisp Oriented Architecture by John W.F. McClain Submitted to the Department of Electrical Engineering and Computer Science on August 5th, 1994, in partial fulfillment of the requirements for the degrees of Master of Science in Electrical Engineering and Computer Science and Bachelor of Science in Electrical Engineering Abstract In this thesis I describe LOOP, a new architecture for the efficient execution of pro- grams written in Lisp like languages. LOOP allows Lisp programs to run at high speed without sacrificing safety or ease of programming. LOOP is a 64 bit, long in- struction word architecture with support for generic arithmetic, 64 bit tagged IEEE floats, low cost fine grained read and write barriers, and fast traps. I make estimates for how much these Lisp specific features cost and how much they may speed up the execution of programs written in Lisp.
    [Show full text]
  • Brief History of Microprogramming
    Microprogramming History -- Mark Smotherman A Brief History of Microprogramming Mark Smotherman Last updated: October 2012 Summary: Microprogramming is a technique to implement the control logic necessary to execute instructions within a processor. It relies on fetching low-level microinstructions from a control store and deriving the appropriate control signals as well as microprogram sequencing information from each microinstruction. Definitions and Example Although loose usage has sometimes equated the term "microprogramming" with the idea of "programming a microcomputer", this is not the standard definition. Rather, microprogramming is a systematic technique for implementing the control logic of a computer's central processing unit. It is a form of stored-program logic that substitutes for hardwired control circuitry. The central processing unit in a computer system is composed of a data path and a control unit. The data path includes registers, function units such as shifters and ALUs (arithmetic and logic units), internal processor busses and paths, and interface units for main memory and I/O busses. The control unit governs the series of steps taken by the data path during the execution of a user- visible instruction, or macroinstruction (e.g., load, add, store). Each action of the datapath is called a register transfer and involves the transfer of information within the data path, possibly including the transformation of data, address, or instruction bits by the function units. A register transfer is accomplished by gating out (sending) register contents onto internal processor busses, selecting the operation of ALUs, shifters, etc., through which that information might pass, and gating in (receiving) new values for one or more registers.
    [Show full text]
  • POWER4 System Microarchitecture
    by J. M. Tendler J. S. Dodson POWER4 J. S. Fields, Jr. H. Le system B. Sinharoy microarchitecture The IBM POWER4 is a new microprocessor commonplace. The RS64 and its follow-on organized in a system structure that includes microprocessors, the RS64-II [6], RS64-III [7], and RS64- new technology to form systems. The name IV [8], were optimized for commercial applications. The POWER4 as used in this context refers not RS64 initially appeared in systems operating at 125 MHz. only to a chip, but also to the structure used Most recently, the RS64-IV has been shipping in systems to interconnect chips to form systems. operating at up to 750 MHz. The POWER3 and its follow- In this paper we describe the processor on, the POWER3-II [9], were optimized for technical microarchitecture as well as the interconnection applications. Initially introduced at 200 MHz, most recent architecture employed to form systems up to systems using the POWER3-II have been operating at a 32-way symmetric multiprocessor. 450 MHz. The RS64 microprocessor and its follow-ons were also used in AS/400* systems (the predecessor Introduction to today’s eServer iSeries*). IBM announced the RISC System/6000* (RS/6000*, the POWER4 was designed to address both commercial and predecessor of today’s IBM eServer pSeries*) family of technical requirements. It implements and extends in a processors in 1990. The initial models ranged in frequency compatible manner the 64-bit PowerPC Architecture [10]. from 20 MHz to 30 MHz [1] and achieved performance First used in pSeries systems, it will be staged into the levels exceeding those of many of their contemporaries iSeries at a later date.
    [Show full text]
  • The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2
    The RISC-V Instruction Set Manual Volume I: User-Level ISA Document Version 2.2 Editors: Andrew Waterman1, Krste Asanovi´c1;2 1SiFive Inc., 2CS Division, EECS Department, University of California, Berkeley [email protected], [email protected] May 7, 2017 Contributors to all versions of the spec in alphabetical order (please contact editors to suggest corrections): Krste Asanovi´c,Rimas Aviˇzienis,Jacob Bachmeyer, Christopher F. Batten, Allen J. Baum, Alex Bradbury, Scott Beamer, Preston Briggs, Christopher Celio, David Chisnall, Paul Clayton, Palmer Dabbelt, Stefan Freudenberger, Jan Gray, Michael Hamburg, John Hauser, David Horner, Olof Johansson, Ben Keller, Yunsup Lee, Joseph Myers, Rishiyur Nikhil, Stefan O'Rear, Albert Ou, John Ousterhout, David Patterson, Colin Schmidt, Michael Taylor, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray VanDeWalker, Megan Wachs, Andrew Waterman, Robert Wat- son, and Reinoud Zandijk. This document is released under a Creative Commons Attribution 4.0 International License. This document is a derivative of \The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.1" released under the following license: c 2010{2017 Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovi´c. Creative Commons Attribution 4.0 International License. Please cite as: \The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2", Editors Andrew Waterman and Krste Asanovi´c,RISC-V Foundation, May 2017. Preface This is version 2.2 of the document describing the RISC-V user-level architecture. The document contains the following versions of the RISC-V ISA modules: Base Version Frozen? RV32I 2.0 Y RV32E 1.9 N RV64I 2.0 Y RV128I 1.7 N Extension Version Frozen? M 2.0 Y A 2.0 Y F 2.0 Y D 2.0 Y Q 2.0 Y L 0.0 N C 2.0 Y B 0.0 N J 0.0 N T 0.0 N P 0.1 N V 0.2 N N 1.1 N To date, no parts of the standard have been officially ratified by the RISC-V Foundation, but the components labeled \frozen" above are not expected to change during the ratification process beyond resolving ambiguities and holes in the specification.
    [Show full text]
  • Enhancing the RISC-V Instruction Set Architecture
    Enhancing the RISC-V Instruction Set Architecture Plamen Petrov MInf Project (Part 1) Report Master of Informatics School of Informatics University of Edinburgh 2019 3 Abstract Since its emergence, RISC-V has offered a license-free alternative to proprietary in- struction sets designed by ARM and Intel by providing a stable base to researchers and small companies. This makes it possible for small companies and researchers to design new cores without incurring exorbitant costs. In our two-part project we explore RISC- V’s performance compared to the commercial ARM and X86 architectures. Most of the first part focuses on static code size, where we find that RISC-V performs very rea- sonably, but is behind Thumb2. For this reason, we propose improvements to RISC-V which constitute of new prologue and epilogue instructions that almost fully bridge this gap. We give ideas for other possible enhancements and plan to extend the project to cover dynamic measures in the second part. Overall, we conclude that RISC-V per- forms very well given the resources invested in it and open instruction sets, in general, deserve to be developed further for the better of the computer architecture field as a whole. 4 Acknowledgements I would like to express my gratitude to my supervisor Professor Nigel Topham for supporting me with the project throughout the year. Table of Contents 1 Introduction 7 1.1 Overview . 7 1.2 Aims . 9 1.3 Contributions . 10 1.4 Outline . 10 2 Background 11 2.1 Abbreviations . 11 2.2 Binary File . 11 2.3 SPEC2006 .
    [Show full text]
  • Data and Control Dependence Handling
    18-447 Computer Architecture Lecture 8: Pipelining II: Data and Control Dependence Handling Prof. Onur Mutlu Carnegie Mellon University Spring 2015, 2/2/2015 Agenda for Today & Next Few Lectures Single-cycle Microarchitectures Multi-cycle and Microprogrammed Microarchitectures Pipelining Issues in Pipelining: Control & Data Dependence Handling, State Maintenance and Recovery, … Out-of-Order Execution Issues in OoO Execution: Load-Store Handling, … 2 Readings for Next Few Lectures (I) P&H Chapter 4.9-4.11 Smith and Sohi, “The Microarchitecture of Superscalar Processors,” Proceedings of the IEEE, 1995 More advanced pipelining Interrupt and exception handling Out-of-order and superscalar execution concepts McFarling, “Combining Branch Predictors,” DEC WRL Technical Report, 1993. Kessler, “The Alpha 21264 Microprocessor,” IEEE Micro 1999. 3 Readings for Next Few Lectures (II) Smith and Plezskun, “Implementing Precise Interrupts in Pipelined Processors,” IEEE Trans on Computers 1988 (earlier version in ISCA 1985). 4 Recap of Last Lecture Wrap Up Microprogramming Horizontal vs. Vertical Microcode Nanocode vs. Millicode Pipelining Basic Idea and Characteristics of An Ideal Pipeline Pipelined Datapath and Control Issues in Pipeline Design Resource Contention Dependences and Their Types Control vs. data (flow, anti, output) Five Fundamental Ways of Handling Data Dependences Dependence Detection Interlocking Scoreboarding vs. Combinational 5 Review: Issues in Pipeline Design Balancing work in pipeline stages How many
    [Show full text]
  • Overview Programming Model Cache and Bus Interface Unit Operation
    Overview 1 Programming Model 2 Cache and Bus Interface Unit Operation 3 Exceptions 4 Memory Management 5 Instruction Timing 6 Signal Descriptions 7 System Interface Operation 8 Performance Monitor 9 PowerPC Instruction Set Listings A Invalid Instruction Forms B PowerPC 604 Processor System Design C and Programming Considerations Glossary GLO Index IND 1 Overview 2 Programming Model 3 Cache and Bus Interface Unit Operation 4 Exceptions 5 Memory Management 6 Instruction Timing 7 Signal Descriptions 8 System Interface Operation 9 Performance Monitor A PowerPC Instruction Set Listings B Invalid Instruction Forms C PowerPC 604 Processor System Design and Programming Considerations GLO Glossary IND Index G522-0330-00 MPC604EUM/AD 3/98 PowerPC™ 604e RISC Microprocessor User's Manual with Supplement for PowerPC 604™ Microprocessor . This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document. The PowerPC 604e microprocessor embodies the intellectual property of IBM and of Motorola. However, neither party assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party. Neither party is to be considered an agent or representative of the other party, and neither has granted any right or authority to the other to assume or create any express or implied obligations on its behalf.
    [Show full text]
  • Coding Assembler for Performance
    Slide 1 Coding Assembler for Performance SHARE 107 Baltimore, MD Session 8192 August 2006 David Bond Tachyon Software LLC [email protected] Slide 2 © Tachyon Software LLC, 2006 Permission is granted to SHARE Incorporated to publish this material for SHARE activities and for others to copy, reproduce, or republish this material in a manor consistent with SHARE's By-laws and Canons of Conduct. Tachyon Software retains the right to publish this material elsewhere. Tachyon Software is a registered trademark and Tachyon z/Assembler is a trademark of Tachyon Software LLC. IBM, HLASM, z/OS, z/VM, z/Architecture, and System z are trademarks or registered trademarks of the International Business Machines Corporation. Other trademarks belong to their respective owners. Slide 3 Why code in assembler? ● High performance ● Access to OS services ● Your boss said so ● Job security In this session, we will look at coding techniques that can improve performance, or at least not sabotage performance on modern processors. If you have been coding assembler for a long time, you may not realize how much the rules have changed. Slide 4 Not your parent's mainframe Many people still think of mainframes as they were in the 1960's: ● Some or all instructions were microcoded ● Memory access speed was constant ● Instruction timings were published ● Instruction speed was independent of adjacent instructions On modern System z machines: ● Simple instructions are in hardware ● Complex instructions are millicoded ● Multiple processors and LPARs ● Processors are piplined and superscalar ● Each processor has a 2-level memory cache ● Instructions and data are cached separately Slide 5 Processor and Memory Organization Processors are wired together into MultiChip Modules.
    [Show full text]
  • Design of the RISC-V Instruction Set Architecture by Andrew Shell
    Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California, Berkeley Committee in charge: Professor David Patterson, Chair Professor Krste Asanovi´c Associate Professor Per-Olof Persson Spring 2016 Design of the RISC-V Instruction Set Architecture Copyright 2016 by Andrew Shell Waterman 1 Abstract Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman Doctor of Philosophy in Computer Science University of California, Berkeley Professor David Patterson, Chair The hardware-software interface, embodied in the instruction set architecture (ISA), is arguably the most important interface in a computer system. Yet, in contrast to nearly all other interfaces in a modern computer system, all commercially popular ISAs are proprietary. A free and open ISA standard has the potential to increase innovation in microprocessor design, reduce computer system cost, and, as Moore's law wanes, ease the transition to more specialized computational devices. In this dissertation, I present the RISC-V instruction set architecture. RISC-V is a free and open ISA that, with three decades of hindsight, builds and improves upon the original Reduced Instruction Set Computer (RISC) architectures. It is structured as a small base ISA with a variety of optional extensions. The base ISA is very simple, making RISC-V suitable for research and education, but complete enough to be a suitable ISA for inexpensive, low- power embedded devices. The optional extensions form a more powerful ISA for general- purpose and high-performance computing.
    [Show full text]