COMPUTER SCIENCE COMPUTER SCIENCE SEDGEWICK/WAYNE SEDGEWICK/WAYNE

Computer Science 21. CPU

•Overview Computer 21. Central Processing Unit •Bits, registers, and memory Science •Program counter An Interdisciplinary Approach •Components and connections

R O B E R T S E D G E W I C K KEVIN WAYNE Sections 6.2-3 http://introcs.cs.princeton.edu

CS.21.A.CPU.Overview

Let's build a computer! A smaller computing machine: TinyTOY

TOY instruction-set architecture. CPU = Central Processing Unit Type 1 instruction • 256 16-bit words of memory. opcode Rd Rs Rt Computer • 16 16-bit registers. 4 bits to specify Display • 1 8-bit program counter. one of 16 registers Type 2 instruction Touchpad • 2 instruction types opcode Rd addr Battery • 16 instructions. Keyboard 8 bits to specify one ... of 256 memory words CPU (difference between a TV set and a computer) TinyTOY instruction-set architecture. • 32 8-bit words of memory. Previous lecture • 1 8-bit register. Combinational circuits • 1 5-bit program counter. ALU (calculator) 1 instruction type TinyTOY instruction • opcode addr This lecture • 8 instructions. Sequential circuits with memory CPU 5 bits to specify one of 32 memory words CPU (computer) Purpose of TinyTOY. Illustrate CPU circuit design for a "typical" computer.

3 4 TinyTOY instruction set architecture Review: the state of the machine

TinyTOY instructions. Contents of memory, registers, and PC at a particular time • Halt • Provide a record of what a program has done. • Add • Completely determines what the machine will do. ALU and IR hold • AND intermediate states of computation • XOR • LOAD ADDRESS Memory Registers ALU • LOAD TinyTOY instruction opcode addr • STORE IR • BRANCH NEGATIVE 5 bits to specify one of 32 memory words

4 bits and 16 words in prototype machine PC TinyTOY instruction-set architecture.

• 16 8-bit words of memory (expandable to 32). • 1 8-bit register (R0). • 1 4-bit program counter (expandable to 5). • 8 instructions (only one type).

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CPU circuit components for TinyTOY Perspective

TinyTOY CPU Q. Why TinyTOY?

• ALU (adder, AND, XOR) ALU MAIN MEMORY A. TOY circuit width would be about 5 times TinyTOY circuit width. • Memory CONTROL 16 8-bit words (expandable to 32) • Register (R0) • PC (with incrementer) • IR • MUXes (switch circuits)

• Control PC R0 MUX 4 bits • Clock stay tuned 3-way TOY (this lecture)

R0 8 bits TinyTOY IR Address MUX 8 bits 2-way

Sobering fact. The circuit for your computer is hundreds to thousands of times wider.

Goal. Complete CPU circuit for TinyTOY (same design extends to TOY and to your computer). Reassuring fact. Design of all three is based on the same fundamental ideas. 7 8 COMPUTER SCIENCE Sequential circuits SEDGEWICK/WAYNE

Q. What is a sequential circuit?

A. A digital circuit (all signals are 0 or 1) with feedback (loops).

Q. Why sequential circuits? 21. CPU A. Memory (difference between a DFA and a Turing machine).

•Overview •Bits, registers, and memory Basic abstractions • On and off. •Program counter • Wire: Propagates an on/off value. •Connections • Switch: Controls propagation of on/off values through wires. • Flip-flop: Remembers a value.

CS.21.B.CPU.Memory 10

Simple circuits with feedback A new ingredient: Circuits with memory

component level classic notation

Loops in circuits lead to time-varying behavior An SR flip-flop controls feedback. R S R S

R

NOR • Sequence of switch operation matters. • Add control lines to switches Q • Need tight control (see next slide). in simple feedback loop. S • R (reset) sets state to 0. NOR • S (set) sets state to 1. "cross-coupled NOR gates" Example 1. Two switches, each blocked by the other. • Q (state) is always available. Q Q output • State determined by whichever switches first. value • Stable (once set, state never changes). (state) • Basic building block for memory circuits. examples R: set to 0 stays 0 S: set to 1 stays 1 unused

gratuitous addition: looks Example 2. Three switches, blocked in a cycle. looks like "0" like "1" • State determined by whichever switches first. a "buzzer" • Not stable (cycles through states).

Caveat. Timing of switch vs. propagation delay.

11 12 under the cover circuit (gate)

One bit in a register Registers input bus Add logic to an SR flip-flop for more precise control Register input • Provide data value on an input wire instead of using S and R controls. • Holds W bits. bus

• Use enable write signal to control timing of write. • Input and output on W-wire busses. enable • Flip-flop value is always available. • Register contents always available on output bus. write Enable write puts W input bits into register. output • bus 1 write input input (ignored if enable write enable off ignored not write enable) examples write set to 1 S component not enabled level stays "1"

1 1 0 0 = 12 0 write 0 1 enable write enable off 0 value (set to input TinyTOY registers 1 write if write enable) set to 0 enabled R • PC holds 4-bit address. • IR holds 8-bit instruction. looks like "0" stays "0" • R0 holds 8-bit data value. 0 1 0 1 = 5 13 14

One bit in main memory Main memory: interface

interface Add a selection mechanism Main memory. (four 6-bit words) • Flip-flop value is not always available. • N words; each stores W bits. • Use select for read signal to make it available. • Read and write data to one of N words. • "1-hot" OR to collect the one bit value that is selected. • Address inputs select one word. • Addressed word always on output bus. input • When write enabled, W input bits are copied into addressed word. write enable collect in (set to 1 if read select) number of bits per address words word bits value (set to input if write enable) this slide 4 6 2 read select tinyTOY 16 or 32 8 4 or 5

TOY 256 16 8

your computer 1 billion 64 32 collect out

15 16 Main memory bank: component level Main memory bank: switch level

switch-level implementation Main memory. Main memory. component-level implementation (four six-bit words) (four 6-bit words) • N words; each stores W bits. • N words; each stores W bits. • Read and write data to one of N words. • Read and write data to one of N words. • Address inputs select one word. • Address inputs select one word. • Addressed word always on output bus. • Addressed word always on output bus. • When write enabled, W input bits are • When write enabled, W input bits are copied into addressed word. copied into addressed word.

Basic mechanisms • A decoder uses address to switch on one line (through the addressed word) • "1-hot" OR gates at each bit position take word contents to the output bus.

1 Example: Read word 2 (10) 0

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TinyTOY main memory bank COMPUTER SCIENCE SEDGEWICK/WAYNE interface switch level Interface input bus • Input bus for "store" • Output bus for "load" • Address bits to select a word MEMORY • Enable write control signal 16 8-bit words (expandable to 32) 21. CPU

Connections •Overview • Input bus from registers •Bits, registers, and memory

• Output bus to IR and R0 address bits •Program counter • Address bits from PC, IR, R0 •Components and connections • Enable write from "control"

enable write output bus

19 CS.21.C.CPU.PC Designing a digital circuit: overview Another useful combinational circuit: Multiplexer

Steps to design a digital (sequential) circuit Bus multiplexer (MUX). • Design interface: input busses, output busses, control signals. • Combinational circuit to select among input buses. • Determine components. • Exactly one select line i is activated. • Puts bit values from input bus i onto output bus. • Determine datapath requirements: "flow" of bits. • Establish control sequence. Note: MUX in text takes binary select specification

example 0 1 3 4-bit input busses 2 0 select 0 is hot selection lines 1

2 Warmup. Design TinyTOY program counter (PC). Three components and three control signals

output is value of selected input ( bus 0)

Typical use. Connect a component in different ways at different times.

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Counter interface Counter layout and implementation

switch level implementation A Counter holds a value and supports 3 control signals: Layout and connections establish • Increment. Add 1 to value. • data paths (busses) = • Load. Set value from input bus. • control signals • Enable write. Make value available on output bus.

component simplified adder level with y = 0001

INCREMENTER Components inside COUNTER • Register. increment input bus • Incrementer (add 1). load increment • 2-way MUX. increment 2-WAY load load BUS MUX

enable enable enable write write write REGISTER TinyTOY PC: 4-bit counter output bus 23 24 Counter operation Summary of TinyTOY PC (counter) circuit

The PC is three components and supports three control signals: load (from IR) increment • Load, then enable write. Set value from input bus (example: branch instruction). • Increment, then enable write. Add one to value. Value is written to the PC and available on output bus in both cases. INCREMENTER INCREMENTER

interface component circuit level INCREMENTER increment increment 2-WAY 2-WAY load BUS MUX load BUS MUX

increment increment 2-WAY load BUS MUX load enable enable write REGISTER write REGISTER enable enable write write REGISTER

Important note: Enable write is a pulse, to avoid feedback (stay tuned) Next. CPU circuit (10 components, 20+ control signals). 25 26

COMPUTER SCIENCE TinyTOY: Interface SEDGEWICK/WAYNE

CPU is a circuit inside the machine

21. CPU Interface to outside world •Overview • Switches and lights • ON/OFF •Bits, registers, and memory • RUN •Program counter Connections to outside (omitted) •Components and connections • ADDR to PC TinyTOY • DATA to memory bank input bus A computing machine • Buttons to control lines that activate memory load/store

CS.21.D.CPU.Components 28 Review: CPU circuit components for TinyTOY Review: Program counter and instruction register

TinyTOY CPU TOY operates by executing a sequence of instructions.

• ALU (adder, AND, XOR) ALU MAIN MEMORY • Memory CONTROL 16 8-bit words (expandable to 32) • Register (R0) Critical abstractions in making this happen • PC (with incrementer) Program Counter (PC). Memory address of next instruction. • IR • • MUXes (switch circuits) • Instruction Register (IR). Instruction being executed.

• Control PC R0 MUX 4 bits • Clock 3-way FETCH Fetch-increment-execute cycle R0 8 bits • Fetch: Get instruction from memory into IR. • Increment: Update PC to point to next instruction. IR Address MUX EXECUTE 8 bits 2-way • Execute: Move data to or from memory, change PC, or perform calculations, as specified by IR. INCREMENT

29 30

TinyToy data paths and control lines Fetch (every instruction)

ALU MAIN MEMORY CONTROL control 16 8-bit words (expandable to 32) MAIN MEMORY Data paths 16 8-bit words • PC to Address MUX • Address MUX to memory

INCREMENTER • Memory to IR

Control signals R0 MUX 3-way PC MUX • Address MUX select 1 2-way PC 4 bits • IR Write Enable

PC IR Address MUX 2-way R0 4 bits 8 bits 8 bits

IR Address MUX 8 bits 2-way

31 32 Increment (review) Add instruction

Data paths ALU MAIN MEMORY Data paths 16 8-bit words • PC to Incrementer • IR to Address MUX • Incrementer to PC MUX • Address MUX to memory

INCREMENTER • PC MUX to PC • Memory to ALU • R0 to ALU R0 MUX PC MUX 3-way • ALU to R0 MUX 2-way Control signals • PC MUX select 0 • R0 MUX to R0 PC 4 bits R0 • PC write enable 8 bits Control signals Address MUX IR 2-way 8 bits • ALU Select ADD • Address MUX select 0 • R0 MUX Select 0 • R0 Write Enable Note: Occurs during execution of every instruction (except branch). 33 34

Clock TinyTOY clock

A CLOCK provides a regular ON-OFF pulse. Two-cycle design. Each control signal is in one of four epochs.

3 2 1 0

Requirement. Clock cycle longer than max switching time. epoch name example

0 fetch set MA from PC Q. How to implement a clock?

1 fetch/write load IR from memory A. Use an external device.

2 execute set ALU inputs A. Use a buzzer circuit. 3 2 1 0 3 execute/write load R0 from ALU

0 1 2 3

Key feature. A sequence of signals. 35 36 One final combinational circuit: Control Tick-Tock

Control. Circuit that determines control line sequencing. CPU is a circuit, driven by a clock.

RUN example: ADD instruction during epoch 3 Initalize via console switches. Press RUN: clock starts ticking • PC to mem addr MUX • IR enable write FETCH Control line sequencing • PC increment • PC enable write • Clock cycles through four epochs, EXECUTE . INCREMENT raising one line at a time . • Determines sequence of at most 4 sets . [details of instruction execution differ] of control lines for each instruction TinyTOY . A computing machine . .

Faster clock? Faster computer!

Key feature. A simple combinatorial circuit. And THAT . . . is how your computer works! 37 38

TOY "Classic", back-of-envelope design (circa 2005) TinyTOY CPU

ALU Memory

control

PC increment

R0 mux (3-way) PC bus mux (2-way)

PC

R0

MA bus mux (2-way) IR

39 40 A real microprocessor (MIPS R10000) COMPUTER SCIENCE SEDGEWICK/WAYNE

Computer Science

Computer 21. Central Processing Unit Science An Interdisciplinary Approach

R O B E R T S E D G E W I C K KEVIN WAYNE Sections 6.2-3 http://introcs.cs.princeton.edu

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