Self-Cascode Composite Transistor?

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Analog and Mixed-Signal Center (AMSC) ELEN 607 (ESS) Texas A&M University 1 What is a Self-Cascode Composite Transistor?

D D

M2 m W/L G G X W/L M1 S S (a) Self-Cascode Composite NMOS Transistor (b) Equivalent Simple Transistor

In practical cases, for optimal operation the W/L ratio of M2 should be larger than that of M1, i.e. m>1. The 2-transistor structure can be treated as a composite transistor, which has a much larger effective channel length (thus lower output conductance). 2 Working Conditions [5]

For the composite transistor to function properly, both M2 and M1 should conduct, thus, the following conditions should be satisfied:

VG VX VT  0 (1)

VG VS VT  0 (2)

We can rewrite (1) as:

VX VS VG VS VT VDSAT (3)

From (3) we know that transistor M1 must be in linear region. Depending on the drain voltage, transistor M2 can work in saturation region or linear region.

3 Equivalent Transistor Parameter (I)

For the composite transistor work in saturation region, we know M2 should in saturation and M1 is in linear region. Thus, we can write equations for these two transistors as:  1  2 2 i  V V V  i1  1VGS VT  VX VX 1 2 GS X T  2 

Solving i 1 we can obtain: 1 21 2 i2  VGS VT  2 2  1

21 From (3), we have eq  2  1 m 1 If 2  m 1 eq  1  2 m 1 m 1    eq m 1

4 Comments on VDSAT

Because transistor M1 always operates in linear region while the top transistor operates in saturation or linear region. Voltage between the source and drain terminal of M1 is so small that there is no discernable VDSAT difference in both the composite and simple transistors. Thus,self-cascode structure can be used in low voltage applications.

VDSATeq VDSATM 2 VDS M1 VDSATM 2  ID2RM1 1 R  where M1 W C V V  OX GS T L The operating voltage of a regular cascode circuit is much higher than that of a single transistor. This characteristic makes regular cascode circuit not suitable for low voltage applications.

5 DC Simulation Results (I)

m=50

m=8 m=4

m=2

VDS

Effect of “m” on the output characteristics 6 DC Simulation Results (II)

From simulations (TMSC 0.35um process), we observe that: m W/L Equivalent W/L 2 1.5/0.6 1.7/0.9 4 1.5/0.6 2.5/1.5 6 1.5/0.6 3.0/2.1 8 1.5/0.6 3.3/2.4 10 1.5/0.6 3.8/3.0 20 1.5/0.6 20/24

When m is larger, the effective length L is also larger

7 Equivalent (W/L)Transistor Parameter

Because  is proportional to W/L, we can have the equivalent W/L derived from previous results:

W  W      W   L   L     2 1  L  W  W  eq       L 2  L 1

If lengths of M2 and M1 are equal, and M2 is m times wider than M1, the equivalent W/L ratio is:

W  m W  1 W           L eq m 1 L 1 m 1 L 2

8 Equivalent Output Impedance (Low frequency small signal)

iO VO iO VO

VG VG

r2 rO-eff VX gm2 VG VX VT  gmeff VG VT  r1

The equivalent output impedance of the composite transistor is: ro  gm2r2r1  r2  r1  (gm2r1 1)r2  (m gm1r1 1)r2  (m1)r2 m 1 9 Effective Transconductance

M2 m W/L G X W/L RM1=1/gm1 M1

The lower transistor M1 is equivalent to a resistor But this resistor is input dependent.. The effective transconductance of the composite transistor is approximately equal to the transconctance of M1:

gm-eff=gm2/m=gm1

10 Small-Signal Equivalent Circuit (Single Transistor)

Cgd RS VG VO VS L Cgs R gm2VG gO Cds 2 A2s  A1s  A0 AV (s)  2 B2s  B1s  B0 VG VS Equations: VG  sCgs  VG VO  sCgd  0 RS VO VO  gO VO  sCds  gm2 VG  VO VG  sCgd  0 RL Solve this equation set we can obtain the voltage gain as a function of the frequency: A  C C C C C C  R 2 gs gd gs ds ds gd L B2  gm1RLRS  RL  RS CgsCds CgsCgd CdsCgd 

A1  gm1Cgd  g0Cgd  g0Cgs  gm2Cgd  RL B1  Cgs  Cds  Cgd  Cds  gm1RL  Cgs  Cgd gm1RS  g0RL gm1RS  g0RS  g0RL   C g R  R  g R R  A0  gm1gm2  RL gd m2 L S m1 L S B0  gm2  g0  gm1  gm1RL g0 This function has 2 poles and 2 zeros, but it is too complex! 11 Small-Signal Equivalent Circuit (Composite Transistor) Cgd RS VG VO VS gs C gO Cds RL gm2(VG-VX) VX

gm1 2 A2s  A1s  A0 AV (s)  2 Circuit Equations B2s  B1s  B0

VG VS  RS VG sCgs  VG VO sCgd  0

VO  VO VX gO  sCds  gm2 VG VX  VO VG  sCgd  0 RL

VX  gm1  gm2 VG VX  VX VO gO  sCds   0 Solving this equation set we can obtain the voltage gain as a function of the frequency:

A2  CgsCgd CgsCds CdsCgd  RL B2  gm1RLRS  RL  RS CgsCds CgsCgd CdsCgd  A1  gm1Cgd  g0Cgd  g0Cgs  gm2Cgd  RL B0  gm2  g0  gm1  gm1RL g0 A0  gm1gm2  RL B1  Cgs  Cds  Cgd  Cds  gm1RL  Cgs  Cgd gm1RS  g0RL gm1RS  g0RS  g0RL 

 Cgd gm2 RL  RS  gm1RL RS  12 Effect of the Capacitor C gd (Simple)

Let’s assume Cgs  0 Cds  0 RL g0 1, thus

B2  0 A1  Cgd RL B1  CgdRL RS g0  Cgd  RL  gm2 RL 1RS Cgd A0  g m2 RL  CgdRS gm2 RL A2  0 B0  RL g0 1  1 The simplified transfer function is:

A1s  A0 AV (s)  B1s  B0

This means that if we consider the effect of only , the function is simplified to one pole and one zero One zero: One pole: gm2 1 Z    C P gd gm2RL RSCgd

13 Effect of the Capacitor C gd (Composite)

Let’s assume Cgs  0 Cds  0 RL g0 1, thus

A2  0

A1  gm1Cgd  g0Cgd  gm2Cgd  RL  g m1  g m2 Cgd RL

A0  g m1g m2  RL

B2  0

B1  Cgd gm1RL  gm1RS  g0 RL gm1RS  g0 RS  g0 RL  gm2 RL  gm2 RS  gm1gm2 RL RS 

 Cgd gm2 RL 1 gm1RS 

B0  g m2  g 0  g m1  g m1RL g0  g m2 The simplified transfer function is:

A1s  A0 AV (s)  B1s  B0 One zero: One pole: g g g 1 1   m1 m2  m1    Z P 1 g R R C g R R C gm1  gm2 Cgd Cgd  m1 S  L gd m1 S L gd

14 Comments on the Poles and Zeros

Consider the effect of C gd only, we can get the following conclusion:

The pole of the simple transistor is higher than that of the composite transistor.  g 1 Z Composite  m1  Z Simple gm2 m

The same conclusion can be applied to zeros:

 g 1 PComposite  m1  PSimple gm2 m

15 Frequency Parameters

The transition time  increases as the value of m. According to reference[1], The relationship is:

  u 1 1 m

Where  u is the transition time of an unit transistor used in the self-cascode structure. For the saturated MOS transistor in strong inversion parameters  T (Cutoff frequency) and  are related by:

T  2

16 Advantage of the Self-Cascode Structure

The main advantage of this structure is smaller transistor area. The sum of areas of MD and MS is smaller than the area of the equivalent simple transistor. The table below shows the simulation results with MOSIS TSMC 0.35u CMOS process: MS W/L m MD W/L Equivalent FET W/L Area Ratio* Gain (RL=inf.) 3.0/0.6u 3 9.0u/0.6u 5.6u/1.2u 7.2/6.72 42dB 3.0u/0.6u 8 24.0u/0.6u 38.5u/12.0u 16.2/462.0 47dB 1.5u/0.6u 11 16.5u/0.6u 9.9u/12.0u 10.8/118.8 44dB

* COMPOSITE/SINGLE For equal chip area:

AV CASCODE  AV SELFCASCODE  AV SIMPLETRANSISTOR To achieve the same voltage gain:

AREACASCODE  AREASELFCASCODE  AREASIMPLETRANSISTOR 17 Applications (I)--Current Mirror

Iin Iout

Iin Iout M3 M4

M1 M2 M1 M2

Simple transistors can be substituted with self-cascode structure to achieve better performance. (i.e. higher output impedance)

18 Schematic of the Circuit for Simulation

Simple

Composite

Model: TMSC 0.35um CMOS Process

19 Current Mirror Simulation Results (DC)

20-Iout

Simple(1): 15u/6.6u Simple(2): 3.0u/1.2u Composite: 15u/0.6u +1.5u/0.6u m=10

Current Gain Error @15uA: Simple(1): 1.3% Simple(2): 2.7% Composite: 1.7%

Iin Simple(1): 3.5e-3 g0/gm: Simple(2): 7.3e-3 (smaller = better) Composite: 4.2e-3 20 Current Mirror Simulation Results (AC)

Bias Current=15uA

Bandwidth: BWsimple(1)

10% Iout Error Point (MHz): Simple(1): 14.1 Composite: 28.1 Simple(2): 164

Simple(1): 15u/6.6u Simple(2): 3.0u/1.2u Composite: 15u/0.6u +1.5u/0.6u m=10

21 Application (I) – Current Mirrors

Traditional Current Mirror Huge Area (901T)

Iin 1:M Iout R Q Series-Parallel M  Current Mirror S  P

Ex. R = 30, S = 1 R ... P . . .

rows . . . rows Q = 30, P = 1 . . . Ratio: 1:900 Area: 60T S Q columns columns Traditional vs. Series-Parallel

Current Mirror I/O Characteristic AMI 0.6um Process For each transistor, W/L=1.5/0.6um Series-Parallel Current Mirror

AMI 0.6um Process For each transistor, W/L=1.5/0.6um

Good current matching range

Size ↑, Accuracy ↑ Compare Current Mirrors

Series-Parallel current mirror improves the output impedance

Input Output R S P Q M Area Imp. Imp.

Trad. 1 1 1 900 900 901T 71.5K 4.0K 30 1 1 30 900 60T 356.8K 12.4K

Series- 60 2 2 60 900 240T 357.3K 20.7K Parallel 90 3 3 90 900 540T 357.5K 28.8K 120 4 4 120 900 960T 357.6K 36.8K Output Impedance Comparison Input Current = 1uA, Ratio = 1:900 Compare Current Mirrors

Input Output R S P Q M Area Imp. Imp.

Trad. 1 1 1 900 900 901T 19.1K 800 30 1 1 30 900 60T 155.4K 4.3K

Series- 60 2 2 60 900 240T 154.4K 4.8K Parallel 90 3 3 90 900 540T 154.1K 5.5K 120 4 4 120 900 960T 154.1K 6.2K Output Impedance Comparison Input Current = 10uA, Ratio = 1:900 Voltage Swing

Stacked transistors limit the output swing of S-P current mirror Output Output R S P Q Vdsat Vdsat (Iin=1uA) (Iin=10uA) Trad. 1 1 1 900 89mV 245mV 30 1 1 30 441mV 1.4V

Series- 60 2 2 60 303mV 1.0V Parallel 90 3 3 90 244mV 830mV 120 4 4 120 210mV 720mV Vdsat (equivalent) of the output transistor reveals the max swing of the output voltage Applications (II)--Differential Pair AVDD AVDD RL RL RL RL VOUTM VOUTP

VOUTM VOUTP M3 M4 M1 M2 VINP VINM M1 M2 VINP VINM

ITAIL ITAIL

Composite transistors can replace single transistors in a differential pair. Through self-cascode structure, higher voltage gain can be achieved.

28 Differential Pair Simulation Results (DC)

m=10 ITAIL=20uA

29 Differential Pair Simulation Results (AC)

Transistor Size: Simple: 15u/6.6u Composite: 15u/0.6u +1.5u/0.6u m=10

DC Gain: Simple: 49.34dB Composite: 48.95dB 3dB Bandwidth: simple: 5.9MHz Composite: 4.9MHz

30 References

1. C. Galup-Montoro, etc., “Series-Parallel Association of FET’s for High Gain and High Frequency Applications”, IEEE JSSC, Sept. 1994

2. D. Ceuster, etc., “Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors”, Electronics Letters, Feb. 1996

3. P. Furth, H. Om’mani, “A 500-nW Floating-Gate Amplifier with Programmable Gain”, IEEE 1999

4. I. Fujimori, T. Sugimoto, “A 1.5V, 4.1mW Dual-Channel Audio Delta-Sigma D/A Converter”, IEEE JSSC, Dec. 1998

5. Personal note from Dr. Ugur Cilingiroglu

6. Yunchu Li, examples and SPICE tables

31 LOW VOLTAGE CURRENT-MIRRORS

V Iin cnt Vout

Vin Iout Additional Circuitry

Vo M1 M2

General scheme for high-performance current mirror structure.

32 Iout V Vout out I  Arc M4 in M4

  Vin Vo M1 M2

(a) (b) Iout

Vref I + M4 in - V M3 C V V out o - + Vout Vo

M2 Ib

High-performance current mirrors: 33 Conventional active-input current mirror

V V  dd DSAT1 T V Vi min  max VClamp,VDSAT1  Iref  A  Iout + V0min  VDSAT 2 + Vclamp 1 Rin  A gm1 A Vo Vi 1 M1 M2 R  out g - o2 - Vss Advantage: • Lower input impedance Disadvantage: • To achieve stability, gm1 can not be arbitrarily small. Thus, can not work over a wide current range. • Compensation of the amplifier depends on the value of Iref.

34 Improved active input current mirrors (I)

Advantage: Vdd This current mirror can operate over a very wide Iref Iout range of currents: from values equal to junction + leakage currents up to the maximum current the + Vclamp n1 OTA might be able to sink. Disadvantage: Vi Vo • Additional compensation capacitor between n1 M2 and n2 may required to achieve stability M1 VG • The OTA must be able to sink twice the maximum - - expected value for Iref, which imposes an important n2 design constraint for the OTA.

V V V V  AV   T DSAT G DSAT clamp  V V Vimin  max Vclamp,  0min DSAT 2  A A1  1 1 1 R   R  in A g  (1 A) g A g out m1 o1 m1 go2 35 Improved active input current mirrors (II)

Vdd Advantage: Iref • This current mirror can operate over a very Iout wide range of currents: from values equal to + + Vclamp junction leakage currents up to the maximum current the OTA might be able to sink. • If the differential voltage amplifier is already Vi Vo compensated for unity gain feedback, the circuit M2 M1 is always stable. - Disadvantage: - • Higher power supply may be required for amplifier • More chip area and power consumption V V  AV 1 1 DSAT1 T clamp Rin   Vimin  (1 A)(g  g ) (1 A) g A1 m1 o1 m1 1 Rout  go2 36 Improved active input current mirrors (III)

Iout Vout V M3 c Q MAX Iin V  2V  V M4 OUT DSAT oV Vin Ada + I MIN Q MAX Vo V  V  3V  V CNOUT tp DSAT oV C M1 c M2 Ib (a)

Vcntout

Ibias 3

Ibias 1 3 Ada M5 M6 2 + I M7 1 2 Ibias / 2

(b) (a) Proposed low-voltage high-performance current mirror. 37 (b) Implementation of the differential amplifier Ada.

Ib V a o M3

Cc Cb M1 I C b a + - Vi (a)

Iou

ee t Vout Ibias

Ce M4

f v M5 M6 de V o + i M7 C - M2 C f

I / 2 bias (b)

Open-loop response analysis: (a) input side and (b) output side. 38 Active regulated cascode current mirror

Vdd V V  ref T DSAT I Vi min  max VD ,VDSAT  Iout  A1  VD + Vomin  2VDSAT M3 1 A2 R  Vo in + A1 A1 gm1 M2 Vi gm3 1 A2 M1 - Rout  - Vss go3go2

Advantages: Disadvantages: • High output impedance • Poles and zeros may cause unstability • Low input impedance • more power and area

39 Techniques for Wideband Amplifiers ELEN 607 (ESS)

Wideband Alternative Conventional R Frequency Dependent CM Current Mirror (FDCM)

CF >> Cgs

CF 0.1K < R < 1K

Ib CF

Low Frequency Behavior High Frequency Behavior

T. Itakura and T. Iida, “A Feedforward Technique with Frequency-Dependent Current Mirrors for a Low-Voltage Wideband Amplifier,” IEEE J. Solid-State Circuits, Vol. 31, No.6, pp. 847-849, June 1996. 40 An example of its use: ELEN 607 (ESS)

VDD R M 3 I P3 b M P4 M P  1  v M vin v in P2 C o F1 CL C F2 M M n1 n4 R1 M R2 n2 VSS

Wideband Amplifier with Feedforward Technique

• CF1 by passes two current mirrors. • CF2 is fed forward to the input of another FDCM and signal is amplified.

41 ELEN 607 (ESS)

Next, we discuss different families of wideband reported in the literature.

RL M   M n3 vo vo n4 • An alternative is to

connect CF instead to nodes B to nodes A  M  v M n n2 vin in A 1 B

RSS CF

F. Centurelli et al, “A Bootstrap Technique for Wideband Amplifiers,” IEEE Trans. on Circuits And Systesm – I, Vol. 49, No. 10, pp. 1474-1480, October 2002 42 FOLDED-CASCODE WIDEBAND AMPLIFIER

V b4 V M M b4 P4 P3 R F1 M Vb M P2 1 P1   vin Vout   vin vin v in C V F1 C b2 CLVOUT F2 Itail M n5 Vb2

M M M n M n3 n4 3 n4

Conventional Folded-Cascode (FC) FC with Capacitive Feedforward V DD

R F2 Vb 1   I Vo Vin bias   Vo Vo CL C F2 Vb2 Vb2

VSS Differential Wideband Amplifier 43 F. Opt Eynde, W. Sansen, “A CMOS Wideband Amplifier with 800MHz Bandwidth,” IEEE Custom Integrated Circuits Conf., pp. 9.1.1-9.1.4, 1991 References

[1] E. Sánchez-Sinencio and A. Andreou, Editors, “ Low Power/Low Voltage Integrated Circuits and Systems, Piscataway, IEEE Press, 1999. [2] K. Laker, W. Sansen, “Design of Analog Integrated Circuits and Systems”, McGraw-Hill, New York, 1994 [3] Edgar Sánchez-Sinencio, ELEN626 Notes, 1998 [4] Teresa Serrano-Gotarredona, etc., “Very wide range tunable CMOS/Bipolar Current Mirrors with Voltage Clamped Input”, IEEE Trans. On Circuits and Systems, Oct. 1998. [5] D.A. Johns and K. Martin, “Analog Integrated Circuit Design”, New York, John Wiley 1997 [6] R. Jacob Baker, H. Li, etc., “CMOS Circuit Design, Layout, and Simulation”, IEEE Press, 1997.

44 Different OTAs MB VDD MB Vb MB V o Vo

Vin,cm  R VIN V Rs s IN M1 Rs I RSS SS Rss/2 -VSS

Source Degenerated OTA-1 Common-Mode Equivalent Circuit

gm,n rds,p ||gm,n  gmb,n rds,n Rs  2Rss  rds,n  Rs  2Rss  (1) Acm  1 gm,n  gmb,n Rs 2Rss 

Vs (2) 1 gm,n rds,p ||gm,n  gmb,n rds,nRs  rds,n  Rs  V A  o df 2 1 g  g R vin m,n mb,n s

Differential-Mode Equivalent Circuit. 45 Where A CMMR  df Acm

Assume

gm,n  gmb,n rds,n Rs  2Rss   Rs , Rss , rds,n , rds,p

 gm,n  gmb,n rds,nRs  Rs , rds,n , rds,p 1  Rs , Rs  Rss gm,n  gmb,n

rds,p 1 rds,p Rss Acm  , Adf  ,CMRR  2Rss 2 2Rs Rs

46 MB MB Vb

Vo -  MD MD VIN VIN 2Rs

Iss 2R 2Rss ss 2

Source Degenerated OTA-2 CM Equivalent Circuit

V DD g  r || g  g r 2R  r  2R V m,n  ds,p  m,n mb,n ds,n ss ds,n ss  (3) b Acm  1 gm,n  gmb,n 2Rss Vout

Vin 2Rss||Rs g  r || g  g r R || 2R  r  R || 2R 1 m,n  ds,p  m,n mb,n  ds,n s ss ds,n ss ss  (4) Virtual Ground Adf  2 1 gm,n  gmb,n Rs || Rss  Differential-Mode Equivalent Circuit

47 Where

Adf rds,p rds,p CMRR  , Acm  , Adf  Acm 2Rss 2Rs

Then

R CMRR  ss Rs

48 ML ML

Vo -  MD MD VIN VIN I R ss ss 2

 1   g  || r || g  g r 2R  r  2R  m,n  ds,p   m,n mb,n  ds,n ss ds,n ss  (5)  gm,p   Acm  1 gm,n  gmb,n 2Rss

(6) Adf  gm,n rds,p || rds,n 

49 Where

A 1 CMRR  df , A  , A  g r || r  cm g  2R df m,n ds,p ds,n Acm m,p ss

Then

CMRR  gm,n rds,p || rds,n gm,p  2Rss

50 R IBP N Rn/2

MDP MDP Vin - V  o VIN VIN

MDN MDN Rn/2

RN CM Equivalent Circuit

Complementary OTA

gm,p  gmb,p rds,p 2RN  rds,p  2RN ||gm,n  gmb,n rds,n 2RN  rds,n  2RN  Acm  1 g  g 2R  1 g  g 2R   m,n mb,n N   m,p mb,p N  Virtual Ground  ||   gm,n   gm,p 

V vin out 1 A  g  g r || r  df 2 m,n m,p ds,p ds,n Virtual Ground

DM Equivalent Circuit 51 Where

Adf CMRR  , Acm  2gm.p  gmb,p rds,p ||gm,n  gmb,n rds,n  , A cm 1 A  g g r || r  df 2 m,n m,p ds,p ds,n

Then

g  g r || r  CMRR  m,n m,p ds,p ds,n 4gm,p  gmb,p rds,p ||gm,n  gmb,n rds,n 

52 V MB DD V MB V  V  bias1 o o  T1   0 v v 0 Vo vcmc i i   M1 M2 Vo Vin

Vcmc MS

VSS Simple Differential OTA   Vo Vo gm,MS T2   rds,MB ||gm,M1  gmb,M1 rds,M12rds,MS  rds,M1  2rds,MS  v v 0 2vcmc i i 2

V  V  A  T  o o  g r || r  dm 3 v  v m,M1,2 ds,MB ds,M1 i i vcmc Vbias

  r || 2g  g r r  r  2r Vo Vo ds,MB  m,M1 mb,M1 ds,M1 ds,MS ds,M1 ds,MS  rds,MB Acm  T4      v  v 1 2gm,M1  gmb,M1 rds,MS 2r i i vcmc Vbias ds,MS g m,M1 53 Folding Cascode Amplifier Architecture

54 55 56 Cascode with positive feedback and bulk-driven input stage

57 58 1V CDB Folded Cascode OTA

59 References

S Mallya, and JH Nevin Design procedures for a fully differential folded-cascode CMOS operational amplifier –IEEE J. of Solid-State Circuits , vol. 24, No. 6, pp, 1737-1740, December 1989 -

• Folded cascode amplifier with rail-to-rail common-mode range - all 2 versions » WC Hsu, WR Krenik, JR Hellums - US Patent 4,797,631, 1989 - Google Patents Page 1. [54] FOLDED CASCODE AMPLIFIER WITH RAIL-TO-RAIL COMMON-MODE RANGE [75] Inventors: Wei-ChanHsu,Piano;WilliamR. Krenik, Dallas; James R. Heliums, ...

• R. Assaad and J. Silva-Martinez, "Enhancing General Performance of the Folded-Cascode Amplifier by Recycling Current", IEEE Electronics Letters. Vol. 43, Issue 23, November 2007.

T. Lehmann, M. Cassia, 1-V power supply CMOS cascode amplifier IEEE J. of Solid-State Circuits, vol 36, pp. 1082-1086, July