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Cascode Summary • Cascaded Amplifier Design • Amplifier Biasing • Other Amplifier Configurations • Digital Circuit Design

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Cascode Summary • Cascaded Amplifier Design • Amplifier Biasing • Other Amplifier Configurations • Digital Circuit Design EE 330 Lecture 36 • Cascode Summary • Cascaded Amplifier Design • Amplifier Biasing • Other Amplifier Configurations • Digital Circuit Design Review from Last Lecture The Cascode Amplifier (consider npn BJT version) VCC IB VOUT Q2 VXX Q1 VIN VSS • Actually a cascade of a CE stage followed by a CB stage but usually viewed as a “single-stage” structure • Cascode structure is widely used Review from Last Lecture Cascode current sources IX IX Q2 M2 VXX VXX IX VYY VYY M1 Q1 VSS VSS VSS g0CC VCC VCC VDD Q1 VYY IX M1 VYY VXX Q2 M2 VXX All have the same small-signal model I IX X g02 g 01 +gπ2 g=0CC g01 +g 02 +gπ2 +g m2 Current Source Summary (BJT) Basic Cascode IX IX VCC VCC V YY Q1 Q1 Q2 VYY Q1 VYY VXX VSS I X VYY VXX Q2 Q1 VSS IX g01 g01/b g01 gg0 01 g 0CC β Current Source Summary (MOS) Basic Cascode IX VDD IX M2 V VXX V DD YY VYY M1 M1 V YY M 1 V VYY M1 ZZ VSS M2 IX VSS IX g0 g0 gg 0 01 g02 gg0 01 gm2 High Gain Amplifier Comparisons ( n-ch MOS) VCC VDD VCC IB VDD VOUT IB VDD VZZ VOUT M2 V M4 M1 YY VZZ VIN M3 VOUT M2 VXX VZZ M VSS 1 M3 VIN VOUT V M1 SS M2 VOUT gm1 VIN A-V VXX g 01 M2 VXX 1 gm1 VSS A- M1 V V 2g01 IN M1 VIN ggm1 m2 VSS A-VCC gg01 02 VSS gm1 A-VCC g01 1 ggm1 m2 A-VCC 2 g01 g 02 High Gain Amplifier Comparisons (BJT) VDD VCC VCC IB V IB OUT VYY VOUT VIN Q1 VOUT V Q1 IN VCC V EE Q2 Q V VXX VYY 3 CC V -g EE VOUT Q m VZZ 3 AV g Q2 0 VXX 1 g VYY Q4 m1 Q1 A VOUT V V 2gIN Q1 01 gm1 VIN Q2 AV β VXX g 01 VSS VSS Q1 g VIN A m1 V V g01 SS gm1 β A=V g201 The Cascode Amplifier • Operational amplifiers often built with basic cascode configuration • Usually configured as a differential structure when building op amps • Have high output impedance (but can be bufferred) • Terms “telescopic cascode”, “folded-cascode”, and “regulated cascode” often refer to op amps based upon the cascode configuration VDD VB1 M5 M6 VB2 M7 M8 VOUT VB3 M3 M4 VIN VIN M1 M2 IT V B5 M 11 V SS Telescopic Cascode Op Amp (CMFB feedback biasing not shown) Cascade Configurations VDD VDD IB1 IB2 IB1 IB2 VOUT VOUT M1 Q1 Q2 VIN VIN M2 VSS Two-stage Cascade VSS A?VCB A?VCM Cascade Configurations VDD VDD IB1 IB2 IB1 IB2 VOUT VOUT M1 Q1 Q2 VIN VIN M2 VSS Two-stage Cascade VSS -gm1 -g m2 g m1 g m2 g m1 AVCB β g01 +g 2 g 02 g 2 g 02 g 02 -gm1 -g m2 g m1 g m2 AVCM g01 g 02 g01 g 02 • Significant increase in gain • Gain is noninverting • Comparable to that obtained with the cascode Cascade Configurations VDD VDD VYY VXX VYY VXX M4 Q3 Q4 M3 VOUT VOUT M1 Q1 Q2 VIN VIN M2 VSS Two-stage Cascade VSS -gm1 -g m2 g m1 g m2 g m1 AVCB β g01 +g 03 +g 2 g 02 +g 04 2g 2 g 02 2g 02 -gm1 -g m2 g m1 g m2 AVCM g01 g 03 g 02 g 04 4g01 g 02 Note factor or 2 and 4 reduction in gain due to actual current source bias Cascade Configurations V VDD DD I I I IB1 IB2 B1 B2 B3 VOUT VOUT VIN Q1 Q2 Q3 VIN Q1 Q2 VSS VEE Two-stage Cascade Three-stage Cascade • Large gains can be obtained by cascading • Gains are multiplicative (when loading is included) • Large gains used to build “Op Amps” and feedback used to control gain value • Some attention is needed for biasing but it is manageable • Minor variant of the two-stage cascade often used to built Op Amps • Compensation of two-stage cascade needed if feedback is applied to maintain stability • Three or more stages are seldom cascaded because no really good way to compensate to maintain stability Differential Amplifiers VDD R1 R2 VOUT1 VOUT2 V1 Q1 Q2 V2 ITAIL VSS Basic operational amplifier circuit Amplifier Biasing Amplifier biasing is that part of the design of a circuit that establishes the desired operating point (or Q-point) Goal is to invariably minimize the impact the biasing circuit has on the small-signal performance of a circuit Usually at most 2 dc power supplies are available and these are often fixed in value by system requirements – this restriction is cost driven Discrete amplifiers invariable involve adding biasing resistors and use capacitor coupling and bypassing Integrated amplifiers often use current sources which can be used in very large numbers and are very inexpensive Amplifier Biasing Example: Vout RL Vin VDD R RB1 C1 C2 AV =-g m R L Vout C1 C Desired small-signal circuit B E RL Common Emitter Amplifier Vin RB2 RE1 C Vout 3 RL//RC1 Biased circuit Vin RB1//RB2 Actual small-signal circuit AV =-g m R L //R C1 Amplifier Biasing Example: Vout RL Vin Desired small-signal circuit Common Emitter Amplifier VDD R RB1 C1 C2 Vout C1 C B E RL Vin RB2 RE1 C3 Biased small-signal circuit Amplifier Biasing Example: Vout Vin RL Desired small-signal circuit V Common Collector Amplifier DD Vout Vin IB RL VSS Biased circuit Amplifier Biasing Example: R2 R1 Vin Vout Desired small-signal circuit Inverting Feedback Amplifier R2 R1 VDD Vin Vout VSS Biased circuit Other Basic Configurations C B Q1 Q2 E Darlington Configuration • Current gain is approximately β2 • Two diode drop between Beff and Eeff Other Basic Configurations C B Q1 Q2 E Sziklai Pair • Same basic structure ad Darlington Pair • Current gain is approximately βn βp • Current gain will not be as large when βp< βn • Only one diode drop between Beff and Eeff Other Basic Configurations Low offset buffers VDD VCC IB2 IB2 VOUT M1 VOUT VIN M2 VIN Q1 Q2 ZL ZL IB1 IB1 VSS VEE • Actually a CC-CC or a CD-CD cascade • Significant drop in offset between input and output • Biasing with DC current sources Other Basic Configurations Voltage Attenuator VDD VDD VDD M2 VOUT VIN VOUT VOUT VIN VIN M1 • Attenuation factor is quite accurate (Determined by geometry) • Infinite input impedance • M1 in triode, M2 in saturation • Actually can be a channel-tapped structure Amplifier Wrap-Up We will now draw closure to the focus on amplifiers in this course (high-frequency performance will be considered later if time permits) with a brief review: • Amplifier Design Strategies • MOS-Bipolar mappings • Large and Small Signal Models • Basic Amplifier Configurations Amplifier Design Strategies • Draw on Past Experience • Often leads to Circuit or Architecture that can be modified or extended • Remember unique characteristics observed for circuit structures for future use even if not relevant in an existing deisgn • Identify the degrees of freedom in the design and the number of constraints and then systematically explore the design space • Simulation-guided computer simulation is not an effective way of exploring a multi-variable design space ! MOS Amplifiers (summary) • 1-1 mapping between almost all bipolar amplifiers and MOS amplifiers • Simply replace BJT with MOS devices and redo the biasing • Small-signal gains for MOS circuits in terms of small-signal model parameters identical if set gπ = 0 for BJT circuits MOS-Bipolar Amplifier Mapping V VOUT OUT VIN VIN Common Emitter Common Source VIN VIN VOUT VOUT Common Collector Common Drain VOUT VOUT VIN VIN Common Base Common Gate Can use these equations only when small signal circuit is EXACTLY like that shown !! MOS-Bipolar Amplifier Mapping Example: Common Emitter – Common Source Circuits VDD G VOUT VOUT gm AV VIN G gGo VIN 1 RIN g VSS g 0 VCC G VOUT VOUT gm G AV VIN gG VIN o RIN VEE Digital Circuit Design Most of the remainder of the course will be devoted to digital circuit design 3.5V C M6 B M5 A M4 F F C M3 B M2 Verilog A M1 VHDL module gates (input logic [3:0] a,b, library IEEE; use IEEE.STD_LOGIC_1164.all; output logic [3:0] y1,y2,y3,y4,y5); entity gates is assign y1 = a&b; //AND port(a,b: in STD_LOGIC_VECTOR(3 dowto 0); assign y2 = a | b; //OR y1,y2,y3,y4,y5:out STD_LOGIC_VECTOR(3 downto 0)); assign y3 = a ^ b; //XOR end; assign y4 = ~(a & b); //NAND architecture synth of gates is assign y5 = ~( a | b); //NOR begin endmodule y1 <= a and b; y2 <= a or b; y3 <= a xor b; A rendering of a small standard y4 <= a nand b; cell with three metal layers y5 <= a nor b; (dielectric has been removed). end; The sand-colored structures are metal interconnect, with the vertical pillars being contacts, typically plugs of tungsten. The reddish structures are polysilicon gates, and the solid at the bottom Standard Cell Library is the crystalline silicon bulk Digital Circuit Design • Hierarchical Design • Propagation Delay with • Basic Logic Gates Multiple Levels of Logic • Properties of Logic Families • Optimal driving of Large • Characterization of CMOS Capacitive Loads Inverter • Power Dissipation in Logic • Static CMOS Logic Gates Circuits – Ratio Logic • Other Logic Styles • Propagation Delay • Array Logic – Simple analytical models • Ring Oscillators – Elmore Delay • Sizing of Gates Hierarchical Digital Design Domains: Top Behavioral: Structural: Physical Bottom Multiple Levels of Abstraction Hierarchical Digital Design Domains: Top Behavioral: Design Down Top Structural: Physical Design Bottom Up Bottom Hierarchical Digital Design Domains: Top Top Down Design Down Top Behavioral: Structural: Bottom Up Design Bottom Up Physical Bottom Multiple Sublevels in Each Major Level All Design Steps may not Fit Naturally in this Description Hierarchical Analog Design Domains: Top Behavioral: Design Down Top Structural: Physical Design Bottom Up Bottom Hierarchical Digital Design Domains: Behavioral : Describes what a system does or what it should do Structural : Identifies constituent blocks and describes how these blocks are interconnected and how they interact Physical : Describes the constituent blocks to both the transistor and polygon level and their physical placement and interconnection Multiple representations often exist at any level or sublevel End of Lecture 36 .
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