A 56–161 Ghz Common-Emitter Amplifier with 16.5 Db Gain Based

Article A 56–161 GHz Common-Emitter Ampliﬁer with 16.5 dB Gain Based on InP DHBT Process

Yanfei Hou 1 , Weihua Yu 1,2,*, Qin Yu 1, Bowu Wang 1, Yan Sun 3, Wei Cheng 3 and Ming Zhou 4

1 Beijing Key Laboratory of Millimeter Wave and Terahertz Technology, Beijing Institute of Technology, Beijing 100081, China; [email protected] (Y.H.); [email protected] (Q.Y.); [email protected] (B.W.) 2 Chongqing Microelectronics Center, Chongqing 401332, China 3 Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016, China; [email protected] (Y.S.); [email protected] (W.C.) 4 Department of Microwave Module Circuit, Nanjing Electronic Devices Institute, Nanjing 210016, China; [email protected] * Correspondence: [email protected]

Abstract: This paper presents a broadband amplifier MMIC based on 0.5 µm InP double-heterojunction bipolar transistor (DHBT) technology. The proposed common-emitter amplifier contains five stages, and bias circuits are used in the matching network to obtain stable high gain in a broadband range. The measurement results demonstrate a peak gain of 19.5 dB at 146 GHz and a 3 dB bandwidth of 56–161 GHz (relative bandwidth of 96.8%). The saturation output power achieves 5.9 and 6.5 dBm at 94 and 140 GHz, respectively. The 1 dB compression output power is −4.7 dBm with an input power of −23 dBm at 94 GHz. The proposed amplifier has a compact chip size of 1.2 × 0.7 mm2, including DC and RF pads.

Citation: Hou, Y.; Yu, W.; Yu, Q.; Keywords: broadband amplifiers; double-heterojunction bipolar transistor (DHBT); indium phos- Wang, B.; Sun, Y.; Cheng, W.; Zhou, phide (InP) M. A 56–161 GHz Common-Emitter Amplifier with 16.5 dB Gain Based on InP DHBT Process. Electronics 2021, 10, 1654. https://doi.org/ 1. Introduction 10.3390/electronics10141654 Broadband amplifiers play an important role in high-resolution radar systems, high- data-rate communication systems, and measuring instruments. With the advancement Academic Editor: Anna B. Piotrowska of technology, the requirements for system performance and frequency are increasing in number, and the demand for broadband amplifiers is also increasing. Received: 18 June 2021 The traveling wave amplifier is common in broadband amplifier design, and is also Accepted: 9 July 2021 Published: 11 July 2021 known as a distributed amplifier (DA) [1–6]. The bandwidth, flatness, and output power of DAs are outstanding among broadband amplifiers. The main limitation of DAs is that their maximum gain does not exceed the transistor, which limits their high-frequency applica- Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in tions because the transistor gain is inversely proportional to the operating frequency. The published maps and institutional affil- cascode structure is another commonly used topology for designing broadband amplifiers, iations. and it is often used as a basic unit to form a DA to increase its gain [3]. Because of the narrow-band characteristics of the matching network, the common-emitter (CE) structure is considered unsuitable for broadband amplifier design [7–9]. This paper presents a five-stage wideband common-emitter amplifier that incorporates the bias circuit into the matching network and finally obtains a maximum gain of 19.5 dB Copyright: © 2021 by the authors. at 146 GHz with a 3 dB bandwidth of 56–161 GHz. To the best of the authors’ knowledge, Licensee MDPI, Basel, Switzerland. This article is an open access article the proposed common-emitter amplifier has the highest relative bandwidth (RB) in this distributed under the terms and frequency band based on the 0.5 µm InP DHBT process. conditions of the Creative Commons 2. InP DHBT Technology Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ The amplifier was fabricated using a 0.5 µm InP DHBT process. The emitter contact is 4.0/). 500 nm wide and 5 µm long, and the base contacts are 300 nm wide at both sides of the

Electronics 2021, 10, 1654. https://doi.org/10.3390/electronics10141654 https://www.mdpi.com/journal/electronics Electronics 2021, 10, x FOR PEER REVIEW 2 of 10

The amplifier was fabricated using a 0.5 µm InP DHBT process. The emitter contact is 500 nm wide and 5 µm long, and the base contacts are 300 nm wide at both sides of the emitter. An InGaAsP composite collector was used to eliminate the current blocking effect caused by the B-C heterojunction conduction band spike [10]. The composite collector area consists of an InGaAs setback layer, a step-graded InGaAsP layer, and a δ-doping layer; all of the layer structures are listed in [11,12]. The ft/fmax values of the transistor are 350 and 535 GHz, respectively, as shown in Figure 1. Current gain (H21), maximum available power gain (MAG), and maximum stable power gain (MSG) can be obtained by Formulas (1)–(5), where k is the stability factor. The process provides three wiring metal layers and compact interconnect vias between them. Metal-Insulator-Metal (MIM) capacitors with 0.26 fF/µm2 capacitance density and 25 Ω/square TaN TFR are also available [13,14]. YS−2 H ==21 21 21 ()()−++ (1) YSSSS1111 11 22 12 21 S MAG=−−>21 ( k k2 11) k Electronics 2021, 10, 1654 2 of 12 (2) S12

emitter. An InGaAsP composite collector was used to eliminate the current blocking effect caused by the B-C heterojunction conduction band spike [10]. The composite collectorS21 area consists of an InGaAs setback layer, a step-graded InGaAsP layer,MSG and a δ =-doping k < 1 layer; all of the layer structures are listed in [11,12]. The ft/fmax values of the transistor (3) are 350 and 535 GHz, respectively, as shown in Figure1. Current gain ( H21), maximumS12 available power gain (MAG), and maximum stable power gain (MSG) can be obtained by Formulas (1)–(5), where k is the stability factor. The process provides three wiring metal layers and compact interconnect vias between them. Metal-Insulator-Metal22 (MIM) 2 µ 2 −−+ − capacitors with 0.26 fF/ m capacitance density and 251Ω/squareSSSSSS11 TaN TFR are 22 also 11 22 12 21 available [13,14]. = Y −k2S (4) H = 21 = 21 (1) 21 Y (1 − S )(1 + S ) + S S 11 11 22 12 21 2 SS12 21 |S | p MAG = 21 k − k2 − 1 k > 1 (2) |S12| |S | 2 MSG = 21 k < 1 (3) | | zz− S12= 12 21 1 − |S |2 − |SU|2 + |S S − S S |2 (5) k = 11 22 11 22 12 21 (4) |S S | ()()⋅−⋅ () () () 2 12 21 4Rezz11 Re 22 Re zz 12 Re 21 |z − z |2 U = 12 21 (5) 4(Re(z11) · Re(z22) − Re(z12) · Re(z21))

2 Figure 1. The extracted ft/fmax of the 0.5 × 5 µm device. Figure 1. The extracted ft/fmax of the 0.5 × 5 µm2 device. Figure2 shows a cross-section of the back end of the 0.5 µm InP DHBT MMIC process used in this paper. This process includes thin-ﬁlm resistors (TFR), MIM capacitors, and three layers of interconnected metal (M1-M3). A benzocyclobutene (BCB) spin-on dielectric is used asFigure the interlayer 2 shows dielectric (ILD) a cross-section with 2 µm (M1-M2) and of 3 µthem (M2-M3) back ILD end of the 0.5 µm InP DHBT MMIC process used in this paper. This process includes thin-film resistors (TFR), MIM capacitors, and three layers of interconnected metal (M1-M3). A benzocyclobutene (BCB) spin-on dielectric is used as the interlayer dielectric (ILD) with 2 µm (M1-M2) and 3 µm (M2-M3) ILD spacing between the metal layer. Electroplated Au-based interconnects are used for the metallization layers, where M1 has a thickness of 1 µm, and M2 and M3 have a thickness of 2 µm. In this design, thin-film micro-strip lines (TFMLs) can be realized with M1 as the ground and M3 as the signal line [14].

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spacing between the metal layer. Electroplated Au-based interconnects are used for the Electronics 2021, 10, x FOR PEER REVIEWmetallization layers, where M1 has a thickness of 1 µm, and M2 and M3 have a thickness 3 of 10 of 2 µm. In this design, thin-ﬁlm micro-strip lines (TFMLs) can be realized with M1 as the ground and M3 as the signal line [14].

FigureFigure 2. Cross-sectional 2. Cross-sectional view of the view 0.5 µm of indium the 0.5 phosphide µm indium double-heterojunction phosphide bipolardouble-heterojunction bipolar transistortransistor (InP DHBT) (InP technology. DHBT) technology. 2.1. Parasitic Substrate Mode Suppression 2.1.In a Parasitic multi-layer Substrate integrated circuit, Mode thin-film Suppression microstrip lines (TFMLs) are usually used to transmit signals [15]. To achieve integration with an active circuit, a bulk substrate needs to beIn added a multi-layer under the TFML. integrated This structure circuit, requires interlayer thin-film interconnection microstrip and, lines (TFMLs) are usually therefore,used ato defective transmit structure signals on M1, [15]. such asTo a connectionachieve tointegration transistors below with the groundan active circuit, a bulk substrate plane, thin-film resistors (TFRs), and series capacitors. In addition, a typical RF pad uses a coplanarneeds ground–signal–ground to be added under (GSG) the layout TFML. with ground This slots. struct Allure of these requires ground plane interlayer interconnection and, fenestrationstherefore, may a excite defective the bulk substratestructure parasitic on modes. M1, such as a connection to transistors below the To eliminate the parasitic modes, it is feasible to set a number of metallized backside- viasground or insert plane, a dielectric thin-film insertion layerresistors above the(TFRs), bulk substrate and series [16]. However, capacitors. the In addition, a typical RF backsidepad viauses occupies a coplanar a large amount ground–signal–ground of the chip area and reduces integration.(GSG) layout The method with ground slots. All of these of insertingground a plane substrate fenestration insertion layers has may a limited excite suppression the bulk effect substrate on the parasitic parasitic modes. mode, and the realization of the process is difficult. To studyTo theeliminate resonance the phenomena parasitic caused modes, by the parasitic it is feasible modes, the to HFSS set model a number is of metallized backside- establishedvias or by insert taking thea dielectric series capacitor insertion as an example, layer as shown above in Figure the bulk3. In this substrate model, [16]. However, the back- the size of the substrate InP is 1.06 × 1 × 0.1 mm3 (l × w × h), and the size of the capacitance is 55side× 55 viaµm2 ,occupies and the window a large size is amount 60 × 60 µm 2of; all the conductors chip area are made and of gold.reduces integration. The method of insertingMode indices a substrate of the main insertion resonances arelayer shown has in a Figure limited3a. The suppression insertion loss effect on the parasitic mode, increases as frequency increases; simultaneously, several resonant frequencies are observed in theand figure, the indicatingrealization that energyof the is process coupled into is difficult. the substrate through the opening window inTo the study ground plane.the resonance The parasitic modesphenomena bounce at thecaused edge of by the substratethe parasitic due modes, the HFSS model to theis established limited substrate by volume taking and createthe series resonance capacitor at certain frequencies. as an example, The resonant as shown in Figure 3. In this frequency can be approximated as: model, the size of the substrate InP is 1.06 × 1 × 0.1 mm3 (l × w × h), and the size of the r c m 2 n 2 p 2 capacitance is 55f × 55= µm√ 2, and the+ window+ size is 60 × 60 µm(6)2; all conductors are made of mnp 2 ε l w h gold. r where l, w, and h are the length, width, and height of the dielectric substrate, respectively, and m, n, and p are resonance mode indices, which are equivalent to the half-wavelength number of the corresponding dimension. The magnitude of the electric field in the InP substrate is shown in Figure3b, where the resonant frequency is 180 GHz. It can be clearly seen that the electric field maximum distribution is equal to the mode indices

(a) (b) Figure 3. Simulation S-parameters of a series capacitor with an opening window in the ground plane. (a) S-parameters of a series capacitor with an opening window in the ground plane; (b) magnitude plot of the electric field in the InP substrate observed at f3,3,0 = 180 GHz.

Mode indices of the main resonances are shown in Figure 3a. The insertion loss increases as frequency increases; simultaneously, several resonant frequencies are observed in the figure, indicating that energy is coupled into the substrate through the opening window in the ground plane. The parasitic modes bounce at the edge of the substrate due

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Figure 2. Cross-sectional view of the 0.5 µm indium phosphide double-heterojunction bipolar transistor (InP DHBT) technology.

2.1. Parasitic Substrate Mode Suppression In a multi-layer integrated circuit, thin-film microstrip lines (TFMLs) are usually used to transmit signals [15]. To achieve integration with an active circuit, a bulk substrate needs to be added under the TFML. This structure requires interlayer interconnection and, therefore, a defective structure on M1, such as a connection to transistors below the ground plane, thin-film resistors (TFRs), and series capacitors. In addition, a typical RF pad uses a coplanar ground–signal–ground (GSG) layout with ground slots. All of these ground plane fenestrations may excite the bulk substrate parasitic modes. To eliminate the parasitic modes, it is feasible to set a number of metallized backside- vias or insert a dielectric insertion layer above the bulk substrate [16]. However, the backside via occupies a large amount of the chip area and reduces integration. The method of inserting a substrate insertion layer has a limited suppression effect on the parasitic mode, Electronics 2021, 10, 1654 4 of 12 and the realization of the process is difficult. To study the resonance phenomena caused by the parasitic modes, the HFSS model is established by taking the series capacitor as an example, as shown in Figure 3. In this (m, n, p) = (3, 3, 0), which is in agreement with f in Equation (6). Because the thickness 3, 3, 0 3 model,of the the chip size is onlyof the 100 substrateµm, there isInP no is vertical 1.06 × resonance 1 × 0.1 mm below ( 424l × GHzw × h (m,), and n, p = the 0, 0, size 1); of the capacitancethat is, p ≡is 055 below × 55 424µm GHz.2, and the window size is 60 × 60 µm2; all conductors are made of gold.

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to the limited substrate volume and create resonance at certain frequencies. The resonant frequency can be approximated as:

222 cm  n  p f =++ (6) mnp ε    2 r lwh  

where l, w, and h are the length, width, and height of the dielectric substrate, respectively, and m, n, and p are resonance mode indices, which are equivalent to the half-wavelength number of the corresponding dimension. The magnitude of the electric field in the InP substrate is shown in Figure 3b, where the resonant frequency is 180 GHz. It can be clearly seen that the electric field maximum distribution is equal to the mode indices (m, n, p) = (a) (b) (3, 3, 0), which is in agreement with f3, 3, 0 in Equation (6). Because the thickness of the chip Figure 3.Figure Simulation 3. Simulation S-parameters S-parametersis only of 100 a of series aµm, series capacitorthere capacitor is no wi with thvertical anan opening opening resonance window window inbelow the inground the 424 ground plane.GHz plane. ((am,) S-parameters n, (pa )= S-parameters 0, 0, of 1); a that ofis, p ≡ a series capacitorseries capacitor with withan opening an0 opening below window window 424 GHz. in in the the ground ground plane;plane; ( b(b) magnitude) magnitude plot plot of the of electricthe electric ﬁeld infield the InPin the substrate InP substrate observedobserved at f3,3,0 = at 180f3,3,0 GHz.= 180 GHz. Because the electromagnetic waves leaking into the InP dielectric substrate need to form a stable standing wave and then resonate, the addition of backside vias can prevent Because the electromagnetic waves leaking into the InP dielectric substrate need to the generationMode indices of standing of the main waves resonances and eliminat aree shown resonance. in Figure Figure 3a. 4 shows The insertion a two-backside loss in- form a stable standing wave and then resonate, the addition of backside vias can prevent the creases as frequency increases; simultaneously, several resonant frequencies are observed via generationcapacitor ofphoto standing and waves its simulation and eliminate and resonance. measurement Figure4 showsresults. a two-backsideThis backside via via ar- inrangement thecapacitor figure, with photo indicating the and purpose its simulation that of energy breaking and measurementis coupled standing results.into waves the This can substrate backside eliminate viathrough the arrangement resonance the opening gen- windoweratedwith by thein thethe purpose parasiticground of breaking plane. mode, standingThe and parasitic this waves achiev mo canementdes eliminate bounce is theapplied at resonance the toedge the generated of design the substrate by of the the pro- due posedparasitic amplifier. mode, and this achievement is applied to the design of the proposed ampliﬁer.

(a) (b)

FigureFigure 4. ( a4.) Capacitance(a)Capacitance photo, photo, equivalent equivalent circuit model, circuit and model, (b) S-parameters. and (b) S-parameters.

2.3. Equivalent Circuit Model of Transistor The equivalent circuit model is the base of the transistor. As the frequency increases, the parasitic parameters have a significant impact on the device. Due to the use of devices

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2.2. Equivalent Circuit Model of Capacitor In addition to building the HFSS capacitor model, we also establish an equivalent circuit model of the capacitor to achieve accurate matching network analysis. Figure4 shows the equivalent circuit model of the series capacitor model and its simulation results based on measurement results. This model adds two parallel capacitors Cp on the basis of the LCL model to be equivalent to the grounding capacitance caused by defects. As the defect gap spacing is constant, the parallel capacitance values in the equivalent circuit are equal. The simulation results show that the MIM capacitor density is 0.26 fF/µm2. The comparison of S-parameters in Figure4b shows that the equivalent circuit is con- sistent with the measured results, which is beneﬁcial to the design of the matching circuit. Electronics 2021, 10, x FOR PEER REVIEW 5 of 10 2.3. Equivalent Circuit Model of Transistor The equivalent circuit model is the base of the transistor. As the frequency increases, the parasitic parameters have a signiﬁcant impact on the device. Due to the use of devices of differentof different sizes sizes under under the the same same process,process, we we use use the the method method of 3Dof 3D simulation simulation to extract to extract parasiticparasitic parameters parameters described described in [[17].17]. TheThe equivalent equivalent circuit circuit is shown is shown in Figure in Figure5. 5.

(a) (b)

FigureFigure 5. Small-signal 5. Small-signal equivalent-circuit equivalent-circuit model model of (a)) InPInP DHBT DHBT and and (b ()b the) the internal internal device device [17]. [17].

FigureFigure 5a5 ashows shows the the small-signal equivalent-circuit equivalent-circuit model model of the of device. the device. Nine parame-Nine param- etersters are are used used to to ensure ensure equivalence to to the the inter-electrode inter-electrode impedance impedance effect. effect. The inductorsThe inductors and resistances of electrode contacts and posts are represented by Lbxi, Lcxi, and Lexi, and and resistances of electrode contacts and posts are represented by Lbxi, Lcxi, and Lexi, Rbxi, Rcxi, and Rexi, respectively. Figure5b shows the simpliﬁed AgilentHBT model, which andis Rbxi, used forRcxi, the and internal Rexi, device respectively. equivalent Figure circuit. 5b The shows extraction the simplified method of AgilentHBT each parameter model, whichis described is used infor detail the internal in [18]. Parametersdevice equivale biasednt under circuit.Vc =The 1.5 extrac V andtionIb = method 200 µA areof each parameterextracted is according described to thein detail above in method [18]. andParameters are listed biased in Table under1. A comparison Vc = 1.5 V between and Ib = 200 µAthe are model extracted and the according measured to results the above is shown method in Figure and6. are The listed large-signal in Table model 1. A is carriedcomparison betweenout completely the model in accordanceand the measured with the results steps in is [18 shown]; the description in Figure 6. is notThe repeated large-signal here. model is carried out completely in accordance with the steps in [18]; the description is not re- peatedTable here. 1. Small-signal equivalent circuit elements. Rbi Re Rc Rbe Cbci Rbci Gm0 τ Cbe (ΩTable) 1. (Small-signalΩ) (Ω) equivalent(Ω) circuit(fF) elements.(k Ω) (mS) (pS) (fF) 42 3 42.7 67 2.4 34.4 652 0.7 512 Rbi Re Rc Rbe Cbci Rbci Gm0 τ Cbe Cbexi Ccexi Cbcxi Lexi Lbxi Lcxi Rexi Rbxi Rcxi (Ω) (Ω) (Ω(fF)) (fF)(Ω) (fF) (fF)(pH) (pH)(kΩ) (pH) (mS) (Ω) (pS)(Ω ) (Ω(fF)) 42 3 42.7 67 2.4 34.4 652 0.7 512 4.5 24.2 15.5 10.5 9.5 11.1 0.87 1.35 0.78 Cbexi Ccexi Cbcxi Lexi Lbxi Lcxi Rexi Rbxi Rcxi (fF) (fF) (fF) (pH) (pH) (pH) (Ω) (Ω) (Ω) 4.5 24.2 15.5 10.5 9.5 11.1 0.87 1.35 0.78

(a) (b)

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of different sizes under the same process, we use the method of 3D simulation to extract parasitic parameters described in [17]. The equivalent circuit is shown in Figure 5.

(a) (b) Figure 5. Small-signal equivalent-circuit model of (a) InP DHBT and (b) the internal device [17].

Figure 5a shows the small-signal equivalent-circuit model of the device. Nine parameters are used to ensure equivalence to the inter-electrode impedance effect. The inductors and resistances of electrode contacts and posts are represented by Lbxi, Lcxi, and Lexi, and Rbxi, Rcxi, and Rexi, respectively. Figure 5b shows the simplified AgilentHBT model, which is used for the internal device equivalent circuit. The extraction method of each parameter is described in detail in [18]. Parameters biased under Vc = 1.5 V and Ib = 200 µA are extracted according to the above method and are listed in Table 1. A comparison between the model and the measured results is shown in Figure 6. The large-signal model is carried out completely in accordance with the steps in [18]; the description is not repeated here.

Table 1. Small-signal equivalent circuit elements.

Rbi Re Rc Rbe Cbci Rbci Gm0 τ Cbe (Ω) (Ω) (Ω) (Ω) (fF) (kΩ) (mS) (pS) (fF) 42 3 42.7 67 2.4 34.4 652 0.7 512 Cbexi Ccexi Cbcxi Lexi Lbxi Lcxi Rexi Rbxi Rcxi Electronics 2021, 10, 1654 6 of 12 (fF) (fF) (fF) (pH) (pH) (pH) (Ω) (Ω) (Ω) 4.5 24.2 15.5 10.5 9.5 11.1 0.87 1.35 0.78

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(a) (b)

Figure 6. MeasuredFigure 6. andMeasured simulated and simulated S-parameters S-parameters of of0.5 0.5 ×× 55 µmµm InPInP DHBT: DHBT: (a) real(a) S11real and S11 its image;and its (b )image; real S12 and(b) itsreal S12 and its image; (c) realimage; S21 and (c) real its S21 image; and its ( image;d) real (d )S22 real and S22 and its itsimage. image.

3. Amplifier Design 3. Amplifier Design Figure7 shows the schematic diagram of the proposed amplifier. The amplifier adopts Figurea five-stage 7 shows cascaded the CE topology,schematic and thediagram values of biasof the voltage, proposed series resistance, amplifier. and par- The amplifier adopts allela five-stage capacitance cascaded of all bases areCE uniform; topology, this also and applies the values to collectors of withbias differentvoltage, values. series resistance, Generally, the length of the DC bias line is constant, usually λ/4 at operating frequency, and paralleland forms capacitance an open-circuit of converterall bases with are the uniform; parallel capacitor. this also In thisapplies case, the to biascollectors circuit with different values.can be Generally, ignored in the the design length of the of matching the DC network. bias line However, is constant, the electrical usually length λ of/4 at operating frequency,the transmission and forms line an is inverselyopen-circuit proportional converter to the operating with the frequency; parallel therefore, capacitor. this In this case, quarter-wavelength bias circuit is only suitable for narrow-band amplifier designs. the bias circuitThe DC can bias be circuit ignored is incorporated in the design into the matchingof the matching network in thisnetwork. design. AllHowever, bias the electrical lengthlines have of thethe same transmission width, and their line length is inve is adjustedrsely accordingproportional to matching to the requirements. operating frequency; therefore, thisTable quarter-wavelength2 shows the input/output bias impedance circuit and is only output suitable power of for each narrow-band transistor amplifier derived from source-pull and load-pull simulation when the Q1 input power is −7 dBm at designs.140 GHz. The input power of the latter stage is the output power of the previous stage. For Theexample, DC bias the inputcircuit power is incorporated of Q2, −1.39 dBm, into is the the output matching power of network Q1. in this design. All bias lines have the same width, and their length is adjusted according to matching requirements.

Figure 7. Schematic diagram of the amplifier. The characteristic impedance and electrical length of the bias line are calculated at 140 GHz.

Table 2 shows the input/output impedance and output power of each transistor derived from source-pull and load-pull simulation when the Q1 input power is −7 dBm at 140 GHz. The input power of the latter stage is the output power of the previous stage. For example, the input power of Q2, −1.39 dBm, is the output power of Q1.

Table 2. Input/output impedance and output power of transistors.

Q1 Q2 Q3 Q4 Q5 Zs (Ω) 18.7 + j14.3 21.4 + j10.4 21.3 + j4.7 20.5 + j0.6 20.2 + j0.3 Zl (Ω) 21.1 + j32.3 33.4 + j29.7 33.9 + j30.1 33.6 + j30.0 33.6 + j30.0 Pout (dBm) −1.39 3.65 6.38 7.07 7.2

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(c) (d) Figure 6. Measured and simulated S-parameters of 0.5 × 5 µm InP DHBT: (a) real S11 and its image; (b) real S12 and its image; (c) real S21 and its image; (d) real S22 and its image.

3. Amplifier Design Figure 7 shows the schematic diagram of the proposed amplifier. The amplifier adopts a five-stage cascaded CE topology, and the values of bias voltage, series resistance, and parallel capacitance of all bases are uniform; this also applies to collectors with different values. Generally, the length of the DC bias line is constant, usually λ/4 at operating frequency, and forms an open-circuit converter with the parallel capacitor. In this case, the bias circuit can be ignored in the design of the matching network. However, the electrical length of the transmission line is inversely proportional to the operating frequency; therefore, this quarter-wavelength bias circuit is only suitable for narrow-band amplifier designs. Electronics 2021, 10, 1654 The DC bias circuit is incorporated into the matching network in this design. All7 bias of 12 lines have the same width, and their length is adjusted according to matching requirements.

FigureFigure 7.7. SchematicSchematic diagram diagram of of the the amplifier. ampliﬁer. The The characteristic characteristic impedance impedance and electrical and electrical length length of the ofbias the line bias are line calcu- are lated at 140 GHz. calculated at 140 GHz.

TableTable 2. Input/output 2 shows the impedance input/output and output impedance power ofand transistors. output power of each transistor derived from source-pull and load-pull simulation when the Q1 input power is −7 dBm at 140 GHz. The input powerQ1 of the latter Q2 stage is the Q3 output power Q4 of the previous Q5 stage.

For example,Zs (Ω) the input18.7 + j14.3power of 21.4Q2, +−1.39 j10.4 dBm, 21.3is the + j4.7output power 20.5 + j0.6of Q1. 20.2 + j0.3 Zl (Ω) 21.1 + j32.3 33.4 + j29.7 33.9 + j30.1 33.6 + j30.0 33.6 + j30.0 TablePout 2.(dBm) Input/output −impedance1.39 and ou 3.65tput power of transistors. 6.38 7.07 7.2 Q1 Q2 Q3 Q4 Q5 ZFigures (Ω) 8 compares18.7 + thej14.3 effect 21.4 of different + j10.4 bias 21.3 lines’ + j4.7 lengths 20.5 on circuit + j0.6 performance. 20.2 + j0.3 In Figure8a, the input impedance Z = 50 Ω is the characteristic impedance of the transmission Zl (Ω) 21.1 + j32.3 33.40 + j29.7 33.9 + j30.1 33.6 + j30.0 33.6 + j30.0 line, and the output impedance Zs1 is 18.7 − j14.3, which is the conjugate Zs of Q1. It Pout (dBm) −1.39 3.65 6.38 7.07 7.2 is clear that, although a bias circuit with a λ/4 bias line (red dotted line) is theoretically equivalent to an open circuit, it is still different from a true open circuit (green dashed line). As shown in Figure8a, the bias line we used reduces the insertion loss of the matching network above 80 GHz. The slope of the inflection point and its vicinity in Figure8a is carefully designed, and Figure8b shows a comparison of the maximum gain of Q1 under the matching network with different bias line lengths. It can be clearly observed that the gain is flat in the 70–95 GHz range, and this is only the boost effect of the input matching network. Adjusting the length of the bias line between Q1 and Q2, and Q2 and Q3, can reduce the loss of the matching network, thereby increasing the gain of the transistor that follows it, as shown in Figure8c,d. The matching network between Q3 and Q4 can make the gain of Q4 stay flat above 100 GHz, as shown in Figure8e. Because Q2 and Q3 are used to increase the gain, which affects the gain flatness of the amplifier, Q5 needs to be supplemented to balance the high gain at the 120 GHz range, as shown in Figure8f. After the matching networks are individually designed, they are fine-tuned again in the complete circuit to obtain the best performance. Under the combined effect of multiple matching networks, the amplifier maintains a constant gain in the broadband range, as shown in Figure9. The chip size is 1.2 × 0.7 mm2, including DC and RF pads, as shown in Figure 10. Electronics 2021, 10, x FOR PEER REVIEW 7 of 10

Figure 8 compares the effect of different bias lines’ lengths on circuit performance. In Figure 8a, the input impedance Z0 = 50 Ω is the characteristic impedance of the transmission line, and the output impedance Zs1 is 18.7 − j14.3, which is the conjugate Zs of Q1. It is clear that, although a bias circuit with a λ/4 bias line (red dotted line) is theoretically equivalent to an open circuit, it is still different from a true open circuit (green dashed line). As shown in Figure 8a, the bias line we used reduces the insertion loss of the matching network above 80 GHz. The slope of the inflection point and its vicinity in Figure 8a is carefully designed, and Figure 8b shows a comparison of the maximum gain of Q1 under the matching network with different bias line lengths. It can be clearly observed that Electronics 2021, 10, 1654 the gain is flat in the 70–95 GHz range, and this is only the boost effect of the8 ofinput 12 matching network.

(a) (b)

(e) (f)

Figure 8. ComparisonFigure 8. Comparison of matching of matching network network insertion insertion loss loss an andd transistortransistor gain gain under under different different bias lines. bias (a lines.) Input ( matchinga) Input matching network insertionnetwork insertion loss; (b loss;) Q1 ( bgain;) Q1 gain; (c) Q2 (c) Q2gain; gain; (d ()d Q3) Q3 gain; gain; ((ee)) Q4 Q4 gain; gain; (f) ( Q5f) Q5 gain. gain.

Electronics 2021, 10, x FOR PEER REVIEW 8 of 10

Adjusting the length of the bias line between Q1 and Q2, and Q2 and Q3, can reduce the loss of the matching network, thereby increasing the gain of the transistor that follows it, as shown in Figure 8c,d. The matching network between Q3 and Q4 can make the gain of Q4 stay flat above 100 GHz, as shown in Figure 8e. Because Q2 and Q3 are used to

Electronics 2021, 10, x FOR PEER REVIEWincrease the gain, which affects the gain flatness of the amplifier,8 of 10 Q5 needs to be supplemented to balance the high gain at the 120 GHz range, as shown in Figure 8f. After the matching networks are individually designed, they are fine-tuned again in the complete circuitAdjusting to obtain the length the of thebest bias performance. line between Q1 and Under Q2, and the Q2 andcombined Q3, can reduce effect of multiple matching the loss of the matching network, thereby increasing the gain of the transistor that follows

Electronics 2021, 10, 1654 it,networks, as shown in Figurethe amplifier 8c,d. The matching maintains network a betweenconstant Q3 andgain 9Q4 of 12 canin themake broadband the gain range, as shown in ofFigure Q4 stay 9. flat The above chip 100 sizeGHz, isas 1.2shown × 0.7 in Figuremm2 ,8e. including Because Q2 DC and andQ3 are RF used pads, to as shown in Figure 10. increase the gain, which affects the gain flatness of the amplifier, Q5 needs to be supplemented to balance the high gain at the 120 GHz range, as shown in Figure 8f. After the matching networks are individually designed, they are fine-tuned again in the complete circuit to obtain the best performance. Under the combined effect of multiple matching networks, the amplifier maintains a constant gain in the broadband range, as shown in Figure 9. The chip size is 1.2 × 0.7 mm2, including DC and RF pads, as shown in Figure 10.

Figure 9. FigureFigureSimulation 9. Simulation 9. Simulation S-parameters S-parameters of the S-parameters ampliﬁer. of the amplifier. of the amplifier.

2 FigureFigure 10. Chip 10. Chip photograph photograph of the ampliﬁer of the MMIC.amplifier Size: MMIC. 1.2 × 0.7 Size: mm2. 1.2 × 0.7 mm .

4. On-Wafer4. On-Wafer Measurement Measurement Results Results The on-wafer measurements were performed using a Keysight PNA-X N5247B network analyzerThe on-wafer with Keysight measurements N5293AX01 (0~110were perfor GHz) frequencymed using extenders a Keysight (Keysight PNA-X N5247B net- Technologies,work analyzer Santa Rosa,with CA, Keysight USA) and N5293AX01 a Rohde & Schwarz (0~110 ZVA50 GHz) network frequency analyzer extenders (Keysight with Rohde & Schwarz ZC170 (110~170 GHz) frequency extenders (Rohde & Schwarz, Technologies,Figure 10. Chip Santa photographRosa, CA, USA) of and the a amp Rohdelifier & Schwarz MMIC. ZVA50 Size: network1.2 × 0.7 analyzer mm2. Munich,with Germany).Rohde & TheSchwarz measurement ZC170 results (110~170 are shown GHz) in Figurefrequency 11. extenders (Rohde & Schwarz, Munich, Germany). The measurement results are shown in Figure 11. 4. On-WaferThe measured Measurement S-parameter results Results displayed in Figure 11a show that the maximum gain of the amplifier is 19.5 dB at 146 GHz, and the 3 dB bandwidth is 56~161 GHz (relative bandwidthThe of on-wafer 96.8%). The measurementsreflection parameter wereS11 is below perfor −5 dBmed in the using range aof Keysight62~160 PNA-X N5247B net- GHz,work and analyzer S22 is below −with5 dB in Keysight the range of 45~170N5293AX01 GHz. The amplifier(0~110 provides GHz) saturationfrequency extenders (Keysight outputTechnologies, power of 6.5 Santa and 5.9 Rosa,dBm at CA,94 and USA) 140 GHz, and respectively, a Rohde as & shown Schwarz in Figure ZVA50 network analyzer 11b,c. The 1 dB compression output power of the PA is −4.7 dBm at 94 GHz when the with Rohde & Schwarz ZC170 (110~170 GHz) frequency extenders (Rohde & Schwarz, Munich, Germany). The measurement results are shown in Figure 11. The measured S-parameter results displayed in Figure 11a show that the maximum gain of the amplifier is 19.5 dB at 146 GHz, and the 3 dB bandwidth is 56~161 GHz (relative bandwidth of 96.8%). The reflection parameter S11 is below −5 dB in the range of 62~160 GHz, and S22 is below −5 dB in the range of 45~170 GHz. The amplifier provides saturation output power of 6.5 and 5.9 dBm at 94 and 140 GHz, respectively, as shown in Figure 11b,c. The 1 dB compression output power of the PA is −4.7 dBm at 94 GHz when the

Electronics 2021, 10, x FOR PEER REVIEW 9 of 10

Electronics 2021, 10, 1654 10 of 12 input power is −23 dBm. The amplifier starts to gain compression at a low input power; thus, it is more suitable for driving stages. The DC power consumption is 33.3 mW.

(a) (b) (c)

Figure 11. Comparison of measured and simulated results. The biases for all tests are VC = 1.5 V and VB = 0.9 V. (a) Small- Figure 11. Comparison of measured and simulated results. The biases for all tests are VC = 1.5 V and V = 0.9 V.(a) Small-signal signal S-parameter; (b) large-signal output power and gain at 94 GHz; (c) large-signal output power Band gain at 140 GHz. S-parameter; (b) large-signal output power and gain at 94 GHz; (c) large-signal output power and gain at 140 GHz. Table 3 shows the performance comparison of several InP HBT amplifiers. It is clear The measured S-parameter results displayed in Figure 11a show that the maximum that the CE amplifier has a higher gain, while the DA bandwidth is wider. The proposed gain of the amplifier is 19.5 dB at 146 GHz, and the 3 dB bandwidth is 56~161 GHz amplifier has excellent bandwidth performance compared with that of other CE cascaded (relative bandwidth of 96.8%). The reflection parameter S is below −5 dB in the range of amplifiers, because the DC bias circuit is incorporated into the11 matching network, and the 62~160 GHz, and S is below −5 dB in the range of 45~170 GHz. The amplifier provides bandwidth of the amplifier22 can be expanded by adjusting the length of the bias lines. Due saturationto the cascaded output topology, power the of 6.5proposed and 5.9 amplifie dBm atr has 94 anda higher 140 gain GHz, than respectively, that of DAs. as Each shown − intransistor Figure 11 inb,c. this Theamplifier 1 dB provides compression the highest output gain power and ofoutput the PApower is with4.7 dBm minimal at 94 DC GHz whenpower the consumption. input power This is − design23 dBm. has The the amplifieradvantages starts of the to high gain gain compression of CE amplifiers at a low and input power;the wide thus, bandwidth it is more of suitableDAs, but for the driving output stages.power is The low DC due power to the consumptionlack of power issynthe- 33.3 mW. sis. Table3 shows the performance comparison of several InP HBT amplifiers. It is clear that the CE amplifier has a higher gain, while the DA bandwidth is wider. The proposed Tableamplifier 3. Comparison has excellent of broadband bandwidth amplifiers performance based on the InP compared HBT process. with that of other CE cascaded amplifiers, because the DC bias circuit is incorporated into the matching network, and the Chip- Freq. RBbandwidth ofTechnology the amplifier can be expandedGain byTopology adjusting thePDC length P ofsat the bias lines. Due Ref. Size (GHz) (%)to the cascaded(ft/fmax topology, GHz) the proposed(dB) amplifier /Devices/Stages has a higher (mW) gain (dBm) than that of DAs. Each 2 transistor in this amplifier provides the highest gain and output power with minimal(mm ) DC [3] 40–222 138.9power 250 consumption. nm InP HBT This(375/650) design has 10 the advantages DA × 2 × of 4 the high 105 gain 8.5 of CE amplifiers 0.5 × 0.6 and [4] 40–185 128.9the wide 500 nm bandwidth InP DHBT of DAs,(350/400) but the output 10 power DA × is 2 low× 5 due to 96 the lack 10 of power 0.8 × 0.75 synthesis.

[5] DC–170 Table 200 3. Comparison 500 nm InP of DHBT broadband (360/490) ampliﬁers 12 based on DA the InP× 3 × HBT 5 process. 180 10 1.5 × 0.65

[6] DC–110 200 RB 500 nm InPTechnology DHBT (400/400) 13 Topology DA × 2 × 5 P 129 11.5P 1.7 ×Chip-Size 0.8 Ref. Freq. (GHz) Gain (dB) DC sat (%) (ft/fmax GHz) /Devices/Stages (mW) (dBm) (mm2) [8] 55–135 84.2 250 nm InP HBT (350/600) 27.3 CE × 2 × 4 1420 21.4 1.86 × 0.64 250 nm InP HBT [3] 40–222 138.9 10 DA × 2 × 4 105 8.5 0.5 × 0.6 [9] 115–150 26.4 250 nm InP(375/650) HBT (350/600) 29.5 CE × 2 × 5 1540 21.8 1.78 × 0.42 500 nm InP DHBT [4] 40–185 128.9 10 DA × 2 × 5 96 10 0.8 × 0.75 This work 56–161 96.8 500 nm InP(350/400) DHBT (350/535) 19.5 CE × 5 33.3 5.9 1.2 × 0.7 500 nm InP DHBT [5] DC–170 200 12 DA × 3 × 5 180 10 1.5 × 0.65 5. Conclusions(360/490) A five-stage500 nm broadband InP DHBT common-emitter amplifier is presented based on 0.5 µm InP [6] DC–110 200 13 DA × 2 × 5 129 11.5 1.7 × 0.8 DHBT technology.(400/400) The measurement results show that the PA provides a maximum gain 250 nm InP HBT sat [8] 55–135of 84.2 19.5 dB at 146 GHz with a 3 dB27.3 bandwidth CE of× 256–161× 4 GHz; 1420 P values 21.4are 5.9 and 1.86 ×6.50.64 dBm at 94 and(350/600) 140 GHz, respectively. The proposed broadband amplifier is suitable for 250 nm InP HBT [9] 115–150the 26.4 driver stage of the broadband 29.5system. CE × 2 × 5 1540 21.8 1.78 × 0.42 (350/600) 500 nm InP DHBT This work 56–161 96.8 19.5 CE × 5 33.3 5.9 1.2 × 0.7 (350/535)

Electronics 2021, 10, 1654 11 of 12

5. Conclusions A five-stage broadband common-emitter amplifier is presented based on 0.5 µm InP DHBT technology. The measurement results show that the PA provides a maximum gain of 19.5 dB at 146 GHz with a 3 dB bandwidth of 56–161 GHz; Psat values are 5.9 and 6.5 dBm at 94 and 140 GHz, respectively. The proposed broadband amplifier is suitable for the driver stage of the broadband system.

Author Contributions: Conceptualization, W.Y. and M.Z.; methodology, W.Y.; investigation, Y.H. and Q.Y.; formal analysis, Y.H.; software, Y.H.; data curation, B.W.; writing—original draft preparation, Y.H.; writing—review and editing, W.Y.; supervision, Y.S. and W.C. All authors have read and agreed to the published version of the manuscript. Funding: This research was funded by National Natural Science Foundation of China, grant number 61771057, and Science and Technology Innovation Action Plan of Shanghai, grant number 20590730400. Acknowledgments: The author sincerely thank the Beijing Institute of Radio Measurement and Testing and Beijing University of Posts and Telecommunications for on-wafer testing. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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