UUNIVERSITY OF SSOUTHERN CCALIFORNIA SCHOOL OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING EE 348: Lecture Supplement #3 Fall, 1998 Canonic Bipolar Junction Transistor Cells Choma & Trujillo
11.2.2.1. INTRODUCTION
The circuit configurations of linear signal processors realized in bipolar technology are as diverse as are the system operating requirements that these circuits are designed to satisfy. Despite topological diversity, most practical open loop linear bipolar circuits derive from interconnections of surprisingly few basic subcircuits. These subcircuits include the diode- connected bipolar junction transistor (BJT), the common emitter amplifier, the common base amplifier, the common emitter-common base cascode, the emitter follower, the Darlington connection, and the balanced differential pair. Because these open loop subcircuits underpin linear bipolar circuit technology, they are rightfully termed the canonic cells of linear bipolar circuit design.
By examining the low frequency performance characteristics of the canonic cells of linear bipolar technology, this section achieves two objectives. First, the forward gain, the driving point input resistance, and the driving point output resistance are catalogued for each canonic circuit. This information produces Thévenin and Norton I/O port equivalent circuits that expedite the analysis and design of multistage electronics. Second, the forthcoming work establishes a basis for prudent circuit design in that all analytical results are studied by highlighting the attributes and uncovering the limitations of each cell. The understanding that resultantly accrues paves the way toward systematic design procedures that yield optimal circuit architectures capable of circumventing observed subcircuit shortcomings.
11.2.2.2. SMALL SIGNAL MODEL
The fundamental tool exploited in the analyses that follow is the low frequency, small signal equivalent circuit of a bipolar junction transistor shown in Fig. (11.1a). This equivalent circuit, which applies to NPN and PNP discrete component and monolithic transistors, derives from the low frequency, large signal, NPN BJT model offered in Fig. (11.1b)[1]-[2]. As is depicted in Fig. (11.1c), the PNP large signal transistor model is topologically identical to its NPN counterpart. The only difference between the two models is a reversal in the direction of all controlled current sources and branch currents and a reversal in polarity of all assigned branch and port voltages. EE 348 University of Southern California J. Choma, Jr.
r r
b c
base collector c
i
r b i r p o
c r e
(a). emitter r r
b i c i
c collector baseb collecto
v
12c
i
1 1 c1
i 1 1
base b
v I v I
v e BE x CC ce 1 2 2 v v v ce
be be c
2 2
c r
emitter e
2 2
c (b). emitter
r r
b i c
i
c collector base b collecto
v
2 c 1
i
2 2 c2
i 2 2
base b
v I v I
e BE x CC v 2 ec 1 1 v v v
eb eb c ec
1 1
c r
emitter e
1 1
c (c). emitter
FIGURE (11.1). (a) Low Frequency, Small Signal Model Of A Bipolar Junction Transistor. (b) Low Frequency, Large Signal Model Of An NPN Bipolar Junction Tran- sistor. (c) Low Frequency, Large Signal Model Of A PNP Bipolar Junction Transistor.
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The large signal models in Figs. (11.1b) and (11.1c) are simplified to reflect transistor biasing that assures nominally linear device operation for all values of applied input signal voltages. A necessary condition for linear operation is that the internal emitter-base junction voltage, ve, be at least as large as the threshold voltage, say vγ , of the junction for all time; that is
v(t)> v , for all e g (11-1)
For silicon transistors, vγ is typically in the neighborhood of 700 mV to 750 mV. A second condition underlying transistor operation in its linear regime is that the internal base-collector junction voltage, vc, is never positive; that is
v(t)< 0 , for all c (11-2)
In the models of Figs. (11.1b) and (11.1c), rb represents the effective base resistance of a BJT, rc is its net internal collector resistance, and re is the net internal emitter resistance. All three resistances, and particularly rb, decrease monotonically with increasing quiescent base and [3]-[4] collector currents, IBQ and ICQ, respectively . The collector resistance also decreases with increases in the intrinsic collector-emitter voltage, vx. Large base, collector, and emitter resistances conduce reduced circuit gain, diminished gain-bandwidth product, and increased electrical noise. In view of these observations and in the interest of formulating a mathematically tractable analysis that produces conservative estimates of bipolar circuit performance, these resistances are usually interpreted as constants equal to their respective low current, low voltage values.
In a monolithic fabrication process, unacceptably large internal device resistances can be reduced by exploiting the fact that rb, rc, and re are inversely proportional to emitter-base junction injection area. This area is a designable parameter chosen to ensure that the transistor in question conducts the proper density of collector current. Unfortunately, the engineering price potentially paid for a reduction of device resistances through increases in junction area is circuit response speed, since the capacitances associated with transistor junctions are directly proportional to device injection area.
The current, IBE, in Figs. (11.1b) and (11.1c) is given approximately by A J E S v /n V I 5 ee f T (11-3) BE b F where AE is the aforementioned emitter-base junction injection area, JS, is the density of transistor β saturation current, and F is the forward, short circuit current transfer ratio. Moreover, nf is the injection coefficient of the emitter-base junction, ve is the internal junction voltage serving to forward bias the emitter-base junction, and
kT j V 5 (11-4) T q
Lecture Supplement #3 148 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. is the Boltzman voltage. In the latter expression, k is Boltzman's constant [1.38(10-23) joules -per- Kelvin degree], Tj is the absolute temperature of the emitter-base junction, and q is the magnitude of electron charge [1.6(10-19) coulombs].
[5] The current, ICC, derives from
I v ve /n f VT CC x I 5 A J e 12 11 (11-5) CC E S I V KF AF
[6] where IKF, which is proportional to AE, is the forward knee current of the transistor , and VAF, [7] which is independent of AE, is the forward Early voltage . Note that the base current, ib, is the current IBE, while the collector current, ic, is ICC. Thus, the static common emitter current gain (often referred to as the "DC beta"), hFE, of a bipolar junction transistor is
i I i v c CC c x h 5 5 5 b 12 11 (11-6) FE i I F I V b BE KF AF which is functionally dependent on both the collector current and the intrinsic collector-emitter volt- age.
Unlike the base, collector, and emitter resistances, the resistance, rπ, in the small sig- nal model of Fig. (11.1a) is not an ohmic branch element. It is a mathematical resistance that arises from the Taylor series expansion of the current, IBE, about the quiescent operating point, or Q-point, of the transistor. In particular, rπ, which is known as the emitter-base junction diffusion resistance, derives from
1 ]IBE 5 (11-7) r ] v p e |Q where it is understood that the indicated derivative is evaluated at the Q-point of the device. This Q-point is unambiguously defined by the zero signal, or static, values of the base current, IBQ, the collector current, ICQ, and the internal collector-emitter voltage, VXQ. Using (11-3), (11-6), and the + fact that ib IBE,
h n V FE f T r 5 (11-8) p I CQ
The inverse dependence of rπ on quiescent collector current renders rπ large at low collector current biases.
Similarly, ro, the forward Early resistance, derives from
Lecture Supplement #3 149 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
] I 1 CC 5 (11-9) r ] v o x |Q
It can be shown that
V 1 V XQ AF r 5 (11-10) o I CQ I 12 CQ I KF
Like rπ, ro is also large for low level biasing.
Finally, the parameter β, which is the low frequency, small signal, common emitter, short current gain (often more simply referred to as the "AC beta") of the transistor, is
b 5 g r m p (11-11) where gm, the forward transconductance of a BJT is
]ICC g 5 (11-12) m ] v e |Q
From (11-5), (11-6), (11-8), and (11-11),
I CQ b 5 h 12 (11-13) FE I KF
<< β To the extent that ICQ IKF, is nominally independent of both Q-point collector current and emit- ter-base junction injection area.
11.2.2.3. SINGLE INPUT-SINGLE OUTPUT CANONIC CELLS
DIODE-CONNECTED TRANSISTOR
The simplest of the single input-single output, or single ended, canonic cells for linear bipolar circuits is the diode-connected transistor offered in Fig. (11.2a). This transistor connection emulates the volt-ampere characteristics of a conventional PN junction diode. It can therefore be used in rectifier, voltage regulator, DC level shifting, and other applications that exploit
Lecture Supplement #3 150 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. conventional diodes. But unlike a conventional PN junction diode, the diode-connected transistor proves especially useful in current mirror biasing schemes. These and other similar circuits require that the base-emitter terminal voltage, v, of the diode track the base-emitter terminal voltage of a second, presumably identical transistor, over wide variations in junction operating temperatures.
If the voltages dropped across the internal base, collector, and emitter resistances are small, the intrinsic emitter-base junction voltage, ve, is approximately the indicated terminal voltage, v. Moreover, the intrinsic base-collector junction voltage, vc, is essentially zero. It follows that for
v > vγ, the transistor in the diode connection operates in its linear regime.
i5 I 1 i i
Q s s
c 1 1 v
v 5 V1 v R s
Q s d
2 2
(a). (b).
I I
test test
c c
r r
r c r c
b b
c 1 1
i i
x x
V V
test test
r b i r r b i
p x o 2 p x 2
c c
r r
e e
(c). (d).
FIGURE (11.2). (a) Diode-Connected Bipolar Junction Transistor. (b) The Small-Signal Equivalent Circuit Of The Diode In (a). (c) Low Frequency, Small Signal Model Of The Diode-Connected Transistor In (a). The Ratio, Vtest/Itest, Is The Small Signal Resistance, Rd,Presented At The Terminals Of The Diode-Con- nected Transistor. (d) The Model In (c) Approximated For The Case Of Very Large Early Resistance.
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In the subject diagram, the terminal voltage, v, is depicted as a superposition of a static voltage, VQ, and a signal component, vs. The resultant diode current, i, is a superposition of a quiescent current, IQ, and a signal current, is. The quiescent components of diode voltage and current arise from static power supplied to the diode circuit to ensure that the diode-connected device operates in its linear regime. On the other hand, the signal components are established by a time varying signal applied to the input port of the circuit in which the diode-connected transistor is embedded. In order to achieve reasonably linear processing of the applied input signal, the value of = + > VQ must be such as to ensure that v VQ vs vγ for all values of the time varying signal voltage, + > vs. Since vs can be positive or negative at any instant of time, the requirement, VQ vs vγ mandates that the amplitude of vs be sufficiently small.
The immediate impact of the small signal condition corresponding to the linearity re- + > quirement, VQ vs vγ, is that the small signal volt ampere characteristics of the diode are linear. And since the diode is a two terminal element, these characteristics can be modeled at low signal frequencies by a simple resistance, say Rd, as suggested by the single element macromodel offered in Fig. (11.2b). The resistance in the latter figure can be determined by using the small signal transistor model of Fig. (11.1a) to construct the small signal equivalent circuit of the diode- connected transistor shown in Fig. (11.2c). In this figure, the ratio of the test voltage, Vtest, to the test current, Itest, is the desired resistance, Rd. A straightforward KVL analysis confirms that
V () r 1 r | () r 1 r test o c b p R 5 5 r 1 (11-14) d I e b r test 1 1 o r 1 r 1 r 1 r o c b p
Ω Ω Ω Typically, ro is 25 k or larger, rc is smaller than 75 , rb is of the order of 100 , and rπ is in the Ω range of 1 k for a minimal geometry device. It follows that ro >> (rc+rb+rπ), and Rd can be approximated as
r 1 r b p R ' r 1 (11-15) d e b 1 1
Note that this terminal resistance is of the order of the low tens of ohms. For example, if rb = 100 Ω Ω β Ω , rπ = 1.2 k , re = 1 ohm, and = 100, Rd = 13.9 . It is instructive to note that the approximation, ro >> (rc+rb+rπ), collapses the model in Fig. (11.2c) to the structure in Fig. (11.2d), from which (11-15) follows immediately.
A variation of the diode scheme is the so-called VBE multiplier depicted in Fig. (11.3a). This circuit finds extensive use in regulator and level shifting applications that require either a series interconnection of more than one diode or a circuit branch voltage drop whose requisite value is a non-integral multiple of the base-emitter terminal voltage of a single diode.
Lecture Supplement #3 152 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
The circuit under consideration establishes a static terminal voltage, VQ, whose value is a designable multiple of the static base-emitter terminal voltage, VBEQ. To confirm this contention, observe that for static operating conditions, VQ is
V 5 R I 2 I 1 V (11-16) Q Y () Q CQ BEQ where the voltage component, VBEQ, of the net base-emitter terminal voltage, vbe, is
h 1 1 FE V 5 R I 2 I (11-17) BEQ X Q h CQ FE
The current, ICQ , is the static component of the net collector current, ic, and hFE is the collector current to base current transfer ratio defined by (11-6). An elimination of ICQ from the foregoing two expressions leads to
Lecture Supplement #3 153 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
i 1 i I 5 I
Q s Q
c 1 1 R i Y R c s
Y v h i FE 1 1 b 1 c Q V 1 V 1 Q 5 a R v FE Y BE v 11 V
R 2 ()R BEQ
X X
2 2 2
c (a). (b).
R I
Y test
c is
r 1
r c
b c 1
v i R
x V v s
r test
R b i
X p x 2
c 2 r
e c (c). (d).
FIGURE (11.3). (a) Schematic Diagram Of VBE Multiplier. (b) DC Macromodel Of The Multiplier In (a). (c) Low Frequency, Small Signal Equivalent Circuit Of The VBE Multiplier. (d) The Small Signal Equivalent Resistance At The Terminals Of The VBE Multiplier.
a R R FE Y Y V 5 11 V 1 I (11-18) Q R BEQ h 1 1 Q X FE where
h FE a 5 (11-19) FE h 1 1 FE
Lecture Supplement #3 154 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. is known as the static common base current gain (often referred to as the "DC alpha") of a BJT. Equation (11-18) suggests that the static electrical behavior of the VBE multiplier approximates a battery, whose voltage is controllable by the resistive ratio, RY/RX. The internal resistance of this effective battery is inversely dependent on (hFE + 1), and is therefore small. The macromodel in Fig. (11.3b) reflects the foregoing electrical interpretation. Note that for RY = 0 and RX infinitely large, the circuit in Fig. (11.3a) collapses to the diode-connected transistor of Fig. (11.2a), and VQ understandably reduces to VBEQ, the quiescent base-emitter terminal voltage of a diode-connected transistor.
+ > For VQ vs vγ , the transistor in the VBE multiplier operates linearly. Accordingly, the pertinent small signal terminal characteristics emulate a resistance, say Rv, which can be deter- mined by applying the model of Fig. (11.1a) to the circuit in Fig. (11.3a). The resultant equivalent circuit, simplified to reflect the realistic assumption of large ro, is shown in Fig. (11.3c), while Fig. (11.3d) postulates the small signal macromodel. An analysis of the latter circuit reveals that
a R X R ' R |R 1 R 12 (11-20) v X d Y R 1 R X d where
b a 5 (11-21) b 1 1 is the low frequency, small signal, common base, short circuit current gain (more simply referred to as the "AC alpha") of the transistor, and Rd is the resistance given by (11-14). For RY = 0, RX = ♠ β α ♠ reduces Rv to the expected result, Rv Rd. Note further that for >> 1 (which makes 1) and Rd << RX, Rv is essentially the small signal resistance presented at the terminals of a diode-connected transistor.
COMMON EMITTER AMPLIFIER
The most commonly used single ended canonic gain cell is the common emitter amplifier, whose NPN and PNP AC schematic diagrams are shown in Figs. (11.4a) and (11.4b), respectively. The AC schematic diagram delineates only the signal paths of a circuit. Thus, the biasing subcircuits required for linear operation of the transistors are not shown, thereby affording topological and analytical simplification. This simplification is accomplished without loss of engineering generality, for the results produced by an analysis of the AC schematic diagram reveal all salient performance traits of the common emitter configuration.
The common emitter amplifier is distinguished by the facts that signal is applied to the base of the transistor, and the resultant response is extracted as either the voltage, VOS, or the current, IOS, at the collector port. The effective load resistance terminating the collector to ground
Lecture Supplement #3 155 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
is indicated as RLT, while the signal source is represented as a traditional Thévenin equivalent circuit. Alternatively, a Norton representation of the input source can be used, with the understanding that the Norton equivalent signal current, say IST, is simply the ratio of the Thévenin signal voltage, VST, to the Thévenin source resistance, RST.
R R R R
ince outce ince outce
V V
OS OS
R R R R ST LT ST LT 1 1 V I V I ST OS ST OS 2 2
(a). (b).
R r r R
ince b c outce
c V
i OS
rp b i ro
R ST c R 1 LT V ST r e I 2 OS
(c).
FIGURE (11.4). (a) AC Schematic Diagram Of An NPN Common Emitter Amplifier. (b) AC Schematic Diagram Of A PNP Common Emitter Amplifier. (c) Small Signal, Low Frequency Equivalent Circuit Of The Common Emitter Amplifier.
The common emitter amplifier is capable of large magnitudes of voltage and current gains, moderately large input resistance, and very large driving point output resistance. An analytical confirmation of these contentions begins by drawing the small signal equivalent circuit of
Lecture Supplement #3 156 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. the amplifier. This structure is given in Fig. (11.4c) and is valid for either the NPN or the PNP versions of the amplifier. An analysis of the small signal model yields a voltage gain, Avce = VOS/VST, of
r r e o b 2 R r r 1 r 1 r 1 R LT o o c e LT A 5 2 (11-22) vce b r o R 1 r 1 r 1 1 1 r | r 1 r 1 R ST b p r 1 r 1 R e o c LT o c LT
This relationship can be simplified by exploiting the fact that the internal emitter resistance, re, of a β >> << transistor, is small. Thus, re/ro and re (ro + rc + RLT), thereby implying
b R eff LT A ' 2 (11-23) vce R 1 r 1 r 1 b 1 1 r ST b p () eff e where
r o b D b (11-24) eff r 1 r 1 R o c LT is an attenuated version of the AC beta for the utilized transistor This effective beta approximates β + itself, since ro >> (rc RLT) is typical.
In concert with earlier arguments, (11-23) confirms a diminished magnitude of gain for large internal device resistances. Note also that phase inversion, as inferred by the negative sign in either (11-22) or (11-23), prevails between the Thévenin source voltage, VST, and the voltage sig- nal response, VOS. Finally, observe that large magnitudes of voltage gain are possible in the β common emitter orientation when eff is sufficiently large.
The driving point input resistance, Rince, of the common emitter amplifier can be de- termined as the ratio, Vx/Ix, for the test structure depicted in Fig. (11.5a). It is easily shown that
R 5 r 1 r 1 b 1 1 r r 1 r 1 R (11-25) ince b p eff e | o c LT
<< Since re (ro + rc + RLT), (11-25) collapses to
R ' r 1 r 1 ( b 1 1) r (11-26) ince b p eff e
Similarly, the driving point output resistance, Routce, derives as the Vx/Ix ratio of the equivalent circuit offered in Fig. (11.5b). In particular,
Lecture Supplement #3 157 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
b r e R 5 r 1 r | r 1 r 1 R 1 1 1 r (11-27) outce c e p b ST r 1 r 1 r 1 R o e p b ST
Since the model resistance, rπ, varies inversely with collector bias current, Rince is moderately large when the common emitter transistor is biased at low currents. On the other hand, Routce is very large since (11-27) confirms Routce > ro.
R r r
ince b c
c
i
r r
p b i o 1 I V c x x R 2 LT r e
(a).
r r R
b c outce
c
i
r r
p b i o 1 c V I R x x ST 2 r e
(b).
FIGURE (11.5). (a) Small Signal Test Structure Used To Determine The Driving Point Input Resistance Of The Common Emitter Amplifier. (b) Small Signal Test Struc- ture Used To Determine The Driving Point Output Resistance Of The Common Emitter Amplifier.
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When the foregoing results are simplified to reflect the practical special case of a very large forward Early resistance, ro, the cumbersome small signal equivalent circuit of Fig. (11.4c) reduces to a small signal macromodel useful for design oriented circuit analysis of multistage amplifiers. To this end, note that a large ro produces a driving point common emitter input resistance that is independent of the terminating load resistance. Such independence implies no internal feedback from the output to input ports. It follows that the small signal volt-ampere characteristics at the input port of a common emitter amplifier can be modeled approximately by a simple resistance of value, Rince, as defined by (11-26). On the other hand, the large driving point output resistance, Routce, suggests that a prudent output port model of a common emitter stage is a Norton equivalent circuit. The Norton, or short circuit, output current is proportional to the applied input signal voltage, VST, as depicted in Fig. (11.6a). Alternatively, it can be expressed as a
proportionality of the Norton input signal current, IST, as suggested in Fig. (11.6b). In the former
figure, the Norton current is
c V
OS R
ST
R G R R V 1 ince fce ST outce LT V ST 2
(a).
c c V
OS
I R R A I R R ST ST ince ice ST outce LT
(b).
FIGURE (11.6). (a) Small Signal Macromodel Of A Common Emitter Amplifier In Which The Norton Output Port Circuit Uses A Voltage Controlled Current Source. (b) Small Signal Macromodel Of A Common Emitter Amplifier In Which The Norton Output Port Circuit Uses A Current Controlled Current Source.
Lecture Supplement #3 159 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
V A V OS vce ST G V 5 lim I 5 lim 2 5 lim 2 (11-28) fce ST OS ➛ ➛ R ➛ R R LT 0 R LT 0 LT R LT 0 LT
Subject to the assumption of large ro,
A vce b G 5 lim 2 ' (11-29) fce R ➛ 0 R R 1 r 1 r 1 () b 1 1 r LT LT ST b p e
Recalling (11-11), this effective forward transconductance of the amplifier can be expressed in terms of the transconductance, gm, of the transistor utilized in the amplifier. Specifically, g m G ' (11-30) fce r 1 r 1 R e b ST 1 1 g r 1 m e r p
In the macromodel of Fig. (11.6a), Routce is very large by virtue of ro. Accordingly, the parallel combination of Routce and RLT is essentially RLT, thereby implying an approximate common emitter voltage gain of
A ' 2 G R (11-31) vce fce LT
For the alternative macromodel in Fig. (11.6b), the Norton current is
V ST A I 5 A 5 lim I 5 G V (11-32) ice ST ice OS fce ST R ➛ ST R LT 0
Since VST = RSTIST, it follows that Aice is, for large ro,
R ST A 5 G R ' b (11-33) ice fce ST R 1 r 1 r 1 () b 1 1 r ST b p e
Note that the Norton current proportionality, Aice, which is, in fact, the approximate ratio of the indicated output current, IOS, to the Norton source current, IST, in the common emitter configuration, is always smaller than β.
EXAMPLE (11.2.2-1)
Transistor Q1 in the amplifier depicted in Fig. (11.7a) is fundamentally a common emitter configuration since input signal is applied to its base terminal and the output voltage signal
Lecture Supplement #3 160 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
response is extracted at its collector. The amplifier uses coupling capacitors, Ci and Co, at its input and output ports. The input coupling capacitor, Ci, blocks the flow of static current in the source signal branch consisting of the series interconnection of the voltage, VS, and the Thévenin source resistance, RS. Accordingly, Ci precludes RS from affecting the biasing of both transistors used in the amplifier. Similarly, the output coupling capacitor, Co, blocks the flow of static current in the external load resistance, RL. Thus, both Ci and Co can be viewed as open circuits for DC considerations. But simultaneously, these capacitors can be rendered transparent for AC situations by choosing them sufficiently large so that they emulate short circuits at the lowest frequency, say fl, of signal processing interest. In this problem, it is tacitly assumed that Ci and Co, which are perfect DC open circuits, behave as good approximations of AC short circuits.
Lecture Supplement #3 161 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
c V 1 CC
R R R
1 CC C out R o in
C c V i OS
c c Q1 R L c Q2
R
S V 1 i V S R R 2 2 EE c V 2 EE (a).
R R R
outce out outce
R c V R V
R ince OS ince OS
in
Q1 Q1 c c R R R CC L LT
R R d R S ST R 1 1 1 V K V S R R ST S R 2 2 EE 2 EE
(b). (c).
FIGURE (11.7). (a) Common Emitter Amplifier With Capacitively Coupled Input And Output Signal Ports. (b) AC Schematic Diagram Of The Amplifier In (a). (c) Simplified AC Schematic Diagram Of The Amplifier In (a).
The subject amplifier utilizes a diode connected transistor (Q2) for temperature compensation of the static collector current conducted by transistor Q1. For simplicity, assume that these Ω Ω Ω two transistors have identical small signal parameters of rb = 90 , rc = 55 , re = 1.5 , rp Ω Ω β Ω = 970 , ro = 42 k , and = 115. Let the indicated circuit parameters be R1 = 2.2 k , R2 = Ω Ω Ω Ω Ω 1.3 k , REE = 75 , RCC = 3.9 k , RL = 1.0 k , and RS = 300 . Assuming that these circuit variables ensure linear operation of both devices, determine the small signal voltage
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gain, Av = VOS/VS, the driving point input resistance, Rin, and the driving point output resistance, Rout, of the amplifier. Finally, calculate the requisite minimum values of the input and output coupling capacitors, Ci and Co, such that the lowest frequency, fl, of interest is 500 Hz.
SOLUTION: (11.2.2-1)
(1). The first step of the solution process entails drawing the AC schematic diagram of the subject amplifier. By casting this diagram in the form of the canonic cell shown in Fig. (11.4a), the gain and resistance expressions provided above can be exploited directly to assess the small signal performance of the circuit at hand. Such a solution tack maximizes design-oriented understanding by avoiding the algebraic tedium implicit to an analysis of the entire small signal equivalent circuit of the amplifier.
To the foregoing end, observe that transistor Q2 operates in its linear regime as a diode. It can therefore be viewed as the two terminal resistance, Rd, given by (11-14) or (11-15). Since Ω the Early resistance is large, the latter expression can be used to arrive at Rd = 10.64 .
Since the power supply voltage, VEE, is presumed ideal in the sense that it contains no signal component, the resultant series combination of Rd and R2 returns the base of transistor Q1 to ground, as depicted in Fig. (11.7b). Similarly, R1 appears in shunt with the series intercon- nection of Rd and R2, since VCC, like VEE, is also presumed to be an ideal constant (zero sig- nal component) source of voltage. The AC schematic diagram of the input port is completed by noting that the AC short circuit nature of the coupling capacitance, Ci, effectively connects the Thévenin representation of the signal source directly between the base of Q1 and ground.
At the output port of the amplifier, RCC connects between the collector and ground since, as already exploited, VCC is an AC short circuit. Moreover, the external load resistance, RL, shunts RCC, as shown in Fig. (11.7b), because Co behaves as an AC short circuit. The AC schematic diagram is completed by inserting the emitter degeneration resistance, REE, as a series element between ground and the emitter of transistor Q1.
(2). The diagram in Fig. (11.7b) can be straightforwardly collapsed to the simplified topology of Fig. (11.7c). In the latter circuit, the effective load resistance, RLT, is R 5 R | R 5 795.9V LT CC L
At the input port, the Thévenin resistance seen by the base of Q1 is
R 5 R | R 1 R | R 5 219.7V ST 1 () d 2 S
while the corresponding Thévenin signal voltage can be expressed as KSTVS, where, the volt- age divider, KST, is
Lecture Supplement #3 163 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
R | () R 1 R K 5 1 d 2 5 0.73 ST R | () R 1 R 1 R 1 d 2 S
The implication of this calculation is that insofar as the active transistor, Q1, is concerned, the biasing resistances, R1 and R2, cause a loss of more than 25% of the applied input signal.
(3). The resultant AC schematic diagram in Fig. (11.7c) is virtually identical to the canonic topology in Fig. (11.4a). Indeed, if the circuit resistance, REE, is absorbed into Q1 where it appears in series with the internal emitter resistance, re, the diagram is identical to the AC Ω schematic diagram of the canonic common emitter cell. Since (re + REE) = 76.5 is better Ω β than 560 times smaller than the resistance sum, (ro + rc + RLT) = 42.85 k , and = 115 is more than 63,000 times larger than the resistance ratio, (re + REE)/ro = 0.00182, the simplified expression in (11-23) can be used to evaluate the voltage gain, VOS/KSTVS, in Fig. β (11.7c). From (11-24), the effective small signal beta is eff = 112.7. Then, with re replaced Ω by (re + REE) = 76.5 , (11-23) gives V A 5 OS 5 2 8.99 volts/ vce K V ST S
It follows that the actual voltage gain of the amplifier in Fig. (11.7a) is
V OS A 5 5 K A 5 2 6.59 volts/v v V ST vce S
A better design, in the sense of achieving an adequate desensitization of circuit transfer characteristics with respect to parametric uncertainties, entails the use of a slightly larger β β emitter degeneration resistance, REE, selected to ensure that ( eff +1)(re + REE) ' effREE >> (RST + rb + rπ). For such a design, (11-23) produces K R A ' 2 ST LT v R EE
which is nominally independent of transistor parameters.
Ω (4). With re replaced by (re + REE) = 76.5 , (11-26) gives for the input resistance seen looking Ω into the base of transistor Q1 in Fig. (11.7c), Rince = 9.76 k . It follows that the driving point input resistance seen by the source circuit in Fig. (11.7b) is
R 5 R | R 1 R | R 5 757.6 ohm in 1 () d 2 ince
Lecture Supplement #3 164 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
(5). The output resistance, Routce, seen looking into the collector of transistor Q1 in the diagram Ω of Fig. (11.7c) derives from (11-27). With re replaced by (re + REE) = 76.5 , Routce = 2.49 megΩ. The resultant driving point output resistance seen by the load circuit in Fig. (11.7b) is
R 5 R | R 5 3,894 ohm out CC outce
The circuit output resistance is only a scant six ohms smaller than the collector biasing resis- tance, RCC, owing to the large value of Routce. In turn, the value of the latter resistance is dominated by the last term on the right hand side of (11-27), which is proportional to the large forward Early resistance, ro.
(6). The input coupling capacitance, Ci, can be calculated with the help of the input port macro- model of Fig. (11.8a). In this model, the subcircuit to the right of Ci in Fig. (11.7a) is replaced by its Thévenin equivalent circuit, which consists of the driving point input resistance, Rin, calculated above. The voltage transfer function of this input port is
V (jv) R vj () R 1R C i in in S i 5 V (jv) R 1 R S in S 11 vj () R 1R C in S i
An inspection of the foregoing relationship confirms that the dynamical effect of Ci on the ω ω π voltage transfer function response is minimized if (Rin ++RS)Ci >> 1. At = 2 fl, the µ value of Ci that makes the left hand side of this inequality equal to one is Ci = 0.30 F. ω Observe that at l(Rin + RS)Ci = 1,
V (jv ) R 1 R i l in j in 5 5 V (jv ) R 1 R 11 j R 1 R S l in S 2 in S
that is, the magnitude of the input port voltage transfer function is a factor of the square root of two, or 3 decibels (dB), below the transfer function value realized at signal frequencies that µ are significantly higher than fl. If this 3-dB attenuation is acceptable, Ci = 0.30 F is appropriate to the design requirement.
(7). The output coupling capacitance, Co, is calculated analogously by exploiting the macromodel concepts overviewed in Fig. (11.6a). To this end, the output port macromodel is offered in − Fig. (11.8b), where the effective forward transconductance, Gf, is such that Gf (Rout |RL) = Av, as calculated in Step #3. The voltage gain is seen to be
V (jv) vj () R 1R C OS out L o A (jv) 5 5 2 G () R |R v V (jv) f out L S 11 vj () R 1R C out L o
Lecture Supplement #3 165 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
which has an algebraic form that is similar to the foregoing transfer relationship for the amplifier input port. Thus, Co is 1 C > 5 0.065mF o 2p f () R 1 R l out L
Since the 0.30 mF input capacitor and the 0.065 mF output capacitor establish identical input and output port left half plane poles at the same frequency (fl), the resultant attenuation at fl is actually larger than 3-dB. If this enhanced attenuation is unacceptable, the smaller of the two computed capacitances can be made larger by a factor of three or so, thereby translating the associated pole frequency downward by a factor of three. In the present case, a plausible value of Co is Co > (3)(0.065 mF) = 0.2 mF.
It should be noted that the requisite two coupling capacitances are orders of magnitude too large for monolithic realization. Accordingly, if the subject amplifier is an integrated circuit, Ci and Co are necessarily off chip elements.
C C
o i
cV c V
i OS R
S
R G V R R 1 in f S out L V S 2
(a). (b).
FIGURE (11.8). (a) Input Port Macromodel Used In The Calculation Of The Input Coupling Capacitor, Ci. (b) Output Port Macromodel Used To Calculate The Output Coupling Capacitor, Co.
EXAMPLE (11.2.2-2)
When very large magnitudes of voltage gains are required, the output port of a common emitter configuration can be terminated in an active load, as opposed to the passive resistive load encountered in the preceding example. Consider, for example, the complementary, NPN-PNP transistor amplifier whose schematic diagram appears in Fig. (11.9a). The subcircuit containing transistors Q1 and Q2 is identical to that of the amplifier in Fig. (11.7a). Indeed, for the purpose of this example, let the resistances, R1, R2, REE, and RS, as well as the small signal parameters of transistors Q1 and Q2, remain at the values stipulated respectively
Lecture Supplement #3 166 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
for them in the preceding example. In the present diagram, the PNP transistor, Q3, along with its peripheral biasing resistances, R3, R4, and R5, supplants the resistance, RCC, in the previously addressed common emitter unit. Since no signal is applied to the base of Q3, the subcircuit consisting of Q3, R3, R4, and R5 serves only to supply the appropriate biasing current to the collector of transistor Q1. To the extent that this static current is invariant with temperature and the voltage signal response, VOS, established at the collector of Q1, the Q1 load circuit, functions as a nominally constant current source. As a result, the effective load resistance, indicated as RL in the subject figure, seen by the collector of Q1 is very large. In view of the absence of an external load appended to the output port, the resultant voltage gain of the amplifier is commensurably large.
Ω Ω Ω Let R3 = 1.8 k , R4 = 3.3 k , and R5 = 100 . Moreover, let the small signal parameters of Ω Ω Ω Ω Ω β the PNP transistor be rbp = 40 , rcp = 70 , rep = 9 , rpp = 1,100 , rop = 30 k , and p = 60. Assuming linear operation of all devices, determine the small signal voltage gain, Av = VOS/VS, the driving point input resistance, Rin, and the driving point output resistance, Rout, of the amplifier. As in the preceding example, the input coupling capacitance, Ci, can be pre- sumed to act as an AC short circuit for the signal frequencies of interest.
Lecture Supplement #3 167 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
c V 1 CC
R R 4 5
c Q3
R 3 R L
c c V 5 V 1 V O OQ OS R in R R R out
C 1 outce
i c c Q1
Q2 R S 1 V S R R 2 2 EE c V 2 EE
R (a).
outce
R c V
ince OS
R
STP Q1 Q3 R c L R R L R out ST R R R 1 3 4 5 K V c ST S R 2 EE
(b). (c).
FIGURE (11.9). (a) Common Emitter Amplifier With Active Current Source Load. (b) AC Schematic Diagram Of The Common Emitter Unit. (c) AC Schematic Diagram Of The Active, PNP Transistor Load.
Lecture Supplement #3 168 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
SOLUTION: (11.2.2-2)
(1). The AC schematic diagram of the amplifier in Fig. (11.9a) is given in Fig. (11.9b), where the PNP transistor load subcircuit is represented as an effective two terminal load resistance, RL. This representation is rendered possible by the fact that no signal is applied to the PNP load, which therefore acts only to supply biasing current to the collector of transistor Q1. In the diagram, KST, RST, and REE (which effectively appears in series with re, the internal emitter resistance of Q1) remain the same as in Example (11.2.2-1); namely, KST = 0.733, RST = Ω Ω 219.7 , and REE = 75 .
(2). The AC schematic diagram of the Q3 subcircuit alone appears in Fig. (11.9c). A comparison of this figure with that shown in Fig. (11.9b) suggests that the subject diagram represents a PNP common emitter amplifier under zero signal conditions. In particular, the Thévenin Ω source resistance seen by the base of the PNP unit is RSTP = R3|R4 = 1,165 , while the Ω emitter degeneration resistance of this subcircuit is R5 = 100 . It follows that the effective AC load resistance, RL, terminating the collector port of Q1 is the driving point output Ω Ω resistance of a common emitter stage. With rc D rcp = 70 , rb D rbp = 40 , re D (rep + R5) Ω Ω Ω Ω = 109 , rp D rpp = 1.1 k , RST D RSTP = 1,165 , ro D rop = 30 k , and b D bp = 60, (11- Ω 27) yields Routce D RL = 111.5 k .
(3). The voltage gain, input resistance, and output resistance of the actively loaded common Ω Ω emitter amplifier can now be computed. For rc D rcn = 55 , rb D rbn = 90 , re D (ren + Ω Ω Ω Ω REE) = 76.5 , rp D rpn = 970 , RST D RSTN = 219.7 , ro D ron = 42 k , RLT D RL = Ω 111.5 k , and b D bn = 115, (11-24) gives an effective NPN transistor beta of beff = 31.46, and (11-23) yields a voltage gain of Avce = VOS/KSTVST = 2931.9. It follows that the small signal voltage gain of the stage at hand is Av = VOS/VS = KSTAvce = 2682.6 volts/volt. It should be noted that this voltage gain is the ratio of only the signal component, VOS, of the net output voltage, VO (which contains a quiescent component of VOQ), to the source signal voltage, VS.
(4). From (11-25), the driving point input resistance seen looking into the base of transistor Q1 in Ω Fig. (11.7b) is Rince = 3.54 k . Then,
R 5 R | () R 1 R | R 5 666.7 ohm in 1 d 2 ince
This input resistance differs slightly from the corresponding calculation in the preceding example owing to the reduction in the effective forward AC beta caused by the large active load resistance.
Lecture Supplement #3 169 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
(5). The resistance, Routce, seen looking into the collector of transistor Q1 remains the same as Ω calculated in Example (11.2.2-1); namely Routce = 2.49 meg . It follows that the driving point output resistance of the amplifier under investigation is
R 5 R | R 5 106.7V k out L outce
This large output resistance means that the actively loaded common emitter configuration is a relatively poor voltage amplifier. In particular, an output buffer is mandated to couple virtually any practical external load resistance to the amplifier output port. In addition to reducing the output resistance, such a properly designed and implemented output buffer can reliably establish and stabilize the quiescent output voltage, VOQ.
COMMON BASE AMPLIFIER
The second of the canonic linear bipolar gain cells is the common base amplifier. whose NPN and PNP AC schematic diagrams and corresponding small signal equivalent circuit appear in Figs. (11.10a) and (11.10b), respectively. As is confirmed below, the input resistance, Rincb, of this stage is very small and the output resistance, Routcb, is very large. Accordingly, the common base unit comprises a relatively poor voltage amplifier in the sense that its voltage gain, though potentially large, is a sensitive function of both the Thévenin source resistance, RST, and the Thévenin load resistance, RLT.
Although the common base amplifier is not well-suited for general voltage gain applications, it is an excellent current buffer, which is ideally characterized by zero input resistance, infinitely large output resistance, and unity current gain. When used for current buffering purposes, the common base amplifier rarely appears as a stand alone single stage amplifier since signal excita- tions, particularly at the input and the output ports of an electronic system are invariably formatted as voltages. Instead, it is invariably used in conjunction with an input voltage to current converter and/or an output current to voltage converter to achieve desired system performance characteristics.
The small signal analysis of the common base stage is considerably simplified if the assumption of large ro is exploited at the outset. To this end, the equivalent circuit shown in Fig. (11.10b) reduces to the structure of Fig. (11.11a). In the latter equivalent circuit, observe a signal emitter current, ies, that relates to the indicated signal base current, i, in accordance with the KCL constraint,
i 5 2 b 1 1 i (11-34) es
The signal component of the output current, IOS, is therefore expressible as
b I 5 2 b i5 i 5 a i (11-35) OS b 1 1 es es
Lecture Supplement #3 170 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. where (11-21) and (11-34) are used. The last result suggests the alternative model in Fig. (11.11b), which is a slightly more convenient version of the model in Fig. (11.11a) in that the current α controlled current source, ies, is dependent on the signal input port current, ies, as opposed to the signal current, i, that flows in the grounded base lead.
By inspection of the equivalent circuit in Fig. (11.11b), the small signal voltage gain, Avcb, of the common base cell is a R a R LT LT A 5 5 (11-36) vcb R 1 R R 1 r 1 12 a r 1 r ST d ST e p b where (11-21) is used once again and Rd is the diode resistance defined by (11-15). In contrast to the common emitter cell, the common base stage has no voltage gain phase inversion. But like the common emitter configuration, the common base voltage gain is directly proportional to the effective load resistance. It is also almost inversely proportional to the effective source resistance, given that the diode resistance, Rd, is small.
Lecture Supplement #3 171 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
R R
outcb outcb
V V
OS OS
R R R LT R LT incb incb R R ST I ST I 1 OS 1 OS V V ST ST 2 2
(a). (b).
r
o
R r r R
incb e c outcb
c c V OS b i R rp ST 1 i R V LT ST 2 r b I OS
(c).
FIGURE (11.10). (a) AC Schematic Diagram Of An NPN Common Base Amplifier. (b) AC Schematic Diagram Of A PNP Common Base Amplifier. (c) Small Signal, Low Frequency Equivalent Circuit Of The Common Base Amplifier.
Lecture Supplement #3 172 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
b i R r r
i outcb
es e c c V OS
R rp ST R incb 1 i R V LT ST 2 r b I OS
(a).
a i R
r es r outcb i e c
es
c V OS
R rp ST R incb 1 i R V LT ST 2 r b I OS
(b).
FIGURE (11.11). (a) The Equivalent Circuit Of Fig. (11.10c), Simplified For The Case Of Very Large Early Resistance, ro. (b) Modification Of The Circuit In (a) In Which The Current Controlled Current Source Is Rendered Dependent On The Input Signal Current, ies.
Although the voltage gain is vulnerable to uncertainties in the terminating load and source resistances, the common base current gain, Aicb, is virtually independent of RLT and RST. This contention follows from the fact that Aicb, which is the ratio of IOS to the Norton equivalent source current, VST/RST, is R a R ST ST A 5 A 5 (11-37) icb R vcb R 1 R LT ST d
Lecture Supplement #3 173 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
which is independent of RLT (to the extent that the Early resistance, ro, can indeed be ignored). Since the signal in a current-driven amplifier is likely to have a large source resistance, RST >> Rd, ♠ α which implies Aicb , independent of RLT and RST. Note that this approximate current gain is essentially unity, since α, as introduced by (11-21), approaches one for the typically encountered circumstance of large β.
The input and output resistances of the common base amplifier follow immediately from an analysis of the model in Fig. (11.11b). In particular, the driving point input resistance, Rincb, is
V ST R 5 5 r 1 12 a r 1 r 5 R (11-38) incb i e p b d es |R 5 0 ST whose numerical value is of the order of only a few tens of ohms. On the other hand, the driving α point output resistance, Routcb, is infinitely large since VST = 0 constrains ies, and thus ies, to zero. α In turn, ies = 0 means that RLT in Fig. (11.11b) faces an open circuit, whence Routcb = .
To the extent that the common base amplifier is excited from a signal current source and that the forward Early resistance of the utilized transistor is very large, the common base amplifier is seen to have almost unity current gain, very low input resistance, and infinitely large output resistance. Its transfer characteristics therefore approximate those of an ideal current buffer. Of course, the finite nature of the forward Early resistance renders the observable driving point output resistance of a common base cell large, but nonetheless finite. The actual output resistance can be determined as the Vx to Ix ratio in the AC schematic diagram of Fig. (11.12a). The requisite analysis is algebraically cumbersome owing to the presence of ro in shunt with the current controlled current source in the equivalent circuit of Fig. (11.10c). Fortunately, however, an actual circuit analysis can be circumvented by a proper interpretation of cognate common emitter results formulated earlier.
In order to demonstrate the foregoing contention, consider Fig. (11.12b), which depicts the AC schematic diagram for determining the driving point output resistance, Routce, of a common emitter amplifier. The only difference between the two AC schematic diagrams in Fig. (11.12) is the topological placement of the effective source resistance, RST. In the common base stage, this source resistance is in series with the emitter of a transistor whose base is grounded. On the other hand, RST appears in the common emitter configuration as an element in series with the base of a transistor whose emitter grounded. It follows that (11-27) can be used to deduce an expression for Routcb, provided that in (11-27) RST is set to zero and re is replaced by (re + RST). The result is
b r 1 R e ST R 5 r 1 r 1 R | r 1 r 1 1 1 r (11-39) outcb c e ST p b r 1 R 1 r 1 r o e ST p b
For large RST and large ro, (11-29) reduces to
Lecture Supplement #3 174 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
R R
outcb outce
1 1 V I V I x x R x x 2 ST 2 R ST
(a). (b).
FIGURE (11.12). (a) AC Schematic Diagram Appropriate To The Computation Of The Driving Point Output Resistance Of A Common Base Amplifier. (b) AC Schematic Diagram Pertinent To Computing The Driving Point Output Resistance Of A Common Emitter Amplifier.
R ' b 1 1 r (11-40) outcb o which is an extremely large output resistance.
The common base stage is generally used in conjunction with a common emitter amplifier to form the common emitter-common base cascode, whose schematic diagram is shown in Fig. (11.13). In this application, the common emitter stage formed of transistor Q1, the emitter degeneration resistance, REE, and the biasing elements, R1 and R2, serves as a transconductor that converts the input signal voltage, VS, to a collector current whose signal component is i1s. Note that such conversion is encouraged by the fact that the effective load resistance, RLeff, terminating the collector of Q1, is the presumably low input resistance of the common base stage formed of transistor Q2 and the biasing resistances, R3 and R4. Since the current gain of a common base stage is essentially unity, Q2 translates the signal current in its emitter to an almost identical signal current flowing through the collector load resistance, RL. The latter element acts as a current to voltage converter to establish the signal component, VOS, of the net output voltage, VO.
The analysis of the common emitter-common base cascode begins by representing the collector port of the common emitter configuration by its Norton equivalent circuit. Assuming that the input coupling capacitor, C1, is sufficiently large to enable its replacement by a short circuit over the signal frequency range of interest, the pertinent AC schematic diagram is the circuit in Fig. (11.14a), where Ins symbolizes the Norton, or short circuit, signal current conducted by the collector of transistor Q1. The corresponding small signal equivalent circuit appears in Fig. (11.14b), where the Early resistance is tacitly ignored, the effective source resistance, RST, seen by the base of Q1 is
Lecture Supplement #3 175 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
c V 1 CC
R R
3 L
c V 5 V 1 V O OQ OS R out
c Q2
C R 2 2 R Leff cc R in R i 5 I 1 i 1 1 1Q 1s
C
1 c Q1
R S R R 1 2 EE V S c 2 V 2 EE
FIGURE (11.13). Schematic Diagram Of A Common Emitter-Common Base Cascode. The Common Emitter Stage Formed Of Transistor Q1 And Its Peripheral Elements Acts As A Voltage To Current Converter. Transistor Q2 And Its Associated Biasing Elements Functions As A Current Amplifier, While The Load Resistance, RL, Acts As A Current To Voltage Converter.
Lecture Supplement #3 176 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
I
ns
Q1 c c
R S R R R 1 1 2 EE V S 2
(a). r r R b c ns
i
R rp b i ST I c ns 1 K V r ST S e 2
(b).
FIGURE (11.14). (a) AC Schematic Diagram Used To Calculate The Norton Equivalent Output Circuit Of The Common Emitter Subcircuit In The Cascode Configuration Of Fig. (11.13). (b) Small Signal Model Of The AC Circuit In (a).
R 5 R R R (11-41) ST S | 1| 2 and the voltage divider, KST, is
R R 1| 2 K 5 (11-42) ST R R 1 R 1| 2 S
Using the model in Fig. (11.14b), it is a simple matter to show that
Lecture Supplement #3 177 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
I 5 b i 5 G V (11-43) ns ns S where Gns, which can be termed the Norton transconductance of the common emitter stage, is
b K ST G 5 (11-44) ns R 1 r 1 r 1 b 1 1 r ST b p e
The Norton output resistance, Rns, is infinitely large by virtue of the assumption of infinitely large Early resistance.
The foregoing results permit drawing the AC schematic diagram of the common base component of the common emitter-common base cascode in the topological form depicted in Fig. (11.15a). From the corresponding small signal equivalent circuit in Fig. (11.15b), which assumes that the capacitor, C2, behaves as an AC short circuit and which once again ignores transistor Early resistance, the voltage gain, say Av, follows immediately as
V a b K R OS ST L A 5 5 2 a G R 5 2 (11-45) v ns L V R 1 r 1 r 1 b 1 1 r S ST b p e
The driving point output resistance, Rout, like the Norton output resistance of the common emitter stage, is infinitely large. In fact, Rout is a good approximation of infinity. Its numerical value β approaches ( + 1)ro, since the terminating resistance, Rns, seen in the emitter circuit of transistor Q2 is of the order of ro.
Equation (11-45) is similar in form to (11-23), which defines the voltage gain of a simple common emitter amplifier. A careful comparison of the two subject relationships suggests that the voltage gain of the common emitter-common base cascode of Fig. (11.13) is equivalent to the voltage gain achieved by a simple common emitter stage whose output port is loaded in an α α effective load resistance of RL. Although is close to unity, but nonetheless always less than one, α an effective load of RL implies that the voltage gain of the cascode is slightly less than that achieved by the common emitter stage alone, provided, of course, that the transistors utilized in both configurations have identical small signal parameters. A question therefore arises as to the prudence of incorporating common base signal processing in conjunction with a common emitter unit stage.
In fact, no practical purpose is served by a common emitter-common base cascode if the load resistance, RL, driven by the amplifier is very small. But if the load resistance imposed on the output port of a simple common emitter amplifier is large, as it is when the load itself is realized actively, as per Example (11.2.2-2), the effective transistor beta defined by (11-24) is appreciably smaller than the actual small signal beta. The result is a degraded common emitter amplifier voltage gain. In this situation, the insertion of a common base stage between the output port of the common emitter amplifier and RL, as diagrammed in Fig. (11.13), increases the degraded gain of the common emitter amplifier alone by restoring the effective beta of the common emitter transistor to a value that approximates the actual small signal beta of the transistor. This observation follows from the fact that the effective load resistance, RLeff, seen by the collector of the common emitter transistor in
Lecture Supplement #3 178 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. the cascode topology is of the order of only a small diode resistance. It follows from (11-24) that β β eff for RLT = RLeff is likely to be significantly larger than the value of eff that derives from the load condition, RLT = RL.
The reason for using common base circuit technology in conjunction with a common emitter amplifier is circuit broadbanding. In particular, a carefully designed common emitter- common
R
L
V c OS R out
Q2
R
Leff
G V
ns S
(a).
a i
r es r R out
ies e c
c V OS
r
R p
Leff
G nsV S R L
r b
(b).
FIGURE (11.15). (a) The Effective AC Schematic Diagram Of The Common Base Component Of The Common Emitter- Common Base Cascode Of Fig. (11.13). (b) Small Signal Model Of The AC Circuit In (a).
Lecture Supplement #3 179 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. base cascode configuration displays a 3-dB bandwidth and a gain-bandwidth product that are signifi- cantly larger than the bandwidth and gain-bandwidth product afforded by a common emitter stage of comparable gain. The primary reason underlying this laudable attribute is the low effective load resistance presented to the collector of the common emitter stage by the emitter of the common base structure. This low resistance attenuates the magnitude of the phase-inverted voltage gain of the common emitter circuit, thereby reducing the deleterious effects of Miller multiplication of the base- collector junction depletion capacitance implicit to the common emitter transistor[8].
COMMON COLLECTOR AMPLIFIER
While the common base configuration functions as a current buffer, the common col- lector amplifier, or emitter follower, whose AC schematic diagrams appear in Figs. (11.16a) and (11.16b), operates as a voltage buffer. It offers high input resistance, low output resistance, a voltage gain approaching unity, and a moderately large current gain. The small signal model of the emitter follower is the circuit in Fig. (11.16c).
Assuming infinitely large Early resistance, ro, a straightforward analysis of the subject model reveals an emitter follower voltage gain, Avcc, of V R OS LT A 5 5 (11-46) vcc V R 1 R 1 12 a R S LT d ST where Rd is the diode resistance given by (11-15). Observe that Avcc is a positive, less than unity, α number. The indicated gain approaches one for RLT >> Rd + (1 - )RST. Although the voltage gain is less than one, the corresponding current gain, which is simply the voltage gain scaled by a factor of (RST/RLT), can be substantially larger than one.
It is simple to confirm that the driving point input resistance, Rincc, and the driving point output resistance, Routcc, of the emitter follower are, respectively,
R 5 r 1 r 1 b 1 1 r 1 R 5 b 1 1 R 1 R (11-47) incc b p e LT d LT and
r 1 r 1 R p b ST R 5 r 1 5 R 1 1 2 a R (11-48) outcc e d ST b 1 1
It is interesting and instructive to note that the driving point input resistance, Rincc, of an emitter follower is of the same form as the driving point input resistance, Rince, of a common + emitter stage. Indeed, if RLT in the emitter follower is zero, Rincc Rince. This result is reasonable in view of the fact that for both the emitter follower and common emitter configurations, the input
Lecture Supplement #3 180 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. resistance is, as suggested by the test circuits in Figs. (11.17a) and (11.17b), the Thévenin resistance presented to the source circuit by the base of the subject transistor. Moreover, the common collector output resistance, Routcc, mirrors the driving point input resistance, Rincb, for the common base + amplifier. In fact, Rincb Routcc if the base of a common base amplifier is terminated to ground in a resistance of value RST. Once again, the latter observation is intuitively correct, for, as depicted in Figs. (11.17c) and (11.17d), the emitter of the transistor comprises the input terminal for the common base amplifier and the output terminal of an emitter follower.
An inspection of (11-46) confirms a common collector voltage gain that tends toward unity for progressively larger Thévenin load resistances, RLT. Correspondingly, the driving point input resistance of an emitter follower increases dramatically with increasing RLT. These observa- tions are often pragmatically exploited by supplanting the passive load in the schematic diagram of Fig. (11.16a) with an active load, as suggested in Fig. (11.18a). Since the effective AC load resis- tance must be large to achieve a near unity voltage gain, this active load must function as a sink of
Lecture Supplement #3 181 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
R R
incc incc
R R
outcc outcc
V V R OS R OS ST ST R R 1 LT 1 LT V V ST I ST I 2 OS 2 OS
(a). (b). R incc r r
b c c
i
r b i r p o R ST c 1 V r
ST e R
outcc
2 V OS
R LT
I OS
(c).
FIGURE (11.16). (a) AC Schematic Diagram Of An NPN Common Collector Amplifier. (b) AC Schematic Diagram Of A PNP Common Collector Amplifier. (c) Small Signal, Low Frequency Equivalent Circuit Of The Common Collector Ampli- fier, Assuming That The Early Resistance Is Sufficiently Large To Ignore.
Lecture Supplement #3 182 Fall Semester, 1998
EE 348 University of Southern California J. Choma, Jr.
R R
incc ince
R 1 1 LT V I R V I x x LT x x 2 2
(a). (b).
R
outcc
R R R ST 1 incb 1 LT I V I V x x x x 2 2
(c). (d).
FIGURE (11.17). (a) Test Circuit For Determining The Driving Point Input Resistance, Rincc, Of A Common Collector Amplifier. (b) Test Circuit For Determining The Driving Point Input Resistance, Rince, Of A Common Emitter Amplifier. Note That Rincc = Rince If RLT In The Common Collector Unit Is Zero. (c) Test Circuit For Determining The Driving Point Output Resistance, Routcc, Of A Common Collector Amplifier. (d) Test Circuit For Determining The Driving Point Input Resistance, Rincb, Of A Common Base Amplifier. Note That Routcc = Rincb If RST In The Common Collector Unit Is Zero. nominally constant current. To this end, the active load in question is shown conducting a net current that consists of a static current component, ICS, and a signal current component, IOS, where the constant current sink nature of the load implies ICS >> IOS.
Lecture Supplement #3 183 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
The subject active load can be represented by its Norton equivalent circuit, as dia- grammed in Fig. (11.18b), where ICS is depicted as a constant current source and IOS is made to flow through a resistance, Rcs. The latter branch element represents the dynamic resistance presented to the emitter follower output port by the two terminal active termination. Note that Rcs = ` yields IOS = 0, which implies an active load that behaves as an ideal constant current sink. The corresponding AC schematic diagram, which is offered in Fig. (11.18c), derives from Fig. (11.18b) by setting ICS to zero, since ICS itself is a constant current that is divorced of any signal component. Additionally, the biasing sources, VCC, VEE, and ESS, are presumed ideal and are therefore set to zero as well.
The AC schematic diagram in Fig. (11.18c) is identical to that in Fig. (11.16a), subject to the proviso that RLT = Rcs. But since Rcs is presumably a large resistance, substituting RLT = Rcs, into (11-46) to evaluate the voltage gain of the actively loaded emitter follower is at least theoretically inappropriate because the subject gain equation is premised on the assumption of a large Early resistance, ro; specifically, (11-46) reflects the assumption, RLT << ro. A voltage gain expression, more accurate than (11-46), derives from an analysis of the model in Fig. (11.16c). If ro is included in this analysis, but if re and rc are sufficiently small to justify their neglect, the result for RLT = Rcs is
V r R OS o| cs A 5 ' (11-49) vcc V S r R 1 R 1 12 a R o| cs d ST whose algebraic form collapses to (11-46) if Rcs << ro. Similarly, the revised expression for the driving point input resistance is
R ' r 1 r 1 b 1 1 r R (11-50) incc b p o| cs
The output resistance, Routcc, remains as stipulated by (11-48).
The active load appearing in Fig. (11.18a) can be realized as any one of a variety of NPN current sources[9]. Fig. (11.18d) offers an example of such a realization in the form of the Wilson current mirror formed of transistors Q2, Q3, and Q4, and the current setting resistor, R[10]. This subcircuit establishes an extremely high dynamic resistance between the collector of transistor Q2 and the β signal ground. In particular, if 2 and ro2 symbolize the AC beta and forward Early resistance, respectively of transistor Q2, it can be shown that
b r 2 o2 R ' (11-51) cs 2
Note further that the static current, ICS, conducted by the Wilson mirror flows through the emitter lead of the emitter follower transistor Q1. Thus, the biasing stability of Q1 is determined by the thermal sensitivity of the static current that flows in the Wilson subcircuit.
Lecture Supplement #3 184 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
V V
R 1 CC R 1 CC
incc incc
Q1R Q1 R
outcc outcc
c V c V R O R O ST ST I 1 I R I 1 I
1 CS OS cs 1 CS OS
V V c
ST ST I
2 2 OS
1 1 I R
Load
Load cs CS Active
E E Active SS SS c 2 2
(a). (b).
R R 1 V
incc incc CC
Q1 R Q1 R
outcc outcc
V c V R OS R R O ST ST cs I 1 I R CS OS 1 cs 1 V V Q2 c ST I ST 2 OS 2 1 c Q3 R E SS Q4 2 c
2 V (c). (d). EE
FIGURE (11.18). (a) Emitter Follower With Active Load That Conducts A Static Current, ICS, And A Signal Component, IOS. (b) The Norton Equivalent Circuit Of The Active Load. (c) AC Schematic Diagram Of The Actively Loaded Emitter Follower. (d) Wilson Current Mirror Realization Of The Active Load.
Lecture Supplement #3 185 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
EXAMPLE (11.2.2-3)
In order to dramatize the voltage buffering property of an emitter follower, return to the amplifier addressed analytically in Example (11.2.2-1) and drawn schematically in Fig. (11.7a). Let the two coupling capacitors remain large enough to approximate them as AC short circuits over the signal frequency range of interest, and let the small signal parameters Ω Ω Ω Ω Ω of the two transistors remain at rb = 90 , rc = 55 , re = 1.5 , rp = 970 , ro = 42 k , and β Ω Ω = 115. The circuit parameters also remain the same; namely, R1 = 2.2 k , R2 = 1.3 k , Ω Ω Ω Ω REE = 75 , RCC = 3.9 k , and RS = 300 . But instead of RL = 1.0 k , consider an Ω external load termination of RL = 300 . Reevaluate the small signal voltage gain, Av = VOS/VS, for the subject amplifier. Compare this result to the voltage gain achieved when an emitter follower is inserted between the collector of transistor Q1 and the 300 Ω load termination, as depicted in Fig. (11.19a). Assume that the small signal parameters of the emitter follower transistor, Q3, and those of the two transistors that comprise the diode- compensated current sink load of the follower are identical to the model parameters of transistors Q1 and Q2.
SOLUTION: (11.2.2-3)
(1). With reference to Fig. (11.7) and Example (11.2.2-1), the Thévenin load resistance, RLT, is now
R 5 R | R 5 278.6V LT CC L
The parameters, RST and KST in Fig. (11.7c) remain unchanged at the previously computed values of RST = 219.7 V and KST = 0.733. Then, ignoring the effects of the finite, but large, Early resistance, ro, the voltage gain is
V b K R A 5 OS ' 2 ST LT v V S R 1 r 1 r 1 b 1 1 r 1 R ST b p e EE
whence Av = -2.31 volts/volt.
(2). Consider now the amplifier modification shown in Fig. (11.19a). Transistor Q3 functions as an emitter follower to buffer the terminating load resistance, RL, effectively seen by the gain stage formed of transistor Q1 and its peripheral elements. Transistors Q3 and Q4 form a diode compensated current sink that comprises the active load presented to the emitter follower output port under static operational conditions. To the extent that ro can be tacitly ignored, this current sink comprises an infinitely large dynamic resistance. Accordingly, the AC schematic diagram seen to the right of the collector of transistor Q1 is the structure identified in Fig. (11.19b).
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(3). The source circuit that drives the base of transistor Q3 in Fig. (11.19b) is the Thévenin equivalent circuit established at the collector of transistor Q1 in Fig. (11.19a). The signal voltage associated with this source circuit is the open circuit voltage developed at the Q1 collector; that is, it is the voltage at the Q1 collector with the load formed of transistor Q3 and its peripheral elements removed. Since the circuit to the left of the base of transistor Q3 is a linear network,
Lecture Supplement #3 187 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
c c 1 V CC
R R R 1 CC in Q3 R
C c C out
i o
Q1 c c c V OS
Q2 Q4 c R R S L 1 Q5 c V S 2 R R R R R 2 EE 3 4 5 2 V c c c EE
(a).
Q3 R
out V R OS
CC
1
R A V L
v1 S 2
(b).
FIGURE (11.19). (a) The Amplifier Of Fig. (11.7), But With An Emitter Follower Buffer Inserted Between The Gain Stage And The Terminating Load Resistance. (b) AC Schematic Diagram Of The Amplifier In (a).
this Thévenin voltage is necessarily proportional to the input signal, VS. The indicated constant of proportionality in Fig. (11.19b), Av1, can rightfully be termed the open circuit voltage gain of the first stage of the subject amplifier. This is to say that Av1 is Av, as
Lecture Supplement #3 188 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
determined in Step (1) above, but with RL removed and therefore, RLT set equal to RCC. It follows that
b K R A 5 2 ST CC v1 R 1 r 1 r 1 b 1 1 r 1 R ST b p e EE
or Av1 = -32.38 volts/volt. Since ro is taken to be infinitely large, the resistance seen looking into the collector of transistor Q1 is likewise infinitely large. As a result, the Thevenin resis- tance associated with the source circuit in the AC diagram of Fig. (11.19b) is RCC = 3.9 kV.
(4). Recalling (11-46), the voltage gain of the circuit in Fig. (11.19b) is V R A 5 OS 5 L = 0.871 vol vcc A V R 1 R 1 12 a R v1 S L d CC
The resultant overall circuit gain is
V OS A 5 5 A A v V v1 vcc S
or Av = -28.21 volts/volt. Recalling the results of Step (1) of this computational procedure, the effect of the emitter follower is to boost the gain magnitude of the original configuration by a factor of about 12.2.
(5). From (11-48), the driving point output resistance of the buffered amplifier is
R 5 R 1 1 2 a R out d CC
Ω or Rout = 44.3 . Note that for the original non-buffered case, the output resistance is RCC = 3.9 kΩ.
DARLINGTON CONNECTION
In the Darlington connection whose basic schematic diagram is abstracted in Fig. (11.20a), the emitter of one transistor, Q1, is incident with the base of a second transistor, Q2, and the two transistor collector leads are connected together. The output signal is extracted as either the current flowing in the collector of transistor Q2 or the voltage developed at the emitter of Q2. In the former case, the indicated Darlington connection functions as a transconductance amplifier. In the latter case, an output signal voltage at the emitter of Q2 renders the connection functional as a voltage follower, or buffer. In both applications, the small signal driving point input resistance, Rind, seen looking into the base of transistor Q1 is large. On the other hand, the driving point output resistance, Routed, seen at the emitter is small and virtually independent of the source resistance, RS.
Lecture Supplement #3 189 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
The output resistance, Routcd, presented to the node at which the two transistor collectors are incident is large. At the expense of forward transconductance, Routcd can be enhanced by returning the collector of Q1 to the +VCC bus, instead of to the collector of transistor Q2. For a non-zero collector load resistance, RLC, this alternate connection, which is diagrammed in Fig. (11.20b), eliminates Miller multiplication of the base-collector junction capacitance of transistor Q1, thereby resulting in an improved transconductance frequency response.
Lecture Supplement #3 190 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
1 V c 1 V I CC I CC O O R R LC LC R R R outcd R outcd ind ind
c
Q1 Q1
Q2 R Q2 R
outed
R R outed
S S c V c V 1 O 1 O V V S R S R 2 LE 2 LE
2 V V EE 2 EE (a). (b).
1 V c 1 V I CC I CC O O R R LC LC R R R outcd R outcd ind ind
c
Q1 Q1
c Q2 R c Q2 R
outed outed
R R
S S c V c V 1 I O 1 I O V V S R S R 2 LE 2 LE c c
2 V V EE 2 EE (c). (d).
FIGURE (11.20). (a) The Basic Darlington Connection. (b) Alternative Darlington Connec- tion For Wideband Transconductance Response. (c) Darlington Connection
Lecture Supplement #3 191 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
With Input Transistor Current Compensation. (d) Alternative Darlington Connection With Input Transistor Current Compensation. R R ind r outcd b
c
i
1
r b i R R p 1 LC S 1 c I V OS S r e r 2 b c
i
2
R r b i is p 2
c
r R
e outed
V OS
R LE
FIGURE (11.21). The Small Signal Equivalent Circuit Of The Darlington Connection In Fig. (11.20c). The Early Resistance Is Ignored, And Both Transistors Are Pre- sumed To Have Identical Corresponding Small-Signal Parameters. The Resistance, Ris, Represents The Terminal Resistance Associated With The Appended Current Path Conducting Current I In Fig. (11.20c).
A fundamental problem that plagues both of the foregoing two Darlington connections is the fact that the static emitter current conducted by Q1 is identical to the static base current drawn by Q2. Accordingly, the emitter current of Q1 is likely to be much smaller than the biasing current commensurate with optimal gain-bandwidth product in this device. Moreover, this emitter current cannot be predicted accurately since it is inversely proportional to the Q2 static beta, whose numerical value is an unavoidable uncertainty. This poor biasing translates into an unreliable delineation of the static and small signal parameters for Q1. In turn, potentially significant uncertainties shroud the forward transfer and driving point resistance characteristics of the Darlington configuration.
Lecture Supplement #3 192 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
To remedy the situation at hand, an additional current path, usually directed to signal ground, is provided at the junction of the Q1 emitter and the Q2 base, as suggested in Figs. (11.20c) and (11.20d). The appended current path can be a simple two terminal resistance, although care must be exercised to ensure that this resistance is sufficiently large to avoid seriously compromising the large driving point input resistance afforded by the basic Darlington connection in either of the preceding two diagrams. Since large resistance and realistic biasing currents may prove to be conflicting design requirements, the appended current path is often an active current sink, such as the Wilson mirror load explored earlier in conjunction with the common collector amplifier. Note in the latter two diagrams that the current, indicated as I, conducted by the appended passive or active current path is essentially the emitter current of transistor Q1, provided that I is much larger than the base current of Q2.
The small signal bipolar junction transistor equivalent circuit of Fig. (11.1a) can be used to deduce the transfer and driving point resistance characteristics of any of the Darlington con- nections depicted in Fig. (11.20). An analysis is provided herewith for only the configuration in Fig. (11.20c), since this topology is the most commonly encountered Darlington circuit and the others are amenable to very straightforward analyses. To this end, the model for the subject structure is offered in Fig. (11.21), where it is assumed that both transistors are biased so that their corresponding small signal parameters are nominally identical. Moreover, the Early resistance of each transistor is presumed to be sufficiently large to warrant its neglect, and a resistance, Ris, is included to account for the terminal resistance of the appended current path discussed above. Letting
R is k D (11-52) is R 1 b 1 1 R 1 R is d LE denote the small signal current divider between the appended current path and the base circuit of transistor Q2, it can be shown that the driving point input resistance, Rind, is
R 5 b 1 1 R 1 b 1 1 k R 1 R ind d is d LE (11-53)
For large AC beta,
2 R ' b 1 1 k R 1 R (11-54) ind is d LE which is maximal for kis 1. From (11-52), the latter constraint mandates that the appended current path be designed so that its small signal terminal resistance satisfies the inequality, Ris >> (b+1)(Rd + RLE).
The voltage gain, Avd, from the signal source to the emitter port is 2 V b 1 1 k R OS is LE A 5 5 (11-55) vd V 2 S R 1 b 1 1 R 1 b 1 1 k R 1 R S d is d LE
Lecture Supplement #3 193 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
where VOS is the signal component of the net output voltage, VO. Equation (11-55) reduces to R LE A ' (11-56) vd R 1 R d LE for large AC beta. The corresponding driving point output resistance, Routed, is
R R d S R 5 R 1 1 ' R (11-57) outed d 2 d b 1 1 k is b 1 1 k is
At the collector port, the driving point output resistance, Routcd, is infinitely large to the extent that the Early resistance, ro, of both transistors can be ignored. For finite ro, this resistance is of the order of, and slightly larger than, (ro/2). Finally, the model in Fig. (11.21) yields a forward transconductance, Gfd, from the signal source to the collector port, of
I b 1 1 b 1 1 k OS is G 5 5 (11-58) fd V 2 S R 1 b 1 1 R 1 b 1 1 k R 1 R S d is d LE where IOS is the signal component of the net output current, IO. Equation (11-58) collapses to a G ' (11-59) fd R 1 R d LE for large AC beta.
11.2.2.4. DIFFERENTIAL AMPLIFIER
The differential amplifier is a four port network, as suggested in Fig. (11.22a). Source signals represented by the voltages, VS1 and VS2, which have Thévenin resistances of RS1 and RS2, respectively, are applied to the two amplifier input ports. The two output ports are termi- nated in three load resistances. Two of these loads, RL1 and RL2, are single ended terminations in that they provide a signal path to ground from each of the two output terminals. A third load resis- tance, RLL, is differentially connected between the two output terminals. In response to the two applied source signals, two single ended output voltages, VO1 and VO2, are generated across RL1 and RL2, and a differential output voltage, VDO, is established across RLL. This third output response is the difference between VO1 and VO2; that is,
Lecture Supplement #3 194 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
V 5 V 2 V . DO O1 O2 (11-60)
The salient features of a differential amplifier are unmasked by the concepts of differ- ential and common mode excitation and response. To this end, let the differential input source volt- age, VDI, be defined as
VDI D VS1 2 VS2 , (11-61) and let the common mode input voltage, VCI, be
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EE 348 University of Southern California J. Choma, Jr.
PORT #1 V PORT #3 O1
LINEAR R DIFFERENTIAL S1 R
V LL
AMPLIFIER O2 c
PORT #4 2 1 V PORT #2 DO R R R L2 L1 S2 1 1 V V S1 S2 2 2
(a).
PORT #1 V
PORT #3 O1
LINEAR R S1 DIFFERENTIAL R
AMPLIFIER V LL O2
c
PORT #4 1 2 V PORT #2 DO R R R L2 L1 S2 V 1 2 V DI DI 2 2 2 1 c 1 V CI 2 (b).
FIGURE (11.22). (a) System Level Diagram Of A Differential Amplifier. (b) System Level Diagram That Depicts The Electrical Implications Of The Common Mode And The Differential Mode Input Source Voltages.
V D 1 V 1 V . CI 2 S1 S2 (11-62)
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The differential input voltage is seen as the difference between the two applied source excitations. On the other hand, the common mode input voltage is the arithmetic average of the two source voltages.
When solved for VS1 and VS2, (11-61) and (11-62) give
V 5 V 1 1 V , S1 CI 2 DI (11-63a)
V 5 V 2 1 V . S2 CI 2 DI (11-63b)
The preceding two expressions allow the diagram of Fig. (11.22a) to be drawn in the form shown in Fig. (11.22b). This alternative representation underscores the fact that the Thévenin voltage applied to either input port is the superposition of a common mode source voltage and a component propor- tional to the differential source voltage. The common mode component raises both of the open circuit input terminals to a voltage that lies above ground by an amount, VCI. Superimposed with VCI at the open circuit terminals of Port #1 is a differential mode voltage, VDI/2. Simultaneously, a voltage of -VDI/2 superimposes with VCI at the open circuit terminals of Port #2.
The fact that two general source excitations applied to a four port system can be separated into a voltage component that appears only differentially across the two system input ports and a single ended common mode voltage component that is simultaneously incident with both of the system input ports makes it possible to achieve signal discrimination in a differential circuit. In particular, a differential amplifier can be designed so that it amplifies the differential component of two source signals while rejecting (in the sense of amplifying with near zero gain) their common mode component. Signal discrimination is useful whenever an electronic system must process low level electrical signals that are contaminated by spurious inputs, such as the voltage ramifications of electromagnetic interference or the biasing perturbations induced by temperature. If the two input ports of a differential amplifier are geometrically proximate and have matched driving point input impedances, these spurious excitations impact the two input ports identically. The undesired inputs are therefore common mode excitations that can be rejected by a differential amplifier that is well- designed in the sense of producing output port responses that are sensitive to only differential inputs.
If the differential amplifier in Fig. (11.22) is linear, superposition theory gives
V 5 A V 1 A V , O1 11 S1 12 S2 (11-64a)
VO2 5 A21 VS1 1 A22 VS2 , (11-64b) where the Aij are constants, independent of VS1 and VS2. When (11-63a) and (11-63b) are inserted into the last two relationships, the single ended output voltages are expressible as
V V 5 A 1 A V 1 A 2 A DI , O1 11 12 CI 11 12 2 (11-65a)
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V V 5 A 1 A V 2 A 2 A DI . O2 22 21 CI 22 21 2 (11-65b)
It follows that the differential output voltage is
V V 5 A 2 A 1 A 2 A V 1 A 1 A 2 A 2 A DI . DO 11 22 12 21 CI 11 22 12 21 2 (11- 66)
Since the common mode output voltage is
V D 1 V 1 V , CO 2 O1 O2 (11-67)
(11-65a) and (11-65b) yield
A 1 A 1 A 1 A A 2 A 2 A 1 A V V 5 11 22 12 21 V 1 11 22 12 21 DI . CO 2 CI 2 2 (11-68)
The ability of a differential amplifier to process differential excitations is measured by the differential mode voltage gain, AD. This performance index is defined as the ratio of the differential output voltage to the differential input voltage, under the condition of zero common mode input voltage. From (11-66),
V A 1 A 2 A 2 A DO 11 22 12 21 A D 5 (11-69) D V 2 DI V 5 0 | CI
On the other hand, the common mode voltage gain, AC, is a measure of the common mode signal rejection characteristics of a differential amplifier. It is the ratio of the common mode output voltage to the common mode input voltage, under the condition of zero differential input voltage Using (11-68),
V A 1 A 1 A 1 A CO 11 22 12 21 A D 5 (11-70) C V 2 CI V 50 | DI
A measure of the degree to which a differential amplifier rejects common mode excitation is the common mode rejection ratio, r, which is the ratio of the differential mode voltage gain to the common mode voltage gain. From (11-69) and (11-70),
A A 1 A 2 A 2 A D 11 22 12 21 r D 5 (11-71) A A 1 A 1 A 1 A C 11 22 12 21
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A common mode gain of zero indicates that no common mode output results from the application of common mode input signals. Therefore, a practical design goal is the realization of a differential amplifier that has the largest possible magnitude of common mode rejection ratio.
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BALANCED DIFFERENTIAL AMPLIFIER
Most differential amplifiers are balanced. Two operating requirements are satisfied by balanced differential systems. First, with zero common mode input voltage, the two single ended output voltages are mutually phase inverted, but otherwise identical. By (11-65a) and (11-65b), the balance requirement implies the parametric constraint,
A 2 A 5 A 2 A . 11 12 22 21 (11-72)
Second, equal single ended output voltages result when the differential mode input voltage is zero. Using (11-65a) and (11-65b) once again, this stipulation requires
A 1 A 5 A 1 A . 11 12 22 21 (11-73)
Equations (11-72) and (11-73) combine to deliver the balanced operating requirement,
A 5 A 11 22 . A 5 A % 12 21 (11-74)
From (11-69) through (11-71), the differential mode voltage gain, the common mode voltage gain, and the common mode rejection ratio of a balanced differential amplifier are
A 5 A 2 A , D 11 12 (11-75)
A 5 A 1 A , C 11 12 (11-76)
A 2 A r 5 11 12 . A 1 A 11 12 (11-77)
Moreover, the single ended output voltages in (11-65a) and (11-65b) become
V A 2 V V 5 A V 1 A DI 5 D 1 1 CI V , O1 C CI D 2 2 V DI r DI (11-78a)
V A 2 V V 5 A V 2 A DI 5 2 D 1 2 CI V , O2 C CI D 2 2 r V DI DI (11-78b) which give rise to a differential response of
V 5 V 2 V 5 A V . DO O1 O2 D DI (11-79)
Equations (11-78a) and (11-78b) show that a balanced differential amplifier having a very large common mode rejection ratio produces single ended outputs that are nominally phase inverted
Lecture Supplement #3 200 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. versions of one another and approximately independent of the common mode input voltage. On the other hand,
Lecture Supplement #3 201 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
i PORT #3
i V
i1 01 O1 Amplifier PORT #1 #1 R S
i 1 1 V IDENTICAL S1 k c AMPLIFIERS 2 i R 2 K
i i R
i2 V LL 02 O2 Amplifier c PORT #2 #2 2 1 PORT #4 V R R DO R S L L 1 V S2 2
FIGURE (11.23). Generalized System Diagram Of A Balanced Differential System. The Topology Is An AC Schematic Diagram In That Requisite Biasing Subcircuits Of Either Amplifier Are Not Shown.
Lecture Supplement #3 202 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
PORT #3
i i
i1 PORT #1 01 V
Amplifier DO c c #1 2
R i S 1 R R LL k c L 2
V 1 c DI 2 2
(a).
i PORT #3 i
i1 01 PORT #1 Amplifier c V #1 CO
R i S 1 R k c L
1 2R V K CI 2
(b).
FIGURE (11.24). (a) Differential Mode Half Circuit Equivalent Of The Balanced Differential Amplifier. (b) Common Mode Half Circuit Equivalent Of The Balanced Differential Amplifier. the differential output voltage of a balanced system is independent of the common mode input signal, regardless of the value of the common mode rejection ratio.
Fig. (11.23) depicts the most straightforward way to implement balance in a differen- tial configuration. In this abstraction, two identical single ended amplifiers, such as those discussed in earlier subsections, are interconnected to establish signal flow paths between single ended input and single ended output ports. This topology boasts integrated circuit practicality, since it exploits the inherent ability of a mature monolithic fabrication process to produce well-matched equivalent components. The two single ended amplifiers in the subject figure are topologically identical, and they incorporate matched active devices that are biased at the same quiescent operating points. Thus, Amplifiers #1 and #2 have small signal, two port equivalent circuits that are mirror images of
Lecture Supplement #3 203 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. one another. In order to ensure balanced operation, the single ended output ports of each amplifier are terminated to ground in equal load resistances, RL. Similarly, the Thévenin source resistances are equivalent. Observe that balance implies that the upper half of the circuit in Fig. (11.23) is a mirror image of the lower half of the system schematic diagram. This interpretation begets the common reference to a balanced differential amplifier as a differential pair.
The balance condition entails the following engineering constraints.
(1). Under the case of differential mode excitation, which implies VS1 = -VS2 = VDI/2 and hence, VCI = 0, the currents indicated in Fig. (11.23) are such that ii1 = -ii2, io1 = -io2, and i1 = -i2. Since the resistance, RK, conducts a current equal to the sum of i1 and i2, i1 = -i2 clamps node k to signal ground potential for exclusively differential mode inputs. Moreover, (11-78a) and (11-78b) confirm VO1 = -VO2 = ADVDI/2, which produces a signal current through the differential load resistance, RLL, of V 2 V V O1 O2 5 O1 . R LL RLL / 2
Since the single ended response voltage, VO1, is referred to signal ground, the mid- point of the differential load resistance is effectively grounded for differential inputs.
The foregoing disclosures imply the circuit diagram of Fig. (11.24a), which is the so- called differential mode half circuit equivalent[11]-[12] of the differential amplifier. For a balanced differential pair driven by exclusively differential inputs, the branch currents, branch voltages, and node voltages computed from an analysis of the structure in Fig. (11.24a) are precisely the negative of the corresponding circuit variables in the remaining half of the system.
(2). Under the case of common mode inputs, which implies VS1 = VS2 = VCI and hence, VDI = 0, the currents delineated in Fig. (11.23) satisfy the constraints, ii1 = ii2, io1 = io2, and i1 = i2. Since the resistance, RK, conducts a current equal to the sum of i1 and i2, i1 = i2 establishes a voltage at node k of
R i 1 i 5 2 R i ; K 1 2 K 1 that is, the signal voltage developed at node k corresponds to an Amplifier #1 current of i1 flowing through a resistance whose value is twice RK. Additionally, VO1 = VO2 = VCO, which means that no signal current flows through RLL under exclusively common mode excitation.
It follows that the common mode half circuit equivalent of the differential amplifier, is as drawn in Fig. (11.24b). For a balanced differential pair driven by exclusively common mode input signals, the branch currents, branch voltages, and nodal voltages computed for the structure in Fig. (11.24b) are identical to the corresponding circuit variables in the other half of the circuit.
Lecture Supplement #3 204 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
THEVENIN EQUIVALENT I/O CIRCUITS
Because the two input ports of a differential amplifier electrically interact with one another, the Thévenin equivalent circuit seen by the two signal sources in Fig. (11.22a) is itself a two
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PORT #1 PORT #3
LINEAR, BALANCED R
I DIFFERENTIAL LL
t1
AMPLIFIER c
PORT #4 PORT #2 I t2 R R L L
1 1 V V t1 t2 2 2 (a).
R
XI
PORT #1 PORT #2
cc I V V I t1 t1 t2 t2 R XX R XX 1 1 R R V XX XX V t1 t2 2 2
(b).
FIGURE (11.25). (a) Test Circuit Used To Evaluate The Thévenin Input Equivalent Circuit Of A Balanced Differential Amplifier. Note The Connection Of Balanced Loads At Ports #3 and #4. (b) Hypothesized Thévenin Equivalent Input Circuit. port network. The branch elements of this Thévenin model are defined in terms of a differential mode input resistance, RDI, and a common mode input resistance, RCI.
Consider the test circuit of Fig. (11.25a), which is configured to formulate the Thévenin equivalent input circuit. This structure is analogous to that of Fig. (11.22a), except that the linear differential unit is presumed balanced. Furthermore, the original source circuits are supplanted by the test voltages, Vt1 and Vt2, which establish the input port currents, It1 and It2. Because no signals other than Vt1 and Vt2 are applied to the differential pair, the Thévenin equivalent circuit seen between Ports #1 and #2 is a resistance, say RXI. Similarly, a second resistance, RXX, is introduced to terminate Port #1 to ground. System balance implies that a
Lecture Supplement #3 206 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr. resistance of the same value terminates the second input port. The hypothesized Thévenin equivalent input circuit is given in Fig. (11.25b).
The application of Kirchhoff's Current and Voltage Laws to the model in Fig. (11.25b) produces
V V I 2 t1 5 t2 2 I , t1 R R t2 XX XX (11-80a)
V V 2 V 5 R I 2 t1 . t1 t2 XI t1 R XX (11-80b)
If the test voltages, Vt1 and Vt2, are decomposed into their differential (VDt) and common mode (VCt) components in accordance with V V I 2 t1 5 t2 2 I t1 R R t2 (11-81a) XX XX V D t V 5 V 2 (11-81b) t2 C t 2
(11-80a) and (11-80b) lead to
V V I 5 C t 1 D t , t1 R R 2 R XX XI| XX (11-82a)
V V I 5 C t 2 D t . t2 R R 2 R XX XI| XX (11-82b)
Equations (11-82a) and (11-82b) implicitly define the common mode and differential mode compo- nents of the currents, It1 and It2, resulting from the test voltages, Vt1 and Vt2. Accordingly, the common mode driving point input resistance, RCI, is
RCI 5 RXX . (11-83)
On the other hand, the differential mode driving point input resistance, RDI, is
R 5 R 2 R , DI XI| CI (11-84) where use has been made of (11-82a), (11-82b), and (11-83). Note that the model resistance, RXI, is related to the differential input resistance, RDI, of the amplifier by
Lecture Supplement #3 207 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
2 R R R 5 CI DI . XI 2 R 2 R CI DI (11-85)
The test circuits for measuring the common mode and the differential mode driving point input resistances derive directly from (11-82a) and (11-82b). For a differential input test volt-
age, VDt, of zero, Vt1 and Vt2 are identical to the common mode input test voltage, VCt, whence
PORT #1 PORT #3
R LINEAR, CI BALANCED R
I DIFFERENTIAL LL
t1 R CI AMPLIFIER c
PORT #4 PORT #2
R R I
t1 L L
V
t1 5 R
CI 1 1 I t1 V V t1 t1 2 2
(a).
PORT #1 PORT #3
LINEAR, I t1 BALANCED
R
DIFFERENTIAL LL R
DI $ AMPLIFIER c PORT #4
PORT #2
I R R
t1 L L
V R 1 2 t1 DI
5 V V I 2 t1 t1 t1 2 1
(b).
FIGURE (11.26). (a) Test Circuit Used To Evaluate The Driving Point Common Mode Input Resistance Of A Linear, Balanced Differential Pair. (b) Test Circuit Used To Evaluate The Driving Point Differential Mode Input Resistance Of A Linear, Balanced Differential Pair.
Lecture Supplement #3 208 Fall Semester, 1998 EE 348 University of Southern California J. Choma, Jr.
V V I 5 t1 5 t1 [ I . t1 R R t2 XX CI (11-86)
It follows that the circuit of Fig. (11.26a) is appropriate to the measurement (or calculation) of RCI as the Ohm's Law ratio of the common mode test voltage to the resultant common mode test current. Observe that half circuit analysis measures apply, wherein RCI is the resistance seen looking into Port #1, with Port #3 terminated to ground in the resistance, RL. For differential testing, Vt1 = -Vt2 = VDt/2, whence 2 V 2 V I 5 t1 5 t1 5 2I . t1 t2 R 2 R R XI| CI DI (11-87)
The pertinent test cell is shown in Fig. (11.26b). For half circuit analysis, care should be exercised to recognize that the ratio of the test voltage, Vt1, to the corresponding test current, It1, is one-half of the driving point differential input resistance, RDI. In addition, the subcircuit connecting Port #2 to Port #4 must be removed, and Port #3 must be terminated to ground by the shunt interconnection of the resistances, RL and RLL/2.
Just as a Thévenin model can be constructed for the input ports of a balanced differential pair, a Thévenin equivalent circuit can be developed for the output ports. Under zero input conditions, this output model, which is presented in Fig. (11.27), is topologically identical to the equivalent circuit in Fig. (11.25b). In a fashion that reflects the computation of the resistance parameters for the input equivalent circuit, Fig. (11.28a) is the test circuit for evaluating the driving point common mode output resistance, RCO. Fig. (11.28b) is the test structure for calculating the driving point differential mode output resistance, RDO. Following (11-85), RXO in Fig. (11.27) is given by
R
XO
PORT #3 PORT #4 cc
R R CO CO
FIGURE (11.27). Thévenin Equivalent Output Circuit Of The Balanced Differential Amplifier For The Case Of Zero Input Signal Excitation.
2 R R R 5 CO DO . XO 2 R 2 R CO DO (11-88)
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There are two electrically interactive output ports in the differential system of Fig. (11.22a). Thus, two Thévenin voltages, Vth1 and Vth2, each of which is linearly dependent on the differential mode and the common mode components of the applied source signals must be evaluated. These Thévenin output responses derive from open circuited load conditions, as indicated in Fig. (11.29a). With RS1 = RS2 RS, balance prevails, and Vth1 and Vth2 are characterized by differential and common mode components, analogous to the characterization of the terminated outputs, VO1 and VO2.
The Thévenin voltages in question derive from an analysis of the equivalent circuit in Fig. (11.29b), which represents the model of Fig. (11.27) modified to account for non-zero source
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PORT #1
PORT #3 LINEAR, R BALANCED CO I
DIFFERENTIAL t1
R
CO AMPLIFIER
PORT #4 PORT #2 I
t1
1 1
R R V
S S t1 5 R V V
I CO t1 t1 t1 2 2
(a).
PORT #1 PORT #3
LINEAR, BALANCED R I
DIFFERENTIAL DO t1
%
AMPLIFIER PORT #4
PORT #2 I
t1
2 1
R R V R
S S t1 5 DO V V
I 2 t1 t1 t1 1 2
(b).
FIGURE (11.28). (a) Test Circuit Used To Evaluate The Driving Point Common Mode Output Resistance Of A Linear, Balanced Differential Pair. (b) Test Circuit Used To Evaluate The Driving Point Differential Mode Output Resistance Of A Linear, Balanced Differential Pair. excitation. The proportionality constants, kc and kd, are related to the previously determined common mode and differential mode voltage gains. It is a simple matter to confirm that
k R V V , V 5 k V 6 d XO DI . th1 th2 c CI 2RCO 1 RXO 2 (11-89)
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The first term on the right hand side of this relationship is the open circuit common mode output voltage, while the second term is the open circuit differential mode output voltage. It follows that kc represents the open circuit common mode voltage gain, ACO; that is, k 5 lim A D A . c R ➛ ` C CO L R ➛ ` LL (11-90)
On the other hand, the open circuit differential mode gain, ADO, is k R d XO 5 lim A D A . 2 R 1 R R ➛ ` D DO CO XO L R ➛ ` LL (11-91)
Using (35), the Thévenin model parameter, kd in the last expression can be cast as,
2 R k 5 CO A . d R DO DO (11-92)
Fig. (11.30) summarizes the foregoing modeling results[13].
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PORT #1 PORT #3 V LINEAR th1
R DIFFERENTIAL
S
AMPLIFIER
V
PORT #4 th2 PORT #2
R S 1 1 V V S1 S2 2 2 (a).
R
XO
PORT #3 PORT #4 V ccV th1 I th2 R R CO CO 1 2 k V k V d DI d DI 2 2 2 1 c 1 k V c CI 2
(b).
FIGURE (11.29). (a) System Schematic Diagram Used To Define The Thévenin Voltages At The Output Ports Of A Balanced Differential Amplifier. (b) Thévenin Equivalent Circuit For The Output Ports Of A Balanced Differential Pair.
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PORT #1 PORT #3 LINEAR V 01 R DIFFERENTIAL S R
V LL
AMPLIFIER 02
c
PORT #4 PORT #2 R R L L R S 1 1 V V S1 S2 2 2 (a).
2R R 2R R CI DI CO DO
2R 2 R 2R 2 R
CI DI CO DO
c c c c PORT #1 PORT #2 PORT #3 PORT #4
R R R R CI CI CO CO
R A 1 2 R A CO DO V CO DO V R DI R DI DO 2 1 DO c 1 A V CO CI 2
(b). (c).
FIGURE (11.30). (a) System Schematic Diagram Of A Linear, Balanced Differential Amplifier. (b) Thévenin Equivalent Input Circuit. (c) Thévenin Equivalent Output Circuit. The Parameters, ADO And ACO Represent The Open Circuit Values Of The Differential And Common Mode Voltage Gains, Respectively, Of The Balanced Pair In (a).
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EXAMPLE (11.2.2-4)
Consider the balanced circuit of Fig. (11.31), which is operated as a single ended input, single ended output amplifier. The input voltage signal, which is capacitively coupled to the base of transistor Q1, is represented as a Thévenin equivalent circuit consisting of the source voltage, VS, in series with a source resistance, RS. In order to preserve electrical balance, the base of transistor Q2 is capacitively returned to ground through a resistance whose value is also equal to RS. The capacitors can be presumed to act as AC short circuits over the signal frequency range of interest. For the parameters delineated in the inset to Fig. (11.31), a computer-aided circuit simulation of the subject amplifier indicates that both transistors have the small signal Ω Ω β parameters, rb = 33.5 , rπ = 1.22 k , and = 81.1. Determine the small signal voltage gain, Av = VOS/VS, driving point input resistance, Rin, and driving point output resistance, Rout.
SOLUTION: (11.2.2-4)
(1). The AC schematic diagram of the differential mode half circuit of the balanced amplifier in Fig. (11.31) is shown in Fig. (11.32a). In concert with earlier arguments, note that the junction of the two emitter degeneration resistances, REE, is grounded, as are the mid-point of the resistance, RLL, and the node at which R1, R2, and the two resistances labeled R are incident. Using the bipolar model of Fig. (11.1a), with ro and re ignored, the voltage gain of this structure is the differential mode voltage gain of the differential pair. Moreover, the driving point input resistance of the circuit at hand is one half of the differential input resistance of the original pair, while its driving point output resistance is one half of the differential mode output resistance. Analysis confirms
R R b R | LL L V /2 R 1 R 2 A 5 DO 5 2 S D V /2 R | R 1 r 1 r 1 b 1 1 R DI S b p EE
R DI 5 R| r 1 r 1 b 1 1 R 2 b p EE
R R DO 5 R | LL . 2 L 2 Ω Ω Numerically, AD = -10.09, RDI = 5,971 Ω, and RDO = 1,875 Ω.
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(2). The AC schematic diagram of the pertinent common mode half circuit is given in Fig. (11.32b). The input signal voltage is now the common mode input voltage, VCI, which produces the common mode output response, VCO. Using the bipolar model of Fig. (11.1a), with ro and re ignored, it is easily shown that
R 1 2 R1 | R2 b RL VCO R 1 2 R1 | R2 1 RS A 5 5 2 C V CI RS | R 1 2 R1 | R2 1 rb 1 rp 1 b 1 1 REE 1 2RK
R 5 R 1 2 R | R r 1 r 1 b 1 1 R 1 2R CI 1 2 | b p EE K
R 5 R . CO L
-3 Ω Ω Numerically, AC = -923.3 (10 ), RCI = 5,493 Ω, and RCO = 1,500 Ω. The common mode ρ rejection ratio, ρ = AD/AC = 10.93, is small owing to the relatively small value of the resistance, RK.
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V c 1 CC
R R L L R R
LL out
R in V c c O
CC ccQ1 R R Q2 EE EE c R R R R S S cc 1 V R R R S 2 K 1 2 c
V
2 EE
R 5 450V R 5 2000V R 5 750V
1 2 K
R 5 50V R 5 75V R 5 1500V
S EE L
R R 5 1.5m f 5 5000V 5 5000V C
LL
V 5 5 volts V 5 5 volts
CC EE
FIGURE (11.31). A Balanced Bipolar Differential Amplifier Used In A Single Ended Input, Single Ended Output Mode.
(3). Since the output voltage is extracted at the collector of transistor Q2, (11-78b) is the applicable equation for determining the output signal voltage, VOS. With only a single source voltage, VS, applied, the differential input voltage is VS, and the common mode input voltage is VS/2. It follows that A A 2 A V 5 A V 2 D V 5 C D V OS C CI 2 DI 2 S
whence a voltage gain of
VOS AC 2 AD A 5 5 v V 2 S
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These analyses give Av = 4.583.
(4). In order to evaluate the driving point input and output resistances, the parameters, RXI and Ω Ω RXO must be calculated. From (11-85) and (11-88), RXI = 13.08 k , and RXO = 5.0 .
The two port model for calculating the driving point input resistance, Rin, is given in Fig. (11.30b). Recall that a circuit resistance, whose value is numerically equal to the internal signal source resistance, RS, is connected between ground and the node to which the base of transistor Q2 is incident. By inspection,
R 5 R R 1 R R in CI | XI CI | S
Ω or Rin = 3.87 kΩ.
The output port model that emulates the driving point output resistance is given in Fig. (11.30c). This model is analogous to that of Fig. (11.30a), except that no external loads are connected between signal ground and the node to which the collector of transistor Q1 is inci- dent. Clearly,
R 5 R R 1 R out CO | XO CO
Ω which produces Rout = 1,219 Ω.
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R /2
R /2 DO
DI
c V /2
DO
c Q1 R R | LL R L 2 S R R EE V 1 DI c 2 2
(a).
c V
R CO
CI c Q1 R CO R R L S R R EE 1 V 2(R |R ) CI 1 2 2 2R K c
(b).
FIGURE (11.32). (a) Differential Mode Half Circuit AC Equivalent Schematic Of The Differential Amplifier Shown In Fig. (11.31). (b) Common Mode Half Circuit AC Equivalent Schematic Of The Differential Amplifier Shown In Fig. (11.31).
11.2.2.5. REFERENCES
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[1]. J. J. Ebers and J. L. Moll, "Large-Signal Behavior of Junction Transistors," Proc. IRE, vol. 42, pp. 1761-1772, Dec. 1954. [2]. H. K. Gummel and H. C. Poon, "An Integral Charge-Control Model of Bipolar Transistors," Bell System Tech. Journal, vol. 49, pp. 115-120, May-June 1970. [3]. H. N. Ghosh, "A Distributed Model of the Junction Transistor and its Application in the Prediction of the Emit- ter-Base Diode Characteristic, Base Impedance, and Pulse Response of the Device," IEEE Trans. Electron Devices, vol. ED-12, pp. 513-531, Oct. 1965. [4]. J. R. Hauser, "The Effects of Distributed Base Potential on Emitter Current Injection Density and Effective Base Resistance for Stripe Transistor Geometries," IEEE Trans. Electron Devices, vol. ED-11, pp. 238-242, May 1965. [5]. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: John Wiley and Sons, 1977, pp. 16-19. [6]. C. T. Kirk, "A Theory of Transistor Cut-Off Frequency (fT) at High Current Densities," IEEE Trans. Electron Devices, vol. ED-9, pp. 164-174, March 1962. [7]. J. M. Early, "Effects of Space-Charge Layer Widening in Junction Transistors," Proc. IRE, vol. 46, pp. 1141- 1152, Nov. 1952. [8]. A. S. Sedra and K. C. Smith, Microelectronic Circuits. New York: Holt, Rinehart and Winston, 1987, pp. 52-57 and 639-642. [9]. A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design. New York: Wiley-Interscience, 1984, pp. 170-182. [10]. G. R. Wilson, "A Monolithic Junction FET-NPN Operational Amplifier," IEEE J. Solid-State Circuits, vol. SC- 3, pp. 341-348, Dec. 1968. [11]. E. J. Angelo, Electronic Circuits. New York: McGraw-Hill Book Company, 1970, chap 4. [12]. A. B. Grebene, op. cit., pp. 217-224. [13]. S. A. Witherspoon and J. Choma, Jr., "The Analysis of Balanced Linear Differential Circuits," acc. to IEEE Trans. on Education for publication in Dec. 1994.
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