Two-Port Networks and Amplifiers
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Cascode Amplifiers by Dennis L. Feucht Two-Transistor Combinations
Cascode Amplifiers by Dennis L. Feucht Two-transistor combinations, such as the Darlington configuration, provide advantages over single-transistor amplifier stages. Another two-transistor combination in the analog designer's circuit library combines a common-emitter (CE) input configuration with a common-base (CB) output. This article presents the design equations for the basic cascode amplifier and then offers other useful variations. (FETs instead of BJTs can also be used to form cascode amplifiers.) Together, the two transistors overcome some of the performance limitations of either the CE or CB configurations. Basic Cascode Stage The basic cascode amplifier consists of an input common-emitter (CE) configuration driving an output common-base (CB), as shown above. The voltage gain is, by the transresistance method, the ratio of the resistance across which the output voltage is developed by the common input-output loop current over the resistance across which the input voltage generates that current, modified by the α current losses in the transistors: v R A = out = −α ⋅α ⋅ L v 1 2 β + + + vin RB /( 1 1) re1 RE where re1 is Q1 dynamic emitter resistance. This gain is identical for a CE amplifier except for the additional α2 loss of Q2. The advantage of the cascode is that when the output resistance, ro, of Q2 is included, the CB incremental output resistance is higher than for the CE. For a bipolar junction transistor (BJT), this may be insignificant at low frequencies. The CB isolates the collector-base capacitance, Cbc (or Cµ of the hybrid-π BJT model), from the input by returning it to a dynamic ground at VB. -
Scattering Parameters
Scattering Parameters Motivation § Difficult to implement open and short circuit conditions in high frequencies measurements due to parasitic L’s and C’s § Potential stability problems for active devices when measured in non-operating conditions § Difficult to measure V and I at microwave frequencies § Direct measurement of amplitudes/ power and phases of incident and reflected traveling waves 1 Prof. Andreas Weisshaar ― ECE580 Network Theory - Guest Lecture ― Fall Term 2011 Scattering Parameters Motivation § Difficult to implement open and short circuit conditions in high frequencies measurements due to parasitic L’s and C’s § Potential stability problems for active devices when measured in non-operating conditions § Difficult to measure V and I at microwave frequencies § Direct measurement of amplitudes/ power and phases of incident and reflected traveling waves 2 Prof. Andreas Weisshaar ― ECE580 Network Theory - Guest Lecture ― Fall Term 2011 1 General Network Formulation V + I + 1 1 Z Port Voltages and Currents 0,1 I − − + − + − 1 V I V = V +V I = I + I 1 1 k k k k k k V1 port 1 + + V2 I2 I2 V2 Z + N-port 0,2 – port 2 Network − − V2 I2 + VN – I Characteristic (Port) Impedances port N N + − + + VN I N Vk Vk Z0,k = = − + − Z0,N Ik Ik − − VN I N Note: all current components are defined positive with direction into the positive terminal at each port 3 Prof. Andreas Weisshaar ― ECE580 Network Theory - Guest Lecture ― Fall Term 2011 Impedance Matrix I1 ⎡V1 ⎤ ⎡ Z11 Z12 Z1N ⎤ ⎡ I1 ⎤ + V1 Port 1 ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ - V2 Z21 Z22 Z2N I2 ⎢ ⎥ = ⎢ ⎥ ⎢ ⎥ I2 + ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ V2 Port 2 ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ - V Z Z Z I N-port ⎣ N ⎦ ⎣ N1 N 2 NN ⎦ ⎣ N ⎦ Network I N [V]= [Z][I] V + Port N N + - V Port i i,oc- Open-Circuit Impedance Parameters Port j Ij N-port Vi,oc Zij = Network I j Port N Ik =0 for k≠ j 4 Prof. -
Cascode Techniques
Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode Techniques Michael H. Perrott February 15, 2012 Copyright © 2012 by Michael H. Perrott All rights reserved. M.H. Perrott Review of Large Signal Analysis of Current Mirrors Vdd Δ V2 I I 1 2 1 μ W2 2 λ nCox (VGS2-VTH) (1+ 2Vds2) I2 2 L = 2 I 1 W 2 1 μ C 1(V -V ) (1+λ V ) 2 n ox GS1 TH 1 ds1 M L1 2 ΔV M1 Vds2 > Vdsat2 1 V +ΔV V +ΔV Δ Δ Δ Δ Vss=0 TH 1 TH 2 But, VTH+ V1=VTH+ V2 V1 = V2 λ I2 W2 L1 (1+ 2Vds2) I2 = λ I1 W1 L2 (1+ 1Vds1) M2 in Saturation Current Mismatch setting due to Vds based on difference M2 in Triode geometry Note: for accurate ratio, set L1 = L2 Vds2 Vdsat2 M.H. Perrott 2 The Issue of Vds Mismatch in Current Mirrors V λ dd I2 W2 (1+ 2Vds2) = λ I1 W1 (1+ 1Vds1) I1 I2 Current Mismatch setting due to Vds based on difference geometry V V ds1 ds2 Note: we are assuming L = L M1 M2 1 2 . Issue: Current I2 can vary significantly as a function of the drain voltage of M2 - We often want a tightly controlled current set only by I1 and transistor sizes . How do we improve the current mirror matching performance? M.H. Perrott 3 Cascoded Current Source I Rth R ref d3 thd3 Ibias Vbias V M bias 3 M3 M ro1 2 M1 . Offers increased output resistance - Reduces small signal dependence of output current on the output voltage of the current source - From Lecture 6, we derived: . -
Brief Study of Two Port Network and Its Parameters
© 2014 IJIRT | Volume 1 Issue 6 | ISSN : 2349-6002 Brief study of two port network and its parameters Rishabh Verma, Satya Prakash, Sneha Nivedita Abstract- this paper proposes the study of the various ports (of a two port network. in this case) types of parameters of two port network and different respectively. type of interconnections of two port networks. This The Z-parameter matrix for the two-port network is paper explains the parameters that are Z-, Y-, T-, T’-, probably the most common. In this case the h- and g-parameters and different types of relationship between the port currents, port voltages interconnections of two port networks. We will also discuss about their applications. and the Z-parameter matrix is given by: Index Terms- two port network, parameters, interconnections. where I. INTRODUCTION A two-port network (a kind of four-terminal network or quadripole) is an electrical network (circuit) or device with two pairs of terminals to connect to external circuits. Two For the general case of an N-port network, terminals constitute a port if the currents applied to them satisfy the essential requirement known as the port condition: the electric current entering one terminal must equal the current emerging from the The input impedance of a two-port network is given other terminal on the same port. The ports constitute by: interfaces where the network connects to other networks, the points where signals are applied or outputs are taken. In a two-port network, often port 1 where ZL is the impedance of the load connected to is considered the input port and port 2 is considered port two. -
CHAPTER 3 Frequency Response of Basic BJT and MOSFET Amplifiers (Review Materials in Appendices III and V)
CHAPTER 3 Frequency Response of Basic BJT and MOSFET Amplifiers (Review materials in Appendices III and V) In this chapter you will learn about the general form of the frequency domain transfer function of an amplifier. You will learn to analyze the amplifier equivalent circuit and determine the critical frequencies that limit the response at low and high frequencies. You will learn some special techniques to determine these frequencies. BJT and MOSFET amplifiers will be considered. You will also learn the concepts that are pursued to design a wide band width amplifier. Following topics will be considered. Review of Bode plot technique. Ways to write the transfer (i.e., gain) functions to show frequency dependence. Band-width limiting at low frequencies (i.e., DC to fL). Determination of lower band cut-off frequency for a single-stage amplifier – short circuit time constant technique. Band-width limiting at high frequencies for a single-stage amplifier. Determination of upper band cut-off frequency- several alternative techniques. Frequency response of a single device (BJT, MOSFET). Concepts related to wide-band amplifier design – BJT and MOSFET examples. 3.1 A short review on Bode plot technique Example: Produce the Bode plots for the magnitude and phase of the transfer function 10s Ts() , for frequencies between 1 rad/sec to 106 rad/sec. (1ss / 1025 )(1 / 10 ) We first observe that the function has zeros and poles in the numerical sequence 0 (zero), 2 5 2 10 (pole), and 10 (pole). Further at ω=1 rad/sec i.e., lot less than the first pole (at ω=10 rad/sec), Ts() 10 s. -
Optimal High Performance Self Cascode CMOS Current Mirror
View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Global Journal of Computer Science and Technology (GJCST) Global Journal of Computer Science and Technology Volume 11 Issue 15 Version 1.0 September 2011 Type: Double Blind Peer Reviewed International Research Journal Publisher: Global Journals Inc. (USA) Online ISSN: 0975-4172 & Print ISSN: 0975-4350 Optimal High Performance Self Cascode CMOS Current Mirror By Vivek Pant, Shweta Khurana Kurukshetra University Kurukshetra Abstract - In this paper the current mirror presented, having low voltage and mixed mode structure has been proposed. The performance of self cascade MOSFET current mirror is optimized with high output impedance and can operate at 1 V or below. Simulation results conform to Analog Mentor tools having Design Architect for schematics and Eldonet for SPICE simulation, with input reference current of 20μA. This review paper presents a comparative performance study of self cascode current mirror with other current mirrors. Keywords : current mirrors, cascode current mirror, low voltage analog circuit. GJCST Classification : I.2.9 Optimal High Performance Self Cascode CMOS Current Mirror Strictly as per the compliance and regulations of: © 2011. Vivek Pant, Shweta Khurana.This is a research/review paper, distributed under the terms of the Creative Commons Attribution-Noncommercial 3.0 Unported License http://creativecommons.org/licenses/by-nc/3.0/), permitting all non commercial use, distribution, and reproduction in any medium, provided the original work is properly cited. Optimal High Performance Self Cascode CMOS Current Mirror Vivek Pantα, Shweta KhuranaΩ Abstract - In this paper the current mirror presented, having I = I (W/L) 2 (1+λVds2) (3) out ref low voltage and mixed mode structure has been proposed. -
Solutions to Problems
Solutions to Problems Chapter l 2.6 1.1 (a)M-IC3T3/2;(b)M-IL-3y4J2; (c)ML2 r 2r 1 1.3 (a) 102.5 W; (b) 11.8 V; (c) 5900 W; (d) 6000 w 1.4 Two in series connected in parallel with two others. The combination connected in series with the fifth 1.5 6 V; 16 W 1.6 2 A; 32 W; 8 V 1.7 ~ D.;!b n 1.8 in;~ n 1.9 67.5 A, 82.5 A; No.1, 237.3 V; No.2, 236.15 V; No. 3, 235.4 V; No. 4, 235.65 V; No.5, 236.7 V Chapter 2 2.1 3il + 2i2 = 0; Constraint equation, 15vl - 6v2- 5v3- 4v4 = 0 i 1 - i2 = 5; i 1 = 2 A; i2 = - 3 A -6v1 + l6v2- v3- 2v4 = 0 2.2 va\+va!=-5;va=2i2;va=-3il; -5vl- v2 + 17v3- 3v4 = 0 -4vl - 2vz- 3v3 + l8v4 = 0 i1 = 2 A;i2 = -3 A 2.7 (a) 1 V ±and 2.4 .!?.; (b) 10 V +and 2.3 v13 + v2 2 = 0 (from supernode 1 + 2); 10 n; (c) 12 V ±and 4 n constraint equation v1- v2 = 5; v1 = 2 V; v2=-3V 2.8 3470 w 2.5 2.9 384 000 w 2.10 (a) 1 .!?., lSi W; (b) Ra = 0 (negative values of Ra not considered), 162 W 2.11 (a) 8 .!?.; (b),~ W; (c) 4 .!1. 2.12 ! n. By the principle of superposition if 1 A is fed into any junction and taken out at infinity then the currents in the four branches adjacent to the junction must, by symmetry, be i A. -
S-Parameter Techniques – HP Application Note 95-1
H Test & Measurement Application Note 95-1 S-Parameter Techniques Contents 1. Foreword and Introduction 2. Two-Port Network Theory 3. Using S-Parameters 4. Network Calculations with Scattering Parameters 5. Amplifier Design using Scattering Parameters 6. Measurement of S-Parameters 7. Narrow-Band Amplifier Design 8. Broadband Amplifier Design 9. Stability Considerations and the Design of Reflection Amplifiers and Oscillators Appendix A. Additional Reading on S-Parameters Appendix B. Scattering Parameter Relationships Appendix C. The Software Revolution Relevant Products, Education and Information Contacting Hewlett-Packard © Copyright Hewlett-Packard Company, 1997. 3000 Hanover Street, Palo Alto California, USA. H Test & Measurement Application Note 95-1 S-Parameter Techniques Foreword HEWLETT-PACKARD JOURNAL This application note is based on an article written for the February 1967 issue of the Hewlett-Packard Journal, yet its content remains important today. S-parameters are an Cover: A NEW MICROWAVE INSTRUMENT SWEEP essential part of high-frequency design, though much else MEASURES GAIN, PHASE IMPEDANCE WITH SCOPE OR METER READOUT; page 2 See Also:THE MICROWAVE ANALYZER IN THE has changed during the past 30 years. During that time, FUTURE; page 11 S-PARAMETERS THEORY AND HP has continuously forged ahead to help create today's APPLICATIONS; page 13 leading test and measurement environment. We continuously apply our capabilities in measurement, communication, and computation to produce innovations that help you to improve your business results. In wireless communications, for example, we estimate that 85 percent of the world’s GSM (Groupe Speciale Mobile) telephones are tested with HP instruments. Our accomplishments 30 years hence may exceed our boldest conjectures. -
A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions
Brigham Young University BYU ScholarsArchive Theses and Dissertations 2012-01-28 A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Taylor Matt Waddel Brigham Young University - Provo Follow this and additional works at: https://scholarsarchive.byu.edu/etd Part of the Electrical and Computer Engineering Commons BYU ScholarsArchive Citation Waddel, Taylor Matt, "A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions" (2012). Theses and Dissertations. 2934. https://scholarsarchive.byu.edu/etd/2934 This Thesis is brought to you for free and open access by BYU ScholarsArchive. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of BYU ScholarsArchive. For more information, please contact [email protected], [email protected]. A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Taylor M. Waddel A thesis submitted to the faculty of Brigham Young University in partial fulfillment of the requirements for the degree of Master of Science David J. Comer, Chair Aaron R. Hawkins Richard H. Selfridge Department of Electrical and Computer Engineering Brigham Young University April 2012 Copyright © 2012 Taylor M. Waddel All Rights Reserved ABSTRACT A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Taylor M. Waddel Department of Electrical and Computer Engineering, BYU Master of Science Composite cascode stages have been used in operational amplifier designs to achieve ultra- high gain at very low power. The flexibility and simplicity of the stage makes it an appealing choice for low power op-amp designs. Op-amp design using the composite cascode stage is often made more difficult through the lack of a design process. -
2-PORT CIRCUITS Objectives
Notes for course EE1.1 Circuit Analysis 2004-05 TOPIC 10 – 2-PORT CIRCUITS Objectives: . Introduction . Re-examination of 1-port sub-circuits . Admittance parameters for 2-port circuits . Gain and port impedance from 2-port admittance parameters . Impedance parameters for 2-port circuits . Hybrid parameters for 2-port circuits 1 INTRODUCTION Amplifier circuits are found in a large number of appliances, including radios, TV, video, audio, telephony (mobile and fixed), communications and instrumentation. The applications of amplifiers are practically unlimited. It is clear that an amplifier circuit has an input signal and an output signal. This configuration is represented by a device called a 2-port circuit, which has an input port for the input signal and an output port for the output signal. In this topic, we look at circuits from this point of view. To develop the idea of 2-port circuits, consider a general 1-port sub-circuit of the type we are very familiar with: The basic passive elements, resistor, inductor and capacitor, and the independent sources, are the simplest 1-port sub-circuits. A more general 1-port sub-circuit contains any number of interconnected resistors, capacitors, inductors, and sources and could have many nodes. Sometimes, perhaps when we have finished designing a circuit, we become less interested in the detail of the elements interconnected in the circuit and are happy to represent the 1-port circuit by how it behaves at its terminals. This is achieved by use of circuit analysis to determine the relationship between the voltage V1 across the terminals and the current I1 flowing through the terminals which leads to a Thevenin or Norton equivalent circuit, which can be used as a simpler replacement for the original complex circuit. -
A.F. Amplification with the Cascode
A.F. Amplification with the Cascode AN OUTLINE OF THE ADVANTAGES OF THE TWIN-TRIODE OVER THE PENTODE FOR A.F. By G. A. STEVENS R OR to the development of Band television Hence the circuit has the same gain as a pentode with the I III tuners the cascode was very little u5ed, its main same gm as the lower valve. use being in low noise r.f. stages, and it was used Also, since for any valve that has an impedance RA in asP a voltage amplifier in a stabilised power supply, where its cathode, its anode impedance is increased by a factor: high gain was required. + gm The properties that enhance its use for r.f. amplifica We can write (for1 the cascode:-RK)· tion also indicate its suitability as an a.f. voltage amplifier. ra=ra2(I+gm2 ral) (2) These advantages are as follows :- since the anode impedance of VI is in series with the l. High gain. cathode of V2. Therefore, from equations (1) and (2) 2. Low noise. we can derive:- 3. Low inter-electrode capacitances (particularly be gm g 1 2 tween input and output). ft= ra = ra2 . ml ( + gm ral) (3) From equation (2) it can be seen that for a twin triode 4. Capability of being designed with low phase shift (in feedback amplifiers). The characteristics of the cascode that give rise to the -----�------------Vs above advantages are best illustrated by a simplified analysis of the circuit (a fuller analysis will be found in the " Radio Designers' Handbook" by Langford-Smith, Ch. -
Dv/Dt-Control Methods for the Sic JFET/ Si MOSFET Cascode
Dv/dt-control methods for the SiC JFET/ Si MOSFET cascode . Daniel Aggeler, Member, IEEE, Francisco Canales, Member, IEEE, Juergen Biela, Member, IEEE, and Johann W. Kolar, Senior Member, IEEE „This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of ETH Zürich’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promo- tional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected]. By choosing to view this document you agree to all provisions of the copyright laws protecting it.” 4074 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013 Dv/Dt-Control Methods for the SiC JFET/Si MOSFET Cascode Daniel Aggeler, Member, IEEE, Francisco Canales, Member, IEEE, Juergen Biela, Member, IEEE, and Johann W. Kolar, Fellow, IEEE Abstract—Switching devices based on SiC offer outstanding per- formance with respect to operating frequency, junction tempera- ture, and conduction losses enabling significant improvement of the performance of converter systems. There, the cascode consist- ing of a MOSFET and a JFET has additionally the advantage of being a normally off device and offering a simple control via the gate of the MOSFET. Without dv/dt-control, however, the tran- sients for hard commutation reach values of up to 45kV/μs, which could lead to electromagnetic interference problems. Especially in drive systems, problems could occur, which are related to earth currents (bearing currents) due to parasitic capacitances.