EECS3611 Analog Integrated Circuit Design
Lecture 3
Current Source and Current Mirror
Introduction n Before any device can be used in any application, it has to be properly biased so that small signal AC parameters are well defined and the device is in proper regime of operation – usually in saturation in analog applications. n Current mirror method is a simple way to replicate well defined DC current sources in several independent circuit branches and is very popularly used in analog circuit design. n Current source is also widely used as active load to improve amplifier gain. n Current mirror is also a basic building block in current domain signal processing circuits. Types of Current Source
n Current source provides current to external circuit.
n Current sink receives current from the external circuit.
n In this course, we refer both current source and sink as current source.
n I-V plot of an ideal current source is shown.
n Current is not a function of the voltage across the current source. Realization of Current Source
I n Realization of current D source by MOSFET in I 0 saturation region by
VGS providing certain VGS. n ID is a function of VGS. n Due to the channel length modulation effect of the MOSFET, the output ID ID resistance of the current is finite. n There is a minimum output voltage for the MOSFET
VD current source, VDSsat to keep the transistor in saturation region. Basic Current Source Realization n A simple current source circuit uses a MOS transistor biased with a voltage divider. n This circuit is sensitive to power supply voltage VDD and the threshold voltage VTH.
VDD 1 ⎛W ⎞ VDD R2 2 ID2 = ⎜ ⎟ µCOX ( −VTH 2 ) (1+ λVDS 2 ) 2 ⎝ L ⎠2 R1 + R2 IOUT = ID2 R1 Note: (1) the threshold voltage may M2 vary by 50 to 100 mV from wafer to R2 wafer; (2) both µn and VTH exhibit temperature dependence. A good analog design should be insensitive to Process, supply Voltage and Temperature (PVT) variation. Conceptual Means of Copying Currents
• Use of a reference to generate various currents.
• Two identical MOS devices that have equal gate-source voltages and operate in saturation carry equal currents Current Mirror (1) n Replace R2 with a diode-connected transistor. I = I n OUT D2 For diode-connected transistor M1, we have: VDD VD1 = VG1, and VTH1>0.
VDS1 = VGS1 > VGS1 – VTH1 R n Hence, M1 is always in saturation region. Then: OUT IN
1 W 2 VDD −VGS1 I D1 = µCOX (VGS1 −VTH 1) (1+ λVGS1) = M1 M2 2 L R n For given ID1, we can solve the cubic equation to find the gate voltage, and find the value of R. n If the channel length modulation term is dropped, we can easily calculate the value of R as it is a quadratic equation.
1 W V −V I = µC (V −V )2 = DD GS1 D1 2 OX L GS1 TH 1 R Current Mirror (2) n More generally, the input current can be replaced with a constant current source IREF. The current mirror copies the current from the reference. n The basic idea here is to set VGS of M2 to a VDD fixed value by diode connected transistor M1. n Hence, M2 now looks like a fixed DC current I = I source and should have a very high OUT D2 IREF resistance looking into the drain terminal, I presenting characteristic of a typical current D1
source. M1 M2 n Since both transistors share the same VGS, same process and same temperature variations, the PVT effect will be cancelled off. n This current source simply utilizes matched devices to cancel PVT effect. This is a usual way in analog circuit designs to deal with PVT. Current Mirror Analysis n With accurate model that includes channel length modulation, we have:
1 ⎛W ⎞ 2 I D1 = ⎜ ⎟ µCOX (VGS1 −VTH 1) (1+ λVGS1) 2 ⎝ L ⎠1
1 ⎛W ⎞ 2 I D2 = ⎜ ⎟ µCOX (VGS1 −VTH 2 ) (1+ λVDS 2 ) 2 ⎝ L ⎠2 n Since both transistors are fabricated with the same
process steps, they have the same parameter µCOX and VTH. n So the current is: W (1+ λVOUT ) IOUT I D2 ( L)2 = = W I IN I D1 (1+ λVIN ) ( L)1 Effect of Channel-Length Modulation
• Neglecting channel-length modulation, we can write
• Allows precise copying of the current with no dependence on process and temperature General Concept of Current Mirror n Basic current mirror concept: I à V à I I α = OUT n Define current gain: I IN n Small-signal output resistance RO. n Minimum output voltage VOmin.
RO
IIN IOUT + + V Current to Voltage to - OUT V voltage GS current V IN conversion conversion
- Current Mirrors
n More generally, we can connect more transistors to make several output currents. n Every transistor shares the same VGS, hence same VOD. n By designing different size of the transistor, we can mirror out different currents from the reference current. Here channel length modulation effect is neglected. W ( L)n I = I Dn W REF ( L)1 Current Mirror Specifications n Small-signal output resistance RO. n Minimum output voltage VOmin. n Current gain error definition: I − I E = OUT OUT _ ideal IOUT _ ideal n Two types of error:
n systematic error: error caused by circuit structure.
n Random error: error caused by process variations. n These two types of error are commonly seen in many analog circuits. n A robust design is to minimize both systematic error and random error. Current Mirror Analysis n As VGS1 = VGS2 and assuming matched VTH1 = VTH2 IIN=ID1 IOUT = ID2 W (1+ λVOUT ) IOUT ( L)2 = I W IN ( ) (1+ λVIN ) L 1 V IN VOUT n The output resistance of current source is the M1 M2 output resistance of M2 1 1 RO = = λI D2 λIOUT n Normally, larger L is used so that λ effect is W ( )2 I = L I reduced and the output resistance is higher. OUT _ideal W IN ( )1 n The current gain systematic error is: L
IOUT − IOUT _ideal (1+ λVOUT ) λ E = = −1 = (VOUT −VIN ) ≈ λ(VOUT −VIN ) IOUT _ideal (1+ λVIN ) (1+ λVIN ) Current Mirror Analysis-Gate Overdrive
n This current relationship will be true as long as M2 is in saturation. Clearly, this will happen when VO=VDS2 > VOD2 n Gates of two transistors are connected: VGS2 = VGS1 so VGS2 – VTH2 = VGS1 – VTH1 as VTH1 = VTH2 à VOD1=VOD2 n Define the minimum output voltage: VOmin > VGS2 – VTH2 = VOD n Hence it is a benefit to have a low gate overdrive to increase the output swing. n How much should the gate overdrive be? n For same drain current, if the overdrive is small, transistor size will be very large, giving area penalty and speed penalty. n Overdrive voltage is a trade-off between speed and minimum output swing. Typically, overdrive is selected between 0.1-0.4V. Mismatch n Matched device means all the devices are designed having matched parameters. n Mismatch: parameter differences between matched devices
n Random statistical fluctuations
n Process bias
n Patten shift (Mask misalignment)
n Diffusion interactions Current Mirror Mismatch n A current mirror with current ratio of two is designed. Assume VIN=VOUT to eliminate the channel length modulation effect. n Due to mismatch between M1 and M2, the output current is not exactly
two times of the input current. IIN IOUT = 2IIN n 3 ways to implement: W (1+ λ2VOUT ) IOUT ( L)2 n A: W =W , L =0.5L = ≠ 2 2 1 2 1 W I IN (1+ λ1VIN ) M1 M2 ( L)1 n λ mismatch 2W W n B: W =2W , L =L + Δ 2 1 2 1 I OUT = L + ΔL ≠ 2 n ΔW and ΔL mismatch W W I IN + Δ L + ΔL IIN IOUT = 2IIN n C: Two transistors in parallel,
W3=W2=W1, L3=L2=L1 2(W + ΔW ) Best solution I M1 M3 OUT = L + ΔL = 2 W W M2 I IN + Δ L + ΔL Eliminate the Systematic Error n As we have seen, first simple current mirror output current
(IOUT = ID2) changes when the drain voltage of M2 changes. From model parameter λ = 0.05, the change in IOUT for a 1V change in VD2 will be 5%, which is not acceptable in many analog applications. n Can we do something about this?
IOUT − IOUT _ideal (1+ λVOUT ) E = = −1 ≈ λ(VOUT −VIN ) IOUT _ideal (1+ λVIN ) n The key to eliminate the current gain systematic error is to
make VOUT=VIN in the simple current mirror. n A straightforward way to achieve this would be having an extra MOSFET in series with M2 and fix the drain voltage of
M2 to VIN. This extra transistor is called cascode transistor. Cascode Current Mirror n If we choose VB = VGS4 + VX, VDD I = I then VY = VB – VGS4 à VY = VX. OUT D2 n If VX and VY are the same, the I channel length modulation term for REF both M1 and M2 will be the same. VB M4 Hence, the effect is corrected. X Y n M4 now shields Iout from voltage M1 M2 variations at the output node as VY is fixed by transistor M4 and does not depend on VOUT, eliminating the systematic error: channel length modulation mismatch. n The cascode transistor M4 normally has the same size as M2. n This current mirror is called cascode current mirror. Cascode Current Mirror n How to generate the required VB? n One simple way would be to create an exact replica of M4 in the left branch using a diode connected transistor M3 and utilize the gate voltage of M3 as V . B VDD Q
IREF
IOUT = ID2 VB
M3 M4
Y X M1 M2 Cascode Current Mirror n Transistor M1 and M3 will have the same overdrive VOD. n M2 and M4 have the same overdrive. n As mentioned before, M1 and M2 have the same overdrive. So all 4 transistors have the same overdrive
VOD. n Note all 4 transistors have the same threshold voltage
VTH if body effect is ignored. n Hence VX = VY=VTH + VOD n VGS3 = VOD + VTH as M1 and M3 carry the same current. n VG3 = VGS3 + VX = 2 VTH + 2 VOD ignoring body effect. n Hence VG4 = 2 VTH + 2 VOD n This should also be the case with body effect – only 2
VTH will become VTH1 + VTH3. Cascode Current Mirror-Output Resistance n The output resistance of this current mirror can be found using low frequency small signal equivalent circuit. A small signal is
applied at the drain of M4 to find RO. The method as the same in EE2005 where a test voltage vt is applied at the point where effective resistance is to be found and then current through the
test source, it is calculated so that RO=vt/it. n We will neglect gmb. Only modified result will be given later.
D4 it G4
vt ro4 gm4vgs4 G2 S4
gm2vgs2 ro2
S2 Cascode Current Mirror-Output Resistance n Since the gate voltages of M2 and M4 are fixed by M1and M3 and there is no variable voltage at M1 and M3, the gates of M2 and M4 are AC ground. n Clearly, v =0, v = - i r gs2 gs4 t o2 D4 it G4 v v t − s4 vt it = − gm4it ro2 ro4 gm4vgs4 ro4 G2 S4 v − i r i (1+ g r ) = t t o2 t m4 o2 g v r ro4 m2 gs2 o2 n Hence, RO = output resistance S2 of single cascode current mirror
vt RO = = ro4 (1+ gm4ro2 ) + ro2 it Cascode Current Mirror-Output Resistance n This type of result is quite generally applicable in the sense that due to presence of M2 below M4, the output resistance
seen at the drain of M4 is magnified by a factor ( 1 + gm4 ro2 ). We will use this result later whenever such a configuration appears. n Typically, gm4 r02 >> 1 and r02 = r04 = r0 as M2 and M4 carry the same current. R g r 2 O = m4 o2 2 n If body effect is included: RO = (gm4 + gmb )ro2 n Features of Cascode current mirror:
n No current gain systematic error.
n Higher output resistance.
n Higher minimum output voltage. Triple Cascode Current Mirror n A variation of this circuit known as triple Cascode current mirror where a device is added on the left and right is also
possible. RO in this case will be
VDD Q RO = ro6{1+ gm6[ro4 (1+ gm4ro2 ) + ro2 ]}
IOUT + ro4 (1+ gm4ro2 ) + ro2 3 IREF = gm6 gm4ro 2 M5 M6 ≈ ro (gmro ) Z
M3 M4
X Y
M1 M2 Minimum Output Voltage
n Returning to the 4 MOSFET circuit, if body VOUT effect is present, VTH2 and VTH4 will be IREF different and voltages will alter, but concept IOUT = ID2 still works. For the concept to work, M2 and VB M4 both must be in saturation, i.e. M3 M4 VX =VY =VTH + VOD and M4 must be in Y saturation region: VDS4 > VOD X M1 M2 n So VOUT>VT + 2 VOD n Hence VOUT needs to be quite high, over 1V, for proper operation. This could be a problem for low voltage design and will certainly reduce output swing. n A level shift follower is introduced and this
voltage requirement can be reduced to 2 VOD. Low Voltage Cascode Current Source 1 n In cascode current mirror, VX=VY and VX=VTH+VOD à VOmin=VTH+2VOD n If VX≠VY à Low output voltage, high swing n Adding a voltage shifter VTH, now VY=VX-VTH=VOD
VDD VDD
IREF IREF
IOUT IOUT VB VT + - M3 M4 M3 M4
Y Y X X M1 M2 M1 M2 Low Voltage Cascode Current Source 1 n All transistors have the same overdrive except M3. VX=VTH +VOD 1 1 ⎛W ⎞ 2 1 ⎛W ⎞ 2 n Since W3=1/4W1, I REF = µCOX ⎜ ⎟(VGS 3 −VTH ) = µCOX ⎜ ⎟VOD 2 4 ⎝ L ⎠ 2 ⎝ L ⎠
VGS3=VTH+2VOD à VG3=VX+VGS3=2VTH+3VOD
VG4=VTH+2VOD à VDD Q VY=VOD I VOmin=2VOD REF IOUT
2VTH+3VOD
M3 M5 M4 1 W3= /4W1 V VY=VOD X VTH+2VOD M1 M2 M6 Low Voltage Cascode Current Source 1 n The minimum output voltage is now 2VOD. n The output resistance remains the same as the Cascode current mirror. n However, since VX=VY is no longer valid, the current gain systematic error is not zero.
E ≈ λ(VY −VX ) = −λVTH n This drawback can be eliminated by another circuits, i.e. low voltage Cascode current mirror circuit 2. Low Voltage Cascode Current Source 2 n All the transistors have the same VDD overdrive. Set VB=VTH+2VOD IREF n V =V =V -(V +V )=V X Y B TH OD OD V B I n Then the minimum output voltage is: OUT V =2V OUT OD M3 M4 n And since V =V à X Y X Y
no current gain systematic error. M1 M2 n Design all transistors’ overdrive
smaller than its VTH. n Since VDS3=VGS1-VDS1=VTH>VODà M3 at saturation region. n All transistors are at saturation region. Low Voltage Cascode Current Source 2 n The low voltage cascade current source 2 has:
n High output resistance VDD n Low output voltage: VOUT=2VOD IREF n No current gain systematic error. n How to generate VB=VTH+2VOD? n Two ways: VB n Assuming same L for all MB 1 transistors, WB= /4W1
n Since WB=1/4W1 and same current 1 1 ⎛W ⎞ 2 1 ⎛W ⎞ 2 I REF = µCOX ⎜ ⎟(VB −VTH ) = µCOX ⎜ ⎟VOD 2 4 ⎝ L ⎠ 2 ⎝ L ⎠
n VB=VGS1=VTH+2VOD Low Voltage Cascode Current Source 2 n Another way to generate VB: n All transistor have the same overdrive except M6. n VDS6=VGS6 – VGS7 à VGS6 =VDS6 + VGS7 n Since VGS7>VTH, VDS6 1 W ⎡ 1 2 ⎤ I C (V V ) V V IREF D6 = µ OX ⎢ GS 6 − TH ⋅ DS 6 − DS 6 ⎥ 3 L ⎣ 2 ⎦ 1 W 2 M7 I = µC V V D7 2 L OX OD B 1 W6= /3W M6 ID6 = ID7 and VGS 6 −VTH =VDS 6 +VOD n Solve the equations: VDS6=VOD M5 n VB=VGS5+VDS6=VTH+2VOD Low Voltage Cascode Current Source 2 VDD VDD VDD VDD I IREF IREF IREF IREF OUT IOUT VB VB M7 1 W6= /3W M3 M4 M6 M3 M4 MB Y Y X X 1 M1 M2 M5 M1 M2 WB= /4W1 Full schematic of two types of low voltage Cascode current mirror 2. Wilson Current Mirror n Transistor M1 and M2 have the same overdrive: W (1+ λVY ) IOUT ( L)2 = W I IN (1+ λVX ) ( L)1 n Use feedback to stabilize the output current. n V ↑àI ↑àV ↑àV ↓àI ↓ OUT OUT Y X OUT VDD 2 V n High output resistance: gmro OUT IREF n Minimum output voltage: VTH+2VOD I n Since VX≠VY, the current gain OUT systematic error is not zero. M4 Y X E ≈ λ(VY −VX ) M1 M2 Wilson Current Mirror n By adding M3, VX=VY, the current gain systematic error is zero. 2 n High output resistance: gmro n Minimum output voltage: VTH+2VOD n Not good for low-voltage design VDD IREF IOUT M3 M4 Y X M1 M2 Current Mirror Summary Basic Current Mirror Increase output resistance Cascode Feedback Cascode Current Mirror Wilson Current Mirror Reduce minimum output voltage Low Voltage Cascode Current Mirror