Fully-Integrated Power Management with Switched-Capacitor DC-DC Converters

Hanh-Phuc Le

Advisors: Prof. Elad Alon and Prof. Seth Sanders

UC Berkeley p.1 Evolution of Chip Design

ƒ Initially driven by number of transistors/chip

ƒ More recently, driven by the performance (freq.)

ƒ Today, power becomes an important part of the key drivers

from http://vintagecomputerbits.com from http://www.cobolhacker.com p.2 ITRS Roadmap 2009

With constant die area: ƒ Core frequency increases by 1.05× / year ƒ On-demand accelerator engine frequency increases by 1.05× / year ƒ Number of cores increases by 1.4× / year p.3 Integration Challenges

ƒ Integration has a benefit in energy efficiency

ƒ Save IO power, board area

ƒ Requirement?

ƒ Need different voltage supply for different blocks/IPs and different modes of operations (DVS). p.4 Integration Challenges

p.5 Limited Resources !

Power pins

ƒ But the resources (pins and decap) are limited

p.6 Multiple Off-chip Supplies: Not Appealing

ƒ Split power plane leads to supply impedance degradation

ƒ Compensating by de-cap is area- consuming Æ costly solution

Æ Just supplying power from off- chip is not appealing

p.7 Fully Integrated DC-DC Converters

ƒ One global supply onto die ƒ Local power generated by fully integrated DC-DC converters

ƒ Don’t lose anything from package side

Æ How to make integrated DC-DC conversion efficient? p.8 Outline

ƒ Motivation

ƒ Integrated converter efficiency ƒ Choice of energy storage element ƒ Why switched-capacitor ƒ Efficiency analysis

ƒ Switched-capacitor converter design and prototype

p.9 DC-DC Converter: Linear vs. Switching

Linear Regulator Switching Regulator

V R out = L Vin + RR SWL

Inductor or Capacitor? V η = out ƒ Efficiency is ideally V independent of conversion in ratio.

ƒ Fundamental limit on ƒ Theoretically, can reach up efficiency to 100% efficiency

p.10 SC – Operation of 2-to-1 Conversion

Phase 1 ƒ Two-phase operation

ƒ Phase 1: charge capacitor

Phase 2

ƒ Phase 2: capacitor transfers charge to output

p.11 First Look at Switch Utilization

Magnetic boost/buck: 10-to-1 Ladder Switched-Cap: ƒ 10-to-1 V conversion, 1A @ 1V ƒ 10-to-1 V conversion, 1A@1V

ƒ S1,S2 rated for V-A product of ƒ 20 switches, each blocks 1V ƒ V*I = 10 V-A ƒ 18 switches handle 1/5 A ƒ Sum up to 20 V-A ƒ 2 switches handle 9/5 A

ƒ V-A product sums up to 36/5 =7.2 V-A

Æ Require high voltage switches Æ Native CMOS device convenient p.12 Energy Storage Element Inductor Capacitor

ƒ Very popular for a wide range of off- ƒ Usually considered appropriate for chip applications “low power”

ƒ Standard CMOS inductors have high ƒ High Q, high capacitance density. series resistance Æ low efficiency

ƒ Technology modifications are ƒ Highly compatible with costly commercial CMOS process

p.13 Switched Capacitor Power Converters

• Only switches and capacitors

• Using no inductors has advantages:

• Simplified full integration potential

• Works well over a wide power range

• Single mode, can adjust clock rate

• No minimum load

• No inductive switching losses

p.14 Why Not S-C ?

• Voltage rating of CMOS processes?

• Not suited for high current/power?

• Magnetic-based ckts = higher performance?

• Ripple?

• Interconnect difficulty for many caps?

• Difficult regulation?

p.15 Previous Work

Work [1] [2] Breussegem, VLSI 09 Somasekhar, VLSI 09 Technology 130nm Bulk 32nm Bulk

Topology 2/1 step-up 2/1 step-up

Interleaved Phases 16 32 Converter Area (mm2) 2.25 6.678x10-3

2 2 Power density @ ηmax 2.09 mW/mm 1.123 W/mm

Efficiency (ηmax) 82% 60%

Die photo

p.16 Switched Capacitor Loss

Two-phase operation: charge and discharge flying cap

ƒ Converter supplies digital circuits

ƒ Performance (fCPU) set by Vmin

ƒ Intrinsic switched-capacitor loss: I2 P = 2x L Cfly CfM flyswcapconv, p.17 Multi-Phase Interleaving

ƒ Good news: ƒ Interleaving can reduce ripple

without changing Vmin

2 ⎛ ⎞ IL 1 P ⎜1 += 1 ⎟ Cfly k ⎝ interleave ⎠ CfM flyswcapconv,

Ref: D. Ma, F. Luo, IEEE Trans. VLSI Sys., 2008 p.18 SC – Loss Optimization

ƒ 4 main loss components

= + + PPPP + P loss Rsw C fly bott.cap gate.cap

R I2 α I 2 on α L α W fC L α fC swbott sw swgate W sw Cf flysw Switch resist. Switched cap Bottom Plate Gate loss

Series Losses (Ro) Parasitic Losses (R//) p.19 Optimization for Efficiency

ƒ Efficiency trades off with power density

ƒ Low power density:

ƒ Bottom plate critical

ƒ High power density:

ƒ Flying cap critical

2 Ploss 1 sw CRV swon ≈ convkM bott + 2 PLoad convkM bott o CRV flyL p.20 Achievable Performance Eff. vs. Cap Density

ƒ Looks promising (kbott = 3%) ƒ Especially in mobile applications ƒ 1W/mm2 converter fits in decap area

ƒ Only looked at 2:1 converter so far ƒ Need to support multiple output voltage levels

p.21 Outline

ƒ Motivation

ƒ Integrated converter efficiency ƒ Choice of energy storage element ƒ Why switched-capacitor ƒ Efficiency analysis

ƒ Switched-capacitor converter design and prototype

p.22 Multiple Conversion Ratios

ƒ Standard cell design supports multiple conversion ratios

ƒ Fine output voltages achieved by

controlling fsw (or Wsw) ƒ Equivalent to linearly regulating down from peak efficiency

ƒ How to drive the switches?

Ref: D. Maksimovic and S. Dhar, IEEE PESC, 1999 p.23 Switch Drivers

ƒ Most switches easy to drive ƒ 2 voltage domains: ƒ (Vi – Vo) ƒ (Vo – GND)

ƒ M4, M5, and M7 challenging ƒ Experience voltages between the two domains p.24 Switch Driver – M5

ƒ “Flying” inverter INV5 powered off of C1 ƒ Controlled by top-plate of C2

ƒ Automatically synchronized by operation of other switches p.25 SC Converter Prototype

ƒ Implemented in 32nm SOI test-chip

ƒ Flying cap: MOS, 32-way interleaved

ƒ Supports 0.6V ~ 1.2V from Die photo 2V input

p.26 Measured Eff. vs. P-density

ƒ Measured in 1/2 mode (Vi = 2V, Vo ≈ 0.88V) ƒ 2 Results promising: 82% efficiency @ 0.55 W/mm p.27 Measured Eff. vs. Topologies

Efficiency vs. Vo fsw vs. Vo Settings: Vi = 2V

RL ≈ 4Ω at Vo = 0.8V

p.28 Previous Work

Work [1] [2] This work Breussegem, VLSI 09 Somasekhar, VLSI 09

Technology 130nm Bulk 32nm Bulk 32nm SOI

step-down Topology 2/1 step-up 2/1 step-up 1/2, 2/3, 1/3

Interleaved Phases 16 32 32

Converter Area (mm2) 2.25 6.678x10-3 0.36

2 2 2 Power density @ ηmax 2.09 mW/mm 1.123 W/mm 0.55 W/mm

Efficiency (ηmax) 82% 60% 82%

Die photo

p.29 Conclusions

ƒ Clear need for fully-integrated DC-DC converters ƒ Switched–capacitor converters a promising option

ƒ Design optimization enables both high power density and high efficiency ƒ In 2:1: 82% efficiency at 0.55W/mm2

ƒ Reconfiguration supports wide output voltage range ƒ >70% efficiency for Vo from ~0.75V to 1.15V with Vin = 2V

p.30 Why Not S-C ?

√ Voltage rating of CMOS processes?

√ Not suited for high current/power?

• Magnetic-based ckts = higher performance?

√ Ripple?

√ Interconnect difficulty for many caps? √ Difficult regulation?

p.31