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Fully Integrated Low-Ripple Switched-Capacitor DC–DC Converter with Parallel Low-Dropout Regulator

Fully Integrated Low-Ripple Switched-Capacitor DC–DC Converter with Parallel Low-Dropout Regulator

Article Fully Integrated Low-Ripple Switched- DC–DC Converter with Parallel Low-Dropout Regulator

Jeong-Yun Lee, Gwang-Sub Kim, Kwang-Il Oh and Donghyun Baek *

Microwave Embedded Circuit and System Laboratory, School of Electrical Engineering, Chung-Ang University, Seoul 06974, Korea; [email protected] (J.-Y.L.); [email protected] (G.-S.K.); [email protected] (K.-I.O.) * Correspondence: [email protected]; Tel.: +82-02-820-5828

 Received: 20 November 2018; Accepted: 11 January 2019; Published: 16 January 2019 

Abstract: In this paper, we propose a fully integrated switched-capacitor DC–DC converter with low ripple and fast transient response for portable low-power electronic devices. The proposed converter reduces the output ripple by filtering the control ripple via combining a low-dropout regulator with a main switched-capacitor DC–DC converter with a four-bit digital capacitance modulation control. In addition, the four-phase interleaved technique applied to the main converter reduces the switching ripple. The proposed converter provides an output voltage ranging from 1.2 to 1.5 V from a 3.3 V supply. Its peak efficiency reaches 73% with ripple voltages below 55 mV over the entire output power range. The transient response time for a load current variation from 100 µA to 50 mA is measured to be 800 ns. Importantly, the converter chip, which is fabricated using 0.13 µm complementary metal–oxide–semiconductor (CMOS) technology, has a size of 2.04 mm2. We believe that our approach can contribute to advancements in power sources for applications such as wearable electronics and the Internet of Things.

Keywords: DC–DC converter; switched capacitor; power management ; CMOS technology

1. Introduction Rapid advances in the Internet of Things and wearable electronic devices have led to an increasing demand for various types of sensors [1]. For portability, such devices/applications are usually powered by small batteries, which limit the operating time of sensor-based devices. Therefore, in order to increase the battery efficiency to provide longer operating times, power management units such as power management integrated circuits (ICs) are used to control power consumption [2,3]. The power management IC can be mounted on the same as the sensor IC, as shown in Figure1a. Meanwhile, certain o ff-chip passive components such as and are additionally required for external support of the power management IC because they cannot be integrated into the chip. In this regard, although multichip configurations are convenient for a sensor module design, the cost and size of the resulting modules increase. Thus, integration of the power management unit and passive components into a single sensor chip (Figure1b) is being actively pursued to reduce the module size and to increase market competitiveness [4–9]. The power management unit normally comprises a high-efficiency switching DC–DC converter and a linear low-dropout regulator. The switching DC–DC converter adjusts the battery voltage that drops over time to a fixed supply voltage, and its output drives the low dropout regulator to provide a voltage with low ripple and low noise to supply-sensitive analog components on the sensors [10,11].

Electronics 2019, 8, 98; doi:10.3390/electronics8010098 www.mdpi.com/journal/electronics Electronics 2019, 8, 98 2 of 16 Electronics 2019, 8, x FOR PEER REVIEW 2 of 15 Electronics 2019, 8, x FOR PEER REVIEW 2 of 15 Power Power Power Power management management

(a) (b) (a) (b) Figure 1. Types of sensor modules: (a) Sensor module with multichip architecture and (b) fully Figure 1.1. TypesTypes of sensor modules: ( (aa)) Sensor Sensor module module with with multichip multichip architecture architecture and ( b) fully integrated sensor module (PMIC, power management IC; PMU, power management unit; and LDO, integrated sensor module (PMIC, power manageme managementnt IC; PMU, power mana managementgement unit; and LDO, linear low dropout regulator). linear low dropout regulator).regulator). Figure 2 shows the two types of currently available switching DC–DC converters according to Figure2 2 shows shows thethe twotwo typestypes ofof currently currently available available switching switching DC–DC DC–DC convertersconverters accordingaccording toto the choice of passive components utilized for energy storage. The first type is the -based the choicechoice ofof passivepassive componentscomponents utilizedutilized forfor energyenergy storage.storage. The first first type is thethe inductor-basedinductor-based converter, which employs inductor L S and a push–pullpush–pull stage asas shownshown inin FigureFigure2 a.2a. TheThe outputoutput converter, which employs inductor LSS and a push–pull stage as shown in Figure 2a. The output voltage is regulated by by controlling controlling the the switches (Φ (Φ1 andand ΦΦ2) with) with either either a pulse–width a pulse–width modulator modulator or voltage is regulated by controlling the switches (Φ1 1and Φ2) 2with either a pulse–width modulator or a pulse– modulator [12,13]. The second type is the capacitor-based converter, which ora pulse–frequency a pulse–frequency modulator modulator [12,13]. [12,13 ].The The second second type type is is the the capacitor-based capacitor-based converter, converter, whichwhich employs a flyingflying capacitorcapacitor CCF andand fourfour switchesswitches ((ΦΦ1 andand ΦΦ2). The The output output voltage voltage is is regulated by employs a flying capacitor CFF and four switches (Φ11 and Φ22). The output voltage is regulated by controlling the switches with a pulse–width modulator, pulse–frequency modulator, or digital controlling thethe switches switches with with a pulse–width a pulse–width modulator, modulator, pulse–frequency pulse–frequency modulator, modulator, or digital or capacitor digital capacitor modulator (DCpM) [14–17]. The converting power depends on the storage capacity of the modulatorcapacitor modulator (DCpM) [(DCpM)14–17]. The[14–17]. converting The converting power depends power depends on the storage on the capacitystorage capacity of the passive of the componentspassive components as per the as per relation the relationP = L IP2L/2 = forL·I2 the/2 for inductor-based the inductor-based converter converter and P and= PCCV =2 C·V/2 for2/2 thefor passive components as per the relationL PL = L·I2/2 for the inductor-based converter andC PC = C·V2/2 for the capacitor-based converter. Here, we· note that inductor-based converters can deliver ·more power capacitor-basedthe capacitor-based converter. converter. Here, Here, wenote we note that that inductor-based inductor-based converters converters can deliver can deliver more more power power than capacitor-basedthan capacitor-based converters converters via increasing via increasi theng current the current at a fixed at a batteryfixed battery voltage, voltage,V . V Moreover,BAT. Moreover, high than capacitor-based converters via increasing the current at a fixed battery voltage,BAT VBAT. Moreover, high power efficiency can be achieved by use of an off-chip inductor with high and high powerhigh power efficiency efficiency can becan achieved be achieved by use by ofuse an of oanff-chip off-chip inductor inductor with with high high inductance inductance and and high high Q Q values while maintaining a low ripple voltage. Thus, the traditional inductor-based valuesQ values while while maintaining maintaining a lowa low ripple ripple voltage. voltage. Thus, Thus, the the traditional traditional inductor-basedinductor-based buckbuck converter has been widely adopted for moderate- to high-power applications. has been widely adopted for moderate- to high-powerhigh-power applications.applications.

(a) (b) (a) (b) Figure 2. Configuration of the step-down switching DC–DC converters: (a) Inductor-based converter Figure 2. Configuration of the step-down switching DC–DC converters: (a) Inductor-based converter Figureand (b) 2.capacitor-basedConfiguration converter. of the step-down switching DC–DC converters: (a) Inductor-based converter and (b) capacitor-based converter.converter. On the other hand, integrated inductors based on complementary metal–oxide–semiconductor On the other hand, integrated inductors basedbased onon complementarycomplementary metal–oxide–semiconductormetal–oxide–semiconductor (CMOS) technology present many limitations. First, the feasible inductance LS on a chip is limited (CMOS) technologytechnology present manymany limitations.limitations. First, the feasible inductance LS onon a chip is limited from a few to some tens of nanohenries due to the planar layout structure and fabricationS cost. Thus, from a few to some tens of nanohenries due to the planar layout structure and fabrication cost. Thus, Thus, integrated inductor-based converters should increase the modulation frequency to maintain ripple integrated inductor-based converters should incr increaseease the modulation frequency to maintain ripple levels; however, this also increases the switching loss. Second, series resistance RS is very high, which levels; however, however, this this also also increases increases the the switching switching loss. loss. Second, Second, series series resistance resistance RS is veryR is high, very which high, leads to an increased inductor loss over the switching loss, regardless of the useS of expensive leads to an increased inductor loss over the switching loss, regardless of the use of expensive additional manufacturing processes involving thick metals or integrated magnetic materials. Finally, additional manufacturing processes involving thick metals or integrated magnetic materials. Finally, the integrated inductor exhibits power loss due to the large parasitic capacitance in relation to the the integrated inductor exhibits power loss due to the large parasitic capacitance in relation to the

Electronics 2019, 8, 98 3 of 16 which leads to an increased inductor loss over the switching loss, regardless of the use of expensive additionalElectronics 2019 manufacturing, 8, x FOR PEER REVIEW processes involving thick metals or integrated magnetic materials. Finally,3 of 15 the integrated inductor exhibits power loss due to the large parasitic capacitance in relation to the substrate. In contrast, integrated capacito capacitorsrs afford afford either high parallel resistance RF or high Q factor via thethe metal–insulator–metalmetal–insulator–metal (MIM)(MIM) structure.structure. Th Therefore,erefore, when passive components are realized with CMOS technology, capacitorscapacitors aaffordfford betterbetter energyenergy densitydensity perper chip area relative to inductors, as explained in References [[18–20].18–20]. Consequently, capacitor-basedcapacitor-based convertersconverters exhibit better power and cost eefficiencyfficiency than than inductor-based inductor-based converters converters in low-power in low-power applications, applications, such assuch sensors as sensors and Internet and ofInternet Things of devices. Things devices. Figure3 3shows shows the the block block diagram diagram of a commonlyof a commonly used switched-capacitor used switched-capacitor (SC) DC–DC (SC) converter DC–DC utilizingconverter one-boundary utilizing one-boundary hysteresis feedback hysteresis for feedba outputck voltage for output regulation voltage and regulation its output and ripple its voltage.output Theripple controller voltage.provides The controller switching provides control switching signals to co thentrol converter signals into phasethe converter with the in input phase clock with CLK. the Theinput one-boundary clock CLK. The hysteresis one-boundary configuration hysteresis employs configuration only one comparatoremploys only for one the feedbackcomparator control for the to comparefeedback thecontrol output to compare voltage with the output the reference voltage voltage with theVREF reference[21]. In voltage the steady VREF state, [21]. thisIn the feedback steady causesstate, this a low-frequency feedback causes control a low-frequency ripple. In addition, control theripple. SC DC–DCIn addition, converter the SC “dumps” DC–DC the converter charge from“dumps” the inputthe charge to the from flying the capacitor input to and the from flying the capacitor capacitor and to thefrom output the capacitor at discrete to timethe output intervals at accordingdiscrete time to the intervals clock frequency. according This to discretethe clock charge frequency. transfer This causes discrete an unavoidable charge transfer switching causes ripple. an Theunavoidable switching switching ripple is usuallyripple. lowerThe switching than the controlripple is ripple usually because lower the than switching the control frequency ripple isbecause higher thanthe switching the control frequency frequency. is higher than the control frequency.

Figure 3.3.Block Block diagram diagram of theof switched-capacitorthe switched-capacitor (SC) DC–DC (SC) DC–DC converter converter using one-boundary using one-boundary hysteresis feedbackhysteresis and feedback its output and rippleits output voltage. ripple voltage.

Fully integrated SC DC–DC converters require additional techniques to suppress the ripple due Fully integrated SC DC–DC converters require additional techniques to suppress the ripple due to the size limitations of the load and flying capacitors. Figure4 shows three representative ripple to the size limitations of the load and flying capacitors. Figure 4 shows three representative ripple mitigation techniques applied to the SC DC–DC converters. The capacitance modulation technique mitigation techniques applied to the SC DC–DC converters. The capacitance modulation technique regulates the capacity of the flying capacitor, which transfers the charge to the load, to suppress regulates the capacity of the flying capacitor, which transfers the charge to the load, to suppress the the ripple. Flying capacitors are divided into several capacitors controlled by digital codes [15]. ripple. Flying capacitors are divided into several capacitors controlled by digital codes [15]. The The capacitance modulation operates as a low-capacity flying capacitor in the light-load state and is capacitance modulation operates as a low-capacity flying capacitor in the light-load state and is controlled to operate as a high-capacity flying capacitor in the heavy-load state. Further, pulse–width controlled to operate as a high-capacity flying capacitor in the heavy-load state. Further, pulse–width modulation controls the time for which the flying capacitor is connected to the load. This method modulation controls the time for which the flying capacitor is connected to the load. This method reduces the ripple by regulating the amount of charge delivered to the load per clock cycle [22]. reduces the ripple by regulating the amount of charge delivered to the load per clock cycle [22].

Figure 4. Ripple mitigation techniques.

Electronics 2019, 8, x FOR PEER REVIEW 3 of 15 substrate. In contrast, integrated capacitors afford either high parallel resistance RF or high Q factor via the metal–insulator–metal (MIM) structure. Therefore, when passive components are realized with CMOS technology, capacitors afford better energy density per chip area relative to inductors, as explained in References [18–20]. Consequently, capacitor-based converters exhibit better power and cost efficiency than inductor-based converters in low-power applications, such as sensors and Internet of Things devices. Figure 3 shows the block diagram of a commonly used switched-capacitor (SC) DC–DC converter utilizing one-boundary hysteresis feedback for output voltage regulation and its output ripple voltage. The controller provides switching control signals to the converter in phase with the input clock CLK. The one-boundary hysteresis configuration employs only one comparator for the feedback control to compare the output voltage with the reference voltage VREF [21]. In the steady state, this feedback causes a low-frequency control ripple. In addition, the SC DC–DC converter “dumps” the charge from the input to the flying capacitor and from the capacitor to the output at discrete time intervals according to the clock frequency. This discrete charge transfer causes an unavoidable switching ripple. The switching ripple is usually lower than the control ripple because the switching frequency is higher than the control frequency.

Figure 3. Block diagram of the switched-capacitor (SC) DC–DC converter using one-boundary hysteresis feedback and its output ripple voltage.

Fully integrated SC DC–DC converters require additional techniques to suppress the ripple due to the size limitations of the load and flying capacitors. Figure 4 shows three representative ripple mitigation techniques applied to the SC DC–DC converters. The capacitance modulation technique regulates the capacity of the flying capacitor, which transfers the charge to the load, to suppress the ripple. Flying capacitors are divided into several capacitors controlled by digital codes [15]. The capacitance modulation operates as a low-capacity flying capacitor in the light-load state and is controlled to operate as a high-capacity flying capacitor in the heavy-load state. Further, pulse–width modulation controls the time for which the flying capacitor is connected to the load. This method Electronics 2019, 8, 98 4 of 16 reduces the ripple by regulating the amount of charge delivered to the load per clock cycle [22].

FigureFigure 4. 4. RippleRipple mitigation mitigation techniques. techniques.

The multiphase interleaving technique divides a converter into multiple units and drives each unit in a different clock phase [19]. Because each converter operates in different phases, it appears that the ripple is operating at a frequency that is equal to the number of interleaved phases. The ripple is reduced by the number of interleaved phases. Against this backdrop, here, we propose a low-ripple fast-transient SC DC–DC converter operating over the output current range, which integrates all the active and passive components on a single chip. The converter employs a two-boundary hysteresis control with interleaving through a four-bit DCpM to reduce the switching ripple and a parallel low-dropout regulator (LDR) to considerably mitigate the ripple.

2. Principles of SC DC–DC Converters

2.1. Operation of the 2:1 Step-Down SC DC–DC Converter The 2:1 step-down SC DC–DC converter operates in the two phases, as shown in Figure5. The output voltage is half the input voltage under ideal operation. Hence, maximum efficiency can only be achieved if each phase operates at 50% duty cycle. During phase 1 (Φ1), the flying capacitor is connected between the input node VBAT and output node VL, as shown in Figure5b. In this phase, the flying capacitor is charged up to the voltage difference between VBAT and VL. During phase 2 (Φ2), the flying capacitor is connected to VL and the ground, as shown in Figure5c. The charge acquired by the flying capacitor during phase 1 is supplied to the output node. The repeated charging and discharging during these phases produce output voltage ripple ∆VL, as illustrated in Figure5d. Electronics 2019, 8, x FOR PEER REVIEW 4 of 15

The multiphase interleaving technique divides a converter into multiple units and drives each unit in a different clock phase [19]. Because each converter operates in different phases, it appears that the ripple waveform is operating at a frequency that is equal to the number of interleaved phases. The ripple is reduced by the number of interleaved phases. Against this backdrop, here, we propose a low-ripple fast-transient SC DC–DC converter operating over the output current range, which integrates all the active and passive components on a single chip. The converter employs a two-boundary hysteresis control with interleaving through a four-bit DCpM to reduce the switching ripple and a parallel low-dropout regulator (LDR) to considerably mitigate the ripple.

2. Principles of SC DC–DC Converters

2.1. Operation of the 2:1 Step-Down SC DC–DC Converter The 2:1 step-down SC DC–DC converter operates in the two phases, as shown in Figure 5. The output voltage is half the input voltage under ideal operation. Hence, maximum efficiency can only be achieved if each phase operates at 50% duty cycle. During phase 1 (Φ1), the flying capacitor is connected between the input node VBAT and output node VL, as shown in Figure 5b. In this phase, the flying capacitor is charged up to the voltage difference between VBAT and VL. During phase 2 (Φ2), the flying capacitor is connected to VL and the ground, as shown in Figure 5c. The charge acquired by the Electronicsflying capacitor2019, 8, 98 during phase 1 is supplied to the output node. The repeated charging5 ofand 16 discharging during these phases produce output voltage ripple ΔVL, as illustrated in Figure 5d.

(a) (b)

(c) (d)

Figure 5.5. Operation of a step-down SC DC–DC converter. ( a) Block diagram of a 2:12:1 step-downstep-down SCSC DC–DC converter; ( b) operation during phase 1; (c) operation during phase 2; and (d) thethe outputoutput voltage ripple.

Figure6 shows a simplified model of the 2:1 step-down SC DC–DC converter. The parallel RP represents the shunt loss due to parasitic capacitances in the switches and flying capacitors. We note here that RP is independent of the output current. The output impedance RO is connected in series with the load resistor RL. RO changes the load voltage, and its power loss, called series loss, is the sum of the conductance loss and the intrinsic SC loss. The switch conductance loss is caused by the resistance in the on state of the switch. Increasing the size of the switch reduces the conductance loss but increases the shunt loss via the parasitic capacitance of the switch [23]. The intrinsic SC loss is caused by voltage ripple ∆VF due to the charge and discharge of the capacitor, as shown in Figure5d. The intrinsic SC loss of a 2:1 step-down SC DC–DC converter can be expressed as [24,25]

∆V I 2 P = I F = L (1) CF L · 2 4 C f · F · SW where f SW denotes the switching frequency related to the two-phase operation. A fully-integrated SC DC–DC converter provides a relatively large load current with a small flying capacitance due to chip size limitations. Therefore, the intrinsic SC loss is larger than the switch conductance loss. In this paper, assuming an ideal switch, only the intrinsic SC loss is expressed as the series loss. Upon applying Equation (1) to this simplified model, the load current can be approximated as

(VBAT/2 VL) IL − = 4 CF fSW (VBAT/2 VL) (2) ≈ RO · · · −

The SC DC–DC converters regulate the output voltage via changing the value of Ro, which is adjusted through either frequency or pulse–width modulation of the switching clock. Electronics 2019, 8, x FOR PEER REVIEW 5 of 15

Figure 6 shows a simplified model of the 2:1 step-down SC DC–DC converter. The parallel resistor RP represents the shunt loss due to parasitic capacitances in the switches and flying capacitors. We note here that RP is independent of the output current. The output impedance RO is connected in series with the load resistor RL. RO changes the load voltage, and its power loss, called series loss, is the sum of the switch conductance loss and the intrinsic SC loss. The switch conductance loss is caused by the resistance in the on state of the switch. Increasing the size of the switch reduces the conductance loss but increases the shunt loss via the parasitic capacitance of the switch [23]. The intrinsic SC loss is caused by voltage ripple ΔVF due to the charge and discharge of the capacitor, as shown in Figure 5d. The intrinsic SC loss of a 2:1 step-down SC DC–DC converter can be expressed as [24,25] ΔVI2 PI=⋅FL = (1) CLF ⋅⋅ 24CFSWf

where fSW denotes the switching frequency related to the two-phase operation. A fully-integrated SC DC–DC converter provides a relatively large load current with a small flying capacitance due to chip size limitations. Therefore, the intrinsic SC loss is larger than the switch conductance loss. In this paper, assuming an ideal switch, only the intrinsic SC loss is expressed as the series loss. Upon applying Equation (1) to this simplified model, the load current can be approximated as (/2)VV− ≈=⋅⋅⋅−BAT L ICfVVLFSWBATL4(/2) (2) RO

The SC DC–DC converters regulate the output voltage via changing the value of Ro, which is Electronics 2019, 8, 98 6 of 16 adjusted through either frequency or pulse–width modulation of the switching clock.

Figure 6. SimplifiedSimplified model of a 2:1 step-down swit switched-capacitorched-capacitor (SC) DC–DC converter.

2.2. Multiphase Interleaved SC DC–DC Converter for Low Switching Ripple 2.2. Multiphase Interleaved SC DC–DC Converter for Low Switching Ripple As the SC DC–DCDC–DC converterconverter performs repeated charging and discharging, the output voltage exhibits anan inherent inherent switching switching ripple. ripple. Multiphase Multiphase interleaving interleaving aims toaims mitigate to mitigate this ripple this via ripple dividing via thedividing converter the converter into multiple into unitsmultiple and units driving and each drivin unitg witheach diunitfferent with clock different phases. clock Figure phases.7 illustrates Figure 7 aillustrates four-phase a interleavedfour-phase interleaved converter, with converter, each unit wi utilizingth each aunit quarter utilizing of the a totalquarter capacitance of the total and operatingcapacitance at and a 45 ◦operatingphase shift at relativea 45° phase to the shift clocks relati ofve the to neighboring the clocks of nodes. the neighboring The flying capacitances nodes. The offlying all units capacitances are equal, of andall units hence, are the equal, output and charge hence, perthe cycleoutput is charge also identical. per cycle The is also output identical. current The of eachoutput unit current is the of same each as unit that is of the the same converter as that without of the converter interleaving. without Thus, interleaving. the charge Thus, flowing the through charge eachflowing unit through of the each flying unit capacitor of the flying in multiphase capacitor in interleaving multiphase is interleaving the same as is thatthe same in the as case that ofin the Electronics 2019, 8, x FOR PEER REVIEW 6 of 15 originalcase of the converter. original converter.

FigureFigure 7. 7. BlockBlock diagram diagram of of s s four-phase four-phase interleaved interleaved SC SC DC–DC converter. Figure8 shows the operation of a four-phase interleaved SC DC–DC converter including the Figure 8 shows the operation of a four-phase interleaved SC DC–DC converter including the output voltage ripple with and without phase interleaving. In Figure8a, each SC DC–DC converter output voltage ripple with and without phase interleaving. In Figure 8a, each SC DC–DC converter without phase interleaving operates at the same clock phase (Φ1 and Φ2), producing output ripple ∆VL. without phase interleaving operates at the same clock phase (Φ1 and Φ2), producing output ripple In Figure8b, each converter of the interleaving configuration operates with 45 ◦ phase-shifted clocks ΔVL. In Figure 8b, each converter of the interleaving configuration operates with 45° phase-shifted (ΦA_1, ΦB_1, ΦC_1, and ΦD_1). Therefore, the effective switching frequency f ripple in the converter clocks (ΦA_1, ΦB_1, ΦC_1, and ΦD_1). Therefore, the effective switching frequency fripple in the converter increases by a factor of four relative to the case with no interleaving, thereby reducing the output increases by a factor of four relative to the case with no interleaving, thereby reducing the output ripple to 25% of the original ∆VL. Multiphase interleaving reduces the voltage ripple by increasing the ripple to 25% of the original ΔVL. Multiphase interleaving reduces the voltage ripple by increasing the effective switching frequency but maintains switching losses. To mitigate the output voltage ripple, a load capacitor is generally used. Multiphase interleaving also decreases this load capacitor value by a factor of four due to the increased ripple frequency.

(a) (b)

Figure 8. Operation of an interleaved switched-capacitor (SC) DC–DC converter: (a) Without interleaving and (b) upon applying interleaving.

2.3. Output Voltage Regulation The output voltage of the SC DC–DC converter can be modulated by the three methods depicted in Figure 9. First, frequency modulation enables the adjustment of the operating frequency of switching according to the load impedance, with the duty cycle usually set to 50%. This method changes the output impedance of the converter by varying the charge transferred from the flying

Electronics 2019, 8, x FOR PEER REVIEW 6 of 15

Figure 7. Block diagram of s four-phase interleaved SC DC–DC converter.

Figure 8 shows the operation of a four-phase interleaved SC DC–DC converter including the output voltage ripple with and without phase interleaving. In Figure 8a, each SC DC–DC converter without phase interleaving operates at the same clock phase (Φ1 and Φ2), producing output ripple ΔVL. In Figure 8b, each converter of the interleaving configuration operates with 45° phase-shifted Electronicsclocks (Φ2019A_1,, 8Φ, 98B_1, ΦC_1, and ΦD_1). Therefore, the effective switching frequency fripple in the converter7 of 16 increases by a factor of four relative to the case with no interleaving, thereby reducing the output ripple to 25% of the original ΔVL. Multiphase interleaving reduces the voltage ripple by increasing effective switching frequency but maintains switching losses. To mitigate the output voltage ripple, a the effective switching frequency but maintains switching losses. To mitigate the output voltage load capacitor is generally used. Multiphase interleaving also decreases this load capacitor value by a ripple, a load capacitor is generally used. Multiphase interleaving also decreases this load capacitor factor of four due to the increased ripple frequency. value by a factor of four due to the increased ripple frequency.

(a) (b)

Figure 8. OperationOperation of ofan aninterleaved interleaved switched switched-capacitor-capacitor (SC) (SC)DC–DC DC–DC converter: converter: (a) Without (a) Without interleaving interleavingand (b) upon and applying (b) upon interleaving. applying interleaving.

2.3. Output Voltage Regulation The output voltage of the SC DC–DC converter cancan be modulated by the three methods depicted inin FigureFigure9 .9. First, First, frequency frequency modulation modulation enables enable the adjustments the adjustment of the operating of the operating frequency frequency of switching of accordingswitching toaccording the load to impedance, the load impedance, with the duty with cycle the usuallyduty cycle set tousually 50%. Thisset to method 50%. This changes method the outputchanges impedance the output of impedance the converter of the by varyingconverter the by charge varying transferred the charge from transferred the flying capacitorfrom the flying to the load. However, it requires an additional voltage-controlled oscillator for frequency modulation. Second, time modulation enables the adjustment of the pulse width of the switching signal, which allows for control of the output current for the flying capacitors to charge or discharge. This method modulates the output current by varying the connection time to the output node. However, efficiency is low due to switching losses under light loads, given the low output current of the converter; nevertheless, the switching loss is maintained constant under this condition. Third, capacitance modulation of the charge transfer can be achieved by dividing the SC DC–DC converter into multiple converter cells in parallel and utilizing some cells to provide the required current to the load, thereby establishing “digital” operation. In this method, only the flying capacitors and switches of the converter cells involved in the output current circuit operate, thus improving the efficiency with respect to switching loss. However, the main limitation of this method is the required division of the SC DC–DC converter into cells for accurate output current control. This division increases the complexity of both the chip layout and the state machine to select the appropriate number of cells, thus imposing a tradeoff between efficiency and complexity. Electronics 2019, 8, x FOR PEER REVIEW 7 of 15 capacitor to the load. However, it requires an additional voltage-controlled oscillator for frequency modulation. Second, time modulation enables the adjustment of the pulse width of the switching signal, which allows for control of the output current for the flying capacitors to charge or discharge. This method modulates the output current by varying the connection time to the output node. However, efficiency is low due to switching losses under light loads, given the low output current of the converter; nevertheless, the switching loss is maintained constant under this condition. Third, capacitance modulation of the charge transfer can be achieved by dividing the SC DC–DC converter into multiple converter cells in parallel and utilizing some cells to provide the required current to the load, thereby establishing “digital” operation. In this method, only the flying capacitors and switches of the converter cells involved in the output current circuit operate, thus improving the efficiency with respect to switching loss. However, the main limitation of this method is the required division of the SC DC–DC converter into cells for accurate output current control. This division increases the complexityElectronics 2019 of, 8 ,both 98 the chip layout and the state machine to select the appropriate number of cells,8 of 16 thus imposing a tradeoff between efficiency and complexity.

light load heavy load light load heavy load light load heavy load

Φ1 Φ1 Φ1

Φ2 Φ2 Φ2

CF CF CF F↓ F↑ D↓ D↑ C↓ C↑

frequency control duty control capacitance control (a) (b) (c)

FigureFigure 9. MethodsMethods for for output voltage regulation: ( (aa)) Pulse–frequency Pulse–frequency modulation; modulation; ( (bb)) pulse–width pulse–width modulation;modulation; and and ( (cc)) capacitance capacitance modulation. modulation.

2.4.2.4. DCpM DCpM Control Control TheThe DCpM approachapproach allows allows control control of of the the amount amount of flying of flying capacitance capacitanc associatede associated withthe with charge the chargetransfer transfer in the converter,in the converter, thereby thereby enabling enabling load current load current regulation regulation given thatgiven the that amount the amount of charge of chargetransferred transferred in one clockin one cycle clock is cycle proportional is proportional to this capacitance.to this capacitance. With this With method, this method, the total the switch total switchsize involved size involved in the outputin the output current current of the SC of DC–DCthe SC DC–DC converter converter can be adjustedcan be adjusted according according to the size to theof thesize flying of the capacitance. flying capacitance. Thus, the Thus, shunt the lossshunt originating loss originating from parasitic from parasitic capacitances capacitances of the of flying the flyingcapacitors capacitors and switches and switches and the and conduction the conduction loss dueloss todue the to switchthe switch resistance resistance are reducedare reduced when when the theload load current current is low, is low, thereby thereby maintaining maintaining high high efficiency efficiency under under light light load. load. InIn the the implementation implementation of of the the SC SC DC–DC DC–DC converter converter with with DCpM DCpM control, control, the the flying flying capacitor capacitor is is divideddivided into into a a binary-weight binary-weight bank. bank. Figure Figure 1010 showshowss the the structure structure of of the the SC SC DC–DC DC–DC converter converter with with a a four-bitfour-bit DCpM DCpM control. control. The The flying flying capacitance capacitance is is divided divided into into four four different different banks banks of of size size xx1,1, xx2,2, xx4,4, andand x8. These These four converter cellscells formform aa singlesingle matrix, matrix, and and the the charge charge transfer transfer operation operation is enabledis enabled by bycontrol control code codeC[3:0]. C[3:0]. Figure Figure 11 shows 11 shows a model a model of the of proposed the proposed SC DC–DC SC DC–DC converter converter based onbased a four-bit on a four-bitDCpM. TheDCpM. 2:1 transformerThe 2:1 represents represents the required the voltagerequired step-down voltage step-down process. The process. output The impedance output impedanceRO and the R shuntO andimpedance the shunt impedance RP are binary-weighted RP are binary-weighted according toaccording the DCpM to controlthe DCpM signal. control The signal.output The impedance output impedance is determined is determined as 1/(4 CF f SWas), 1/(4· whereCF·fSWf SW), whereand C FfSWdenote and C theF denote switching the switching frequency · · frequencyand the unit and flying the unit capacitance, flying capacita respectively.nce, respectively. The load current The loadIL of current the converter IL of the can converter be expressed can be as expressed as X3 3 n IL = 4 (0.5 V VL) f C[n] 2 C (3) =⋅· ()· ⋅BAT − ⋅· SW ⋅· [] ⋅· n ⋅· F IVVfCnCLL40.5BAT SWn=0 2 F (3) n=0 where VI and VL represent the input and output voltages, respectively, and DCpM code C[n] determines the output current.

Electronics 2019, 8, x FOR PEER REVIEW 8 of 15 Electronics 2019, 8, x FOR PEER REVIEW 8 of 15 where VI and VL represent the input and output voltages, respectively, and DCpM code C[n] Electronics 2019, 8, 98 9 of 16 determineswhere VI and the outputVL represent current. the input and output voltages, respectively, and DCpM code C[n] determines the output current.

Figure 10. Binary-weighted switched-capacitor (SC) DC–DC converter cells for DCpM. Figure 10. Binary-weighted switched-capacitor (SC)(SC) DC–DC converter cells for DCpM.

3 C[3] RO/2 VBAT VBAT/2 3 C[3] RO/2 VBAT VBAT/2 2 C[2] RO/2 2 C[2] RO/2 1 C[1] RO/2 CL RL 1 C[1] RO/2 CL RL 0 C[0] RO/2 0 C[0] RO/2

Figure 11. ModelModel of of the the proposed switched-capacitor (S (SC)C) DC–DC converter using a four-bit DCpM. 3. ProposedFigure 11. Low-Ripple Model of the SC proposed DC–DC switched-capacitor Converter (SC) DC–DC converter using a four-bit DCpM. 3. Proposed Low-Ripple SC DC–DC Converter 3. ProposedFigure 12 Low-Ripple shows the blockSC DC–DC diagram Converter of the proposed SC DC–DC converter, which is composed of a Figure 12 shows the block diagram of the proposed SC DC–DC converter, which is composed of main converter, an auxiliary LDR, and a DCpM controller. The main converter provides most of the a mainFigure converter, 12 shows an theauxiliary block diagramLDR, and of a the DCpM propos controller.ed SC DC–DC The main converter, converter which provides is composed most of current to the load, whereas the LDR assists the main converter to provide an accurate output current. thea main current converter, to the load,an auxiliary whereas LDR, the LDRand aassists DCpM the controller. main converter The main to provideconverter an provides accurate mostoutput of The LDR is powered by a small four-phase interleaved SC converter to improve efficiency. To reduce current.the current The to LDR the isload, powered whereas by ath smalle LDR four-phase assists the interleaved main converter SC converter to provide to improvean accurate efficiency. output the switching ripple, four interleaved phases (0 , 45 , 90 , and 135 ) are adopted for the SC DC–DC Tocurrent. reduce The the LDR switching is powered ripple, by four a small interleaved four-phase ◦phases ◦interleaved (0◦°, 45°, 90 SC°◦, andconverter 135°) areto improveadopted efficiency.for the SC converter cells. The current of the main converter is controlled by the DCpM, which compares the DC–DCTo reduce converter the switching cells. ripple,The current four interleaved of the main phases converter (0°, 45° , is90 °controlled, and 135° ) byare theadopted DCpM, for thewhich SC output voltage with two reference voltages using two clocked comparators. If output voltage V > comparesDC–DC converter the output cells. voltage The withcurrent two ofreference the main vo ltagesconverter using is two controlled clocked comparators.by the DCpM, If outputwhichO VREF + ∆V or V outputREF + Δ V−voltage or V+ REFΔV + and Δ−V VorREF < V−REF ΔV −, theΔV ,binary the binary code coderemains decreases unchanged. or increases, respectively. If VL lies between VREF + ΔV and VREF − ΔV, the binary code remains unchanged.

Electronics 2019, 8, 98 10 of 16 Electronics 2019, 8, x FOR PEER REVIEW 9 of 15 -1,0,1 decoder

FigureFigure 12. 12. BlockBlock diagram diagram of of the the proposed proposed switch switched-capacitored-capacitor (SC) (SC) DC–DC DC–DC converter. converter.

FigureFigure 13a13a shows shows one one of the four-phase interlea interleavedved SC DC–DC converter matrices matrices used used in in the the mainmain converter,converter, whichwhich is is composed composed of fourof four converter converter cells. cells. Each cellEach employs cell employs a 2:1 step-down a 2:1 step-down topology topologyand operates and operates in a bi-phase in a bi-phase mode (Φ mode1 and (ΦΦ21) and with Φ 50%2) with duty 50% cycle. duty Thecycle. magnitudes The magnitudes of the of flying the flyingcapacitors capacitorsCF and C switchesF and switches are four-bit are four-bit binary-weighted. binary-weighted. Binarycode BinaryC[3:0] code of C the[3:0] DCpM of the controller DCpM controllereither enables either or enables disables or the disables operation the of operation each converter of each cell converter to adjust cell the to output adjust current. the output As shown current. in AsFigure shown 13b, in the Figure auxiliary 13b, the LDR auxiliary powered LDR by powere the smalld by four-phase the small four-phase SC converter SC employs converter a employs p–channel a p–channelmetal–oxide–semiconductor metal–oxide–semiconductor (PMOS) pass (PMOS) pass andtransistor a two-stage and a two-stage operational operational amplifier. . Figure 14 Figureshows the14 shows block diagramthe block of diagra the proposedm of the LDR-assisted proposed LDR-assisted SC DC–DC converterSC DC–DC with converter a low output with ripple.a low outputThe proposed ripple. converterThe proposed exhibits converter only a switchingexhibits on ripple,ly a switching and themain ripple, converter and the is main controlled converter by the is controlledDCpM via by two-boundary the DCpM via hysteresis two-boundary feedback, hysteresis which feedback, also produces whicha also low-frequency produces a low-frequency control ripple. controlNevertheless, ripple. theNevertheless, two-boundary the controllertwo-boundary can limit controller the control can limit ripple the between controlV ripple between∆V and V VREF −+ REF − REF ∆∆VV .and Therefore, VREF + ∆ theV. Therefore, LDR with the a low LDR output with current a low output capability current can compensatecapability can for compensate the output currentfor the outputfluctuation current due tofluctuation the feedback due control to the ripple feedback by providing control ripple an opposite-phase by providing accurate an opposite-phase current to the accurateload. This current approach to the ensures load. thatThis theapproach DCpM ensures control bitsthat performing the DCpM coarsecontrol tuning bits performing are fixed at coarse every tuningoutput are current fixed range,at every and output hence, current the output range, voltage and hence, ripple the of output the proposed voltage ripple converter of the presents proposed no convertercontrol ripple presents due tono hysteresis control ripple feedback due to but hy onlysteresis switching feedback ripple. but only switching ripple. FigureFigure 15a15a shows shows a a simplified simplified model model of of the the pr proposedoposed SC SC DC–DC DC–DC converter, converter, where where the the 2:1 2:1 transformertransformer represents represents the the 2:1 2:1 voltage voltage step-down step-down process. process. The The main main converter converter is is described described using using a a binary-weighedbinary-weighed unit-resistance RO,, which equalsequals 11/(4·/(4 CCFLY·fSW),), where where ffSW andand CCFLY representrepresent the the O · FLY· SW SW FLY switchingswitching frequency frequency and unit flyingflying capacitance, respectively.respectively. CurrentCurrent IIMAINMAIN ofof the the main main SC SC DC–DC DC–DC converterconverter can can be be expressed expressed as

3 3 n IkVVfCnC=⋅40.5 ⋅() ⋅ − ⋅ ⋅X[] ⋅ 2 ⋅ (4) I MAIN= 4 k i (0.5 V BATV L) SWf  C[n] 2n FC (4) MAIN · i · · BAT − L · SW n·=0 · · F n=0 where VI, VO, and ki denote the input voltage, output voltage, and number of interleaved phases, respectively. The auxiliary LDR is modeled as a fixed resistance RSUB for each SC DC–DC converter cell and a variable resistance RLDR for the LDR. Consequently, output current ILDR of the auxiliary LDR can be expressed as

Electronics 2019, 8, 98 11 of 16

where VI, VO, and ki denote the input voltage, output voltage, and number of interleaved phases, respectively. The auxiliary LDR is modeled as a fixed resistance RSUB for each SC DC–DC converter cell and a variable resistance RLDR for the LDR. Consequently, output current ILDR of the auxiliary Electronics 2019, 8, x FOR PEER REVIEW 10 of 15 ElectronicsLDR can 2019 be expressed, 8, x FOR PEER as REVIEW 10 of 15

ILDRIkVVV= 4=⋅40.5ki (0.5 ⋅()V ⋅BAT −VL −VDO ⋅)f fSW ⋅⋅ 2C2 CF (5)(5) LDR· · ii · BAT− L− DO· SW· F· (5) where VDO representsrepresents the the dropout dropout voltage voltage of of the the pass pass tr transistoransistor in in the the LDR. LDR. Hence, Hence, the the auxiliary auxiliary LDR can finely finely adjust the output current. From From Figure Figure 15b,15b, we note that the main converter provides a discrete coarsecoarse currentcurrent that that is is determined determined by by the the DCpM DCpM code, code, whereas whereas the the auxiliary auxiliary converter converter “fills” “fills” the thediscrete discrete steps steps using using the linear the linear LDR. LDR. Thus, Thus, the proposed the proposed SC DC–DC SC DC–DC converter converter can provide can provide any output any outputcurrent current in its operating in its operating range without range without requiring requiring a complex a complex pulse–width pulse–width modulated modulated or pulse–frequency or pulse– frequencymodulated modulated controller. controller.

(a) (b)

Figure 13. Schematic of ( a)) the main switched-capacitor (SC) (SC) DC–DC DC–DC converter converter and and ( (b)) the auxiliary SC DC–DC converter.

Figure 14. 14. BlockBlock diagram diagram of the of theproposed proposed LDR-assisted LDR-assisted SCSC DC–DCDC–DC SC DC–DC converterconverter converter andand itsits and outputoutput itsoutput rippleripple voltage.ripple voltage.

Electronics 2019, 8, 98 12 of 16 Electronics 2019, 8, x FOR PEER REVIEW 11 of 15

auxiliary converter

RSUB RLDR

3 C[3] RO/2 VBAT VBAT/2 VL

2 C[2] RO/2

1 C[1] RO/2 CL RL

0 C[0] RO/2

main converter

(a) (b)

FigureFigure 15. 15.( a(a)) The The simplified simplified model model of of the the proposed proposed switched-capacitor switched-capacitor (SC) (SC) DC–DC DC–DC converter converter and and (b) output(b) output current current versus versus dropout dropout voltage voltage of the of LDR the LDR pass pass transistor. transistor.

4.4. ResultsResults andand DiscussionDiscussion TheThe proposed proposed SC SC DC–DC DC–DC converter converter was was implemented implemented using using a a 0.13 0.13µ μmm CMOS CMOS process process (Dongbu (Dongbu HiTek,HiTek, Seoul, Seoul, Korea), Korea), which which provides provides triple-well triple-well CMOS CMOS devices devices and and MIM MIM capacitors capacitors with with eight eight metal metal layerslayers and and one one poly poly layer. layer. Figure Figure 16 shows 16 shows the microphotograph the microphotograph of the fabricated of the fabricated SC DC–DC SC converter. DC–DC Theconverter. core chip The has core an area chip of has 2.04 an mm area2. Severalof 2.04 mm pads2. areSeveral allocated pads to are the allocated input and to output the input ports and to reduceoutput interconnectionports to reduce lossinterconnection during measurement. loss during The measur area ofement. the capacitors The area isof the the major capacitors contributor is the tomajor the sizecontributor of the main to the SC size DC–DC of the converter, main SC converterDC–DC conver cells, andter, converter load capacitor. cells, Stackedand load capacitors capacitor. utilizing Stacked thecapacitors MIM and utilizing metal–oxide–semiconductor the MIM and metal–oxide–semico (MOS) capacitorsnductor are (MOS) used tocapacitors increase theare capacitanceused to increase per unitthe area,capacitance which areper1 unit fF/µ area,m2 and which 2.5 fF are/µm 12 fF/forμ them2 and MIM 2.5 and fF/ MOSμm2 for capacitors, the MIM respectively. and MOS capacitors, Figure 17 showsrespectively. the measured Figure output17 shows voltage the measured and current. output The voltage proposed and converter current. hasThe an proposed outputvoltage converter range has ofan 1.2 output to 1.5 voltage V from arange 3.3 V of supply. 1.2 to The1.5 V output from voltagea 3.3 V waveformssupply. The were output measured voltage with the use ofwere an MSO7104Bmeasured with oscilloscope the use of (Keysight an MSO7104B Technologies, oscilloscope Santa (Keysight Rosa, CA, Technologies, USA). The output Santa voltage Rosa, CA, and USA). LDR controlThe output signal voltage are shown and LDR for the control LDR insignal the onare andshown off statesfor the in LDR Figure in the17a. on The and output off states voltage in Figure and current17a. The were output set tovoltage 1.2 V and 100currentµA, were respectively. set to 1.2 When V and the 100 LDR μA, was respectively. deactivated, When a high the rippleLDR was of approximatelydeactivated, a 380high mV ripple was of obtained. approximately This is because380 mV thewas DCpM obtained. control This code is because does not the converge DCpM control to one valuecode atdoes light not loads, converge and theto one variation value at in light the control loads, codeand the generates variation a largein the control control ripple. code generates However, a thelarge ripple control drops ripple. below However, 10 mV upon the ripple activation drops of belo thew LDR, 10 mV which upon fine-tunes activation theof the output LDR, current which andfine- limitstunes thethe DCpM output control current code and to limits one value the DCpM in the maincontrol SC code DC–DC to one converter. value in Thus, the themain control SC DC–DC ripple disappearsconverter. Thus, due to the the control bounded rippl DCpMe disappears control due code, to the and bounded only the DC switchingpM control ripple code, appears and only in the the outputswitching voltage ripple waveform. appears Figure in the 17 outputb shows voltage the load waveform. transient performance Figure 17b whenshows the the current load suddenlytransient changesperformance from 120whenµA the to 50current mA. The suddenly output changes current andfrom output 120 μ voltageA to 50 are mA. restored The output to their current regulated and valuesoutput in voltage less than are 800 restored ns. to their regulated values in less than 800 ns. FigureFigure 18 18aa shows shows the the measured measured e ffiefficiencyciency according according to to the the output output current current at theat the input input voltage voltage of 3.3of 3.3 V. TheV. The effi efficiencyciency depends depends on on the the output output voltage, voltage, with with the the output output voltage voltage of of 1.5 1.5 V V corresponding corresponding toto the the highest highest e efficiencyfficiency and and lowest lowest output output current. current. ThisThis isis becausebecause thethe voltagevoltage ratioratio ofof thethe inputinput toto outputoutput isis thethe closestclosest toto the the transformer transformer ratio ratio of of the the 2:1 2:1 step-down step-down topology topology in in this this case. case. TheThe peakpeak eefficiencyfficiency is is 73, 73, 70, 70, and and 65% 65% at at output output voltages voltages of of 1.5, 1.5, 1.35, 1.35, and and 1.2 1.2 V, respectively.V, respectively. Figure Figure 18b shows18b shows the measuredthe measured output output voltage voltage ripple ripple according according to the outputto the output current. current. The maximum The maximum ripple values ripple remain values belowremain 26, below 36, and 26, 55 36, mV and at 55 output mV at voltages output ofvoltages 1.5, 1.35, of and 1.5, 1.21.35, V, respectively.and 1.2 V, respectively. Figure 19 shows Figure the 19 lossshows contributions the loss contributions and their ratio and according their ratio to according the output to current. the output At the current. very lowAt the output very current, low output the DCpMcurrent, loss the and DCpM the LDRloss and quiescent the LDR loss quiescent decrease theloss power decrease effi theciency, power but efficiency, as the current but increases,as the current the switchingincreases, loss the andswitching conduction loss and loss conduction dominates. loss Figure dominates. 19a shows Figure an e ffi19aciency shows reduction an efficiency of 2.3% reduction due to theof 2.3% LDR lossdue atto thethe outputLDR loss current at the of output 5 mA butcurrent only of a 0.23%5 mA reductionbut only a at 0.23% the output reduction current at the of 53output mA. current of 53 mA.

Electronics 2019, 8, 98 13 of 16 ElectronicsElectronics 2019 2019, 8, ,8 x, xFOR FOR PEER PEER REVIEW REVIEW 1212 of of 15 15 Electronics 2019, 8, x FOR PEER REVIEW 12 of 15

Figure 16. Microphotograph of the proposed switched-capacitor (SC) converter. FigureFigure 16. 16. MicrophotographMicrophotograph of of the the proposed proposed sw switched-capacitoritched-capacitor (SC) converter.

VVL L== 1.2 1.2 V V VL = 1.2 V

800800 ns ns 0.50.5 V V 800 ns 0.5 V 1 1µs µs 1 µs

ILIL== 0.1 0.1 mA mA IL IL== 50 50 mA mA IL = 0.1 mA IL = 50 mA

(a) (b) (a) (b) Figure 17. Measured output voltage and current waveforms: (a) the ripple voltage at a low output Figure 17. Measured output voltage and current waveforms: ( (aa)) the the ripple ripple voltage voltage at at a a low output current with and without the low dropout regulator (LDR) in operation and (b) the load transient current with and without the low dropou dropoutt regulator (LDR) in operation and ( b) the load transient responses to a sudden current variation. responses to a sudden current variation.

7575 6060 75 60 7070 50 70 50 65 65 40 40 6060 60 3030 55 30 55 2020 V V=1.50V=1.50V V V=1.50V,=1.50V, Ideal Ideal efficiency=90.9% efficiency=90.9% L L 50 L L 20 V =1.50V efficiency (%) 50 V =1.50V, Ideal efficiency=90.9% L efficiency (%) 50 L

efficiency (%) V =1.35V V =1.35V, Ideal efficiency=81.8% V =1.35VL V =1.35V,L Ideal efficiency=81.8% VL=1.35V VL=1.35V, Ideal efficiency=81.8% 1010 L 4545 L 10 V =1.20V 45 V V=1.20V,=1.20V, Ideal Ideal efficiency=72.7% efficiency=72.7% V =1.20VL VL=1.20V,L Ideal efficiency=72.7% VL=1.20V

output voltage ripple (mV) output L L voltage ripple (mV) output 0 4040 voltage ripple (mV) output 0 40 0 1020304050 000 1020304050 1020304050 0 1020304050 0 1020304050 output current (mA) output current (mA) output current (mA) output current (mA)

(a) (b) (a) (b) Figure 18. (a) Measured efficiency and (b) voltage ripple according to output current. FigureFigure 18. 18. ((aa)) Measured Measured efficiency efficiency and and ( (bb)) voltage voltage ripple ripple according according to output current.

Electronics 2019, 8, 98 14 of 16 Electronics 2019, 8, x FOR PEER REVIEW 13 of 15

100 100 DCpM loss LDR loss 80 Switching loss 80 Conduction loss 60 60

40 40 DCpM loss loss (%) LDR loss 20 20

ratio of loss (%) ratio of Switching loss Conduction loss 0 0 0 1020304050 0 1020304050 output current (mA) output current (mA) (a) (b)

Figure 19. LossLoss contributions from from DCpM, LDR, switch switching,ing, and conduction losses versus output current for VL = 1.2 V: (a) the loss contributions and (b) the ratio of loss contribution. current for VL = 1.2 V: (a) the loss contributions and (b) the ratio of loss contribution.

Table1 1 compares compares thethe performanceperformance ofof thethe proposedproposed SCSC DC–DCDC–DC converterconverter withwith similarsimilar low-ripplelow-ripple converters. As As the the ripple ripple depends depends on on the the output output cu current,rrent, load load capacitance, capacitance, and and switching switching frequency, frequency, we used the following figurefigure ofof meritmerit forfor aa fairfair rippleripple comparisoncomparison [[26,27]:26,27]: FoM=⋅⋅ I() C f V  FoM ripple= I L/ C Lf SWV ripple (6)(6) ripple L L · SW · ripple As can be observed from the table, our approach affords the highest figure of merit. As can be observed from the table, our approach affords the highest figure of merit.

Table 1. Comparison of results of previously reported studies and current study. Table 1. Comparison of results of previously reported studies and current study. Characteristic [15] [22] [26] [28] This Work Characteristic [15][22][26][28] This Work Technology (nm) 45 130 130 130 130 Technology (nm) 45 130 130 130 130 Input voltage (V) 1.8 1.8 1–1.2 1.2 3.3 Input voltage (V) 1.8 1.8 1–1.2 1.2 3.3 OutputOutput voltage voltage (V) (V) 0.8–1 0.8–1 0.3–0.55 0.3–0.55 1.8–2.1 1.8–2.1 0.2–1.1 0.2–1.1 1.2–1.5 1.2–1.5 MaximumMaximum load load current current (mA) (mA)10 10 55 55 2.61 2.61 2.53 2.53 53 53 PowerPower density density (mW /(mW/mmmm2) 2) 5050 24.524.5 0.67 0.67 7.56 7.56 31.2 31.2 FlyingFlying capacitance capacitance (pF) (pF) 534 534 - - 400 400 840 840 2176 2176 Load capacitance (pF) 700 5000 400 764 1000 Load capacitance (pF) 700 5000 400 764 1000 30 Ripple (mV) <50 <50 <10 30 8–55 Ripple (mV) <50 <50 <10 @IL = 30 µA 8–55 Peak efficiency (%) 69 70 82@IL = 30 80.6 μA 73 SwitchingPeak frequency efficiency (MHz) (%) 30 69 100 70 82 20 80.6 5 73 40 FigureSwitching of merit, frequency Equation (6) (MHz) 9.5 30 2.2 100 20 14 5 3.25 40 24.1 Active area (mm2) 0.16 0.97 2.25 0.291 2.04 Figure of merit, Equation (6) 9.5 2.2 14 3.25 24.1 Active area (mm2) 0.16 0.97 2.25 0.291 2.04 5. Conclusions 5. ConclusionsWe proposed a fully-integrated SC DC–DC converter with low ripple and high efficiency. The proposedWe proposed converter a fully-integrated employs a four-bit SC DC–DC DCpM controlconverter and with includes low ripple an auxiliary and high LDR efficiency. in parallel. The Theproposed DCpM converter efficiently employs optimizes a four-bit the gate DCpM switching control lossesand includes according an auxiliary to the output LDR in current, parallel. and The a DCpMtwo-boundary efficiently hysteresis optimizes method the gate supports switching the ripple losses control. according In the to proposed the output structure, current, the and feedback a two- boundaryripple is removed hysteresis by means method of ansupports auxiliary the LDR ripple connected control. in parallel.In the proposed Moreover, structure, four-phase the interleaving feedback rippleis employed is removed to reduce by themeans switching of an ripple auxiliary in the LD mainR connected converter. Thein parallel. proposed Moreover, SC DC–DC four-phase converter interleavingaffords an output is employed voltage to range reduce of 1.2–1.5 the switching V from ari 3.3pple V in supply the main and converter. achieves a The peak proposed efficiency SC of DC– 73% DCand converter ripple below affords 55 mV an overoutput the voltage entire outputrange of current 1.2–1.5 range. V from We a believe 3.3 V supply that our and approach achieves will a peak find efficiencyutility in power of 73% sources and ripple for sensor-based below 55 mV devices over the of entire the future. output current range. We believe that our approach will find utility in power sources for sensor-based devices of the future. Author Contributions: J.-Y.L., G.-S.K., and K.-I.O. carried out the experiments and computer simulation and wrote the paper under the supervision of D.B.

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Funding: This research received no external funding. Acknowledgments: This work was supported by the Institute for Information and Communications Technology Promotion (IITP) grant funded by the Korea government (MSIT) (No. 2018-0-01663, Development of Communication-Sensing Converged B5G Millimeter Wave System) and by the Chung-Ang University Graduate Research Scholarship in 2018. Conflicts of Interest: The authors declare no conflict of interest.

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