EE247 Lecture 9 Switched-Capacitor Filters Today

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EE247 Lecture 9 • Switched-Capacitor Filters – “Analog” sampled-data filters: • Continuous amplitude • Quantized time – Applications: • First commercial product: Intel 2912 voice-band CODEC chip, 1979 • Oversampled A/D and D/A converters • Stand-alone filters E.g. National Semiconductor LMF100

Switched-Capacitor Filters Today • Emulating resistor via switched-capacitor network • 1st order switched-capacitor filter • Switch-capacitor filter considerations: – Issue of aliasing and how to avoid it – Tradeoffs in choosing sampling rate – Effect of sample and hold – Switched-capacitor filter electronic noise – Switched-capacitor integrator topologies

f1 f2 • Capacitor C is the “switched capacitor” vIN vOUT S1 S2

• Non-overlapping clocks f1 and f2 control switches S1 and S2, C respectively

• vIN is sampled at the falling edge of f1

– Sampling frequency fS f1 • Next, f2 rises and the voltage across C is transferred to vOUT f2 • Why does this behave as a resistor? T=1/fs

Switched-Capacitor Resistors

• Charge transferred from v to IN f1 f2 vOUT during each clock cycle is: vIN vOUT S1 S2 Q = C(v – v ) IN OUT C • Average current flowing from

vIN to vOUT is:

i=Q/t = Q . fs f1

Substituting for Q: f2

i =fS C(vIN – vOUT) T=1/fs

i = fS C(vIN – vOUT) f1 f2

With the current through the switched- vIN vOUT capacitor resistor proportional to the S1 S2 voltage across it, the equivalent “switched capacitor resistance” is: C

1 Req = fCs

Example: f1

fs ==1MHz,C1pF f2 T=1/f ®Req=W1Mega s

Switched-Capacitor Filter

REQ • Let’s build a “switched- capacitor vIN vOUT ” filter …

• Start with a simple RC LPF C2

• Replace the physical resistor by an equivalent switched- f capacitor resistor 1 f2

• 3-dB bandwidth: vIN vOUT C S1 S2 w =1 =´f 1 -3dB RCCs eq22 C1 C2 1 C1 ff-3dB =´s 2Cp 2

f1 f2 Req

V Vout Vin Vout in S1 S2 C2 C1 C2

1 1 1 C1 f-3dB = ´ ff-3dB =´s 2p R C 2Cp 2 eq 2 • Corner freq. proportional to: • Corner freq. proportional to: System clock (accurate to few ppm) Absolute value of Rs & Cs C ratio accurate à < 0.1% Poor accuracy à 20 to 50%

Ñ Main advantage of SC filtersà inherent corner frequency accuracy

Typical Sampling Process Continuous-Time(CT) Þ Sampled Data (SD)

Continuous- time Time Signal

Sampled Data

Sampled Data + ZOH

Clock

Nomenclature: x(kT) º x(k) Continuous time signal x(t) x(t) Sampling interval T

Sampling frequency fs = 1/T Amplitude Sampled signal x(kT) = x(k)

• Problem: Multiple continuous time signals can yield exactly the same discrete time signal T • Let’s look at samples taken at 1ms intervals of several sinusoidal waveforms … time

Sampling Sine Waves

T = 1ms

fs = 1/T = 1MHz fin = 101kHz

time voltage y(nT)

v(t) = sin [2p(101000)t]

T = 1ms

fs = 1MHz fin = 899kHz

time voltage

v(t) = - sin [2p(899000)t]

Sampling Sine Waves

T = 1ms

fs = 1MHz fin = 1101kHz

time voltage

v(t) = sin [2p(1101000)t]

Identical samples for:

v(t) = sin [2p fint ]

v(t) = sin [2p( fin+fs )t ]

v(t) = sin [2p( fin-fs )t ]

àMultiple continuous time signals can yield exactly the same discrete time signal

Sampling Sine Waves Frequency Spectrum Time domain

fs = 1/T Voltage

time y(nT)

Frequency domain Before Sampling After Sampling

+ fs - fin fs fin 899kHz 1101kHz Amplitude Amplitude f f f f fin s 2fs … in fs 2fs … 101kHz 1MHz 101kHz 1MHz

Frequency domain Signal scenario before sampling Amplitude f in fs /2 fs 2fs …….. f

Frequency domain Signal scenario after sampling & filtering Amplitude f in fs /2 fs 2fs f

Key point: Signals @ nfS ± fmax__signal fold back into band of interest àAliasing

Aliasing

• Multiple continuous time signals can produce identical series of samples

• The folding back of signals from nfS±fsig down to ffin is called aliasing

– Sampling theorem: fs > 2fmax_Signal • If aliasing occurs, no signal processing operation downstream of the sampling process can recover the original continuous time signal

• Must obey sampling theorem:

fmax_Signal < fs/2 • Two possibilities: 1. Sample fast enough to cover all spectral components, including "parasitic" ones outside band of interest

2. Limit fmax_Signal through filtering

How to Avoid Aliasing?

1- Push Frequency domain sampling frequency to x2 of the highest freq. Amplitude fin f à In most cases fs_old 2fs_old …….. s_new f not practical

2- Pre-filter signal to Frequency domain eliminate signals above then sample Amplitude fs/2 f in fs /2 fs 2fs f

EECS 247 Lecture 9: Switched-Capacitor Filters © 2005 H.K. Page 18 Anti-Aliasing Filter Considerations Desired Signal Brickwall Band Anti-Aliasing Realistic Pre-Filter Anti-Aliasing Pre-Filter Anti-Aliasing Switched-Capacitor Filter Filter Amplitude

0 fs/2 fs 2fs ... f

Case1- B= fmax _Signal = fs /2 • Non-practical since an extremely high order anti-aliasing filter (close to an ideal brickwall filter) is required • Practical anti-aliasing filter àNonzero filter "transition band" • In order to make this work, we need to sample much faster than 2x the signal bandwidth à"Oversampling"

Practical Anti-Aliasing Filter Desired Signal Parasitic Band Tone Anti-Aliasing Switched-Capacitor Filter Filter Attenuation

Case2 - B= f _ << f /2 max Signal s 0 B fs/2 fs-B fs ... f • More practical anti-aliasing filter • Preferable to have an anti- aliasing filter with: àThe lowest order possible 0 B ... f àNo frequency tuning required (if frequency tuning is required then why use switched-capacitor filter, just use the prefilter!?)

Maximum Aliasing Dynamic Range

Filter Order

fs /fin-max

* Assumptionà anti-aliasing filter is Butterworth type (not a necessary requirement) àTradeoff: Sampling speed versus anti-aliasing filter order Ref: R. v. d. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd ed., Kluwer publishing, 2003, p.41]

Effect of Sample & Hold

...... Sample & Hold Tp Ts

•Using the Fourier transform of a rectangular impulse: T sin(pfT ) H ( f ) = p p Ts pfTp

abs(H(f)) T =0.5T 0.4 p s 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 3 f / fs

Sample & Hold Effect (Reconstruction of Analog Signals)

Time domain

Tp=Ts e

T =T g p s a t l

o time v ZOH

Magnitude sin()p fT Frequency domain Hf()= s droop due p fTs to sinx/x Amplitude effect f in fs 2fs …….. f

Magnitude droop due to sinx/x effect: Time domain

Case 1) f =f /4 sig s Voltage time

-1dB Frequency domain

Droop= -1dB Amplitude f in fs f

Sample & Hold Effect (Reconstruction of Analog Signals)

Time domain

Magnitude droop due 1 to sinx/x effect: 0.8 0.6

0.4 Case 2) 0.2 0 Amplitude fsig=fs /32 -0.2 -0.4

-0.6

-0.8 sampled data after ZOH -1 0 0.5 1 1.5 2 2.5 3 3.5 Time -5 x 10

-0.0035dB Droop= -0.0035dB Frequency domain

à High Amplitude oversampling ratio fin f f desirable s

H(Z) Sampler S/H e.g. (S.C.F)

Time Domain t

Freq. Domain f f f 2f fs 2fs fs 2fs Freq. in s s Domain General Signal f f f f 2f B s 2fs s 2fs s s

1st Order Filter Transient Analysis

SC response: extra delay and steps with Impractical finite rise time.

exaggerated

No problem

ZOH

• ZOH: Emulates an ideal S/Hà pick signal after settling (usually at end of clock phase) • Adds delay and sin(x)/x distortion • When in doubt, use a ZOH in periodic ac simulations

Periodic AC Analysis

Sinc due to ZOH 1. RC filter output RC filter output 2. SC output after ZOH 3. Input after ZOH 4. Corrected output Corrected output • (2) over (3) no ZOH • Repeats filter shape

around nfs SC output • Identical to RC for after ZOH f <

Periodic AC Analysis • SPICE frequency analysis – ac linear, time-invariant circuits – pac linear, time-variant circuits

• SpectreRF statements V1 ( Vi 0 ) vsource type=dc dc=0 mag=1 pacmag=1 PSS1 pss period=1u errpreset=conservative PAC1 pac start=1 stop=1M lin=1001

• Output

– Divide results by sinc(f/fs) to correct for ZOH distortion

S1 ( Vi c1 phi1 0 ) relay ropen=100G rclosed=1 vt1=-500m vt2=500m S2 ( c1 Vo_sc phi2 0 ) relay ropen=100G rclosed=1 vt1=-500m vt2=500m C1 ( c1 0 ) capacitor c=314.159f C2 ( Vo_sc 0 ) capacitor c=1p R1 ( Vi Vo_rc ) resistor r=3.1831M C2rc ( Vo_rc 0 ) capacitor c=1p CLK1_Vphi1 ( phi1 0 ) vsource type=pulse val0=-1 val1=1 period=1u width=450n delay=50n rise=10n fall=10n CLK1_Vphi2 ( phi2 0 ) vsource type=pulse val0=-1 val1=1 period=1u width=450n delay=550n rise=10n fall=10n V1 ( Vi 0 ) vsource type=dc dc=0 mag=1 pacmag=1 PSS1 pss period=1u errpreset=conservative PAC1 pac start=1 stop=3.1M log=1001 ZOH1 ( Vo_sc_zoh 0 Vo_sc 0 ) zoh period=1u delay=500n aperture=1n tc=10p ZOH2 ( Vi_zoh 0 Vi 0 ) zoh period=1u delay=0 aperture=1n tc=10p

ZOH Circuit File

// Copy from the SpectreRF Primer // Implement switch with effective series module zoh (Pout, Nout, Pin, Nin) (period, // resistence of 1 Ohm delay, aperture, tc) if ( ($time() > start) && ($time() <= stop)) I(hold) <- V(hold) - V(Pin, Nin); node [V,I] Pin, Nin, Pout, Nout; else parameter real period=1 from (0:inf); I(hold) <- 1.0e-12 * (V(hold) - V(Pin, Nin)); parameter real delay=0 from [0:inf); parameter real aperture=1/100 from (0:inf); // Implement capacitor with an effective parameter real tc=1/500 from (0:inf); { // capacitance of tc integer n; real start, stop; I(hold) <- tc * dot(V(hold)); node [V,I] hold; analog { // Buffer output // determine the point when aperture V(Pout, Nout) <- V(hold); begins n = ($time() - delay + aperture) / period // Control time step tightly during + 0.5; start = n*period + delay - aperture; // aperture and loosely otherwise $break_point(start); if (($time() >= start) && ($time() <= stop)) $bound_step(tc); // determine the time when aperture ends else n = ($time() - delay) / period + 0.5; $bound_step(period/5); stop = n*period + delay; } $break_point(stop); }

Vo Vin Vout S1 S2 Vin time C1 C2 time

Antialiasing Pre-filter

f-3dB fs 2fs Output Frequency Spectrum Switched-Capacitor Filters à problem with aliasing

Sampled-Data Filters Anti-aliasing Requirements

• Frequency response repeats at fs , 2fs , 3fs….. • High frequency signals close to fs , 2fs ,….folds back into passband (aliasing) • Most cases must pre-filter input to a sampled-data filter to remove signal at f > fs /2 (nyquist à fmax < fs /2 ) • Usually, anti-aliasing filter included on-chip as continuous-time filter with relaxed specs. (no tuning)

f-3dB fs 2fs

• Voice-band SC filter f-3dB =4kHz & fs =256kHz • Anti-aliasing filter requirements: – Need 40dB attenuation at clock frequency – Incur no phase-error from 0 to 4kHz – Gain error 0 to 4kHz < 0.05dB – Allow +-30% variation for anti-aliasing corner frequency (no tuning) Need to find minimum required filter order

Oversampling Ratio versus Anti-Aliasing Filter Order

Maximum Aliasing Dynamic Range

Filter Order

fs/fin_max

* Assumptionà anti-aliasing filter is Butterworth type

à2nd order Butterworth àNeed to find minimum corner frequency for mag. droop < 0.05dB

• Normalized frequency for 0.05dB droop: need perform passband simulationà 0.34à 4kHz/0.34=12kHz • Set anti-aliasing filter corner frequency for minimum corner frequency 12kHz à Nominal Stopband Attenuation dB corner frequency 12kHz/0.7=17.1kHz • Check if attenuation requirement is satisfied for widest filter bandwidth à 17.1x1.3=22.28kHz • Normalized filter clock frequency to max. corner freq. à256/22.2=11.48à make sure enough attenuation Normalized w • Check phase-error within 4kHz From: Williams and Taylor, p. 2-37 bandwidth: simulation

Example : Anti-Aliasing Filter Antialiasing Pre-filter

f-3dB fs 2fs

• Voice-band SC filter f-3dB =4kHz & fs =256kHz • Anti-aliasing filter requirements: – Need 40dB attenuation at clock freq. – Incur no phase-error from 0 to 4kHz – Gain error 0 to 4kHz < 0.05dB – Allow +-30% variation for anti-aliasing corner frequency (no tuning) à2-pole Butterworth LPF with nominal corner freq. of 17kHz & no tuning (12kHz to 22kHz corner frequency )

• Sampling theorem à fs > 2fmax_Signal

• Signals at frequencies nfS± fsig fold back down to desired signal band, fsig à This is called aliasing & usually dictates use of anti-aliasing pre-filters • Oversampling helps reduce required order for anti-aliasing filter • S/H function shapes the frequency response with sinx/x à Need to pay attention to droop in passband due to sinx/x • If the above requirements are not met, CT signal can NOT be recovered from SD or DT without loss of information

Switched-Capacitor Noise

• Resistance of switch S1 f1 f2 produces a noise voltage on C with variance kT/C vIN vOUT S1 S2 • The corresponding noise charge C is Q2=C2V2=kTC

• This charge is sampled when S1 opens

T=1/fs

f f • Resistance of switch S2 1 2 contributes to an vIN vOUT uncorrelated noise charge S1 S2 on C at the end of f 2 C • Mean-squared noise charge

transferred from vIN to vOUT each sample period is 2 Q =2kTC f1

T=1/fs

Switched-Capacitor Noise

• The mean-squared noise current due to S1 and S2’s kT/C noise is :

222 i==(Qfs) 2kBsTCf

• This noise is approximately white and distributed between 0 and fs/2 (noise spectra à single sided by convention) The spectral density of the noise is:

2 2 i12kTCf 4kT =Bs=4kTCf==B using R f BsEQ D fs c RfC 2 EQs à S.C. resistor noise equals a physical resistor noise with same value!

Sampling Noise from SC S/H

Netlist Netlist ahdl_include "zoh.def" simOptions options reltol=10u vabstol=1n iabstol=1p

Vclk 100ns Vrc Vrc_hold 100kOhm R S1 PNOISE Analysis PNOISE1 sweep from 0 to 20.01M (1037 steps)

ZOH1 C T = 100ns 1pF

SpectreRF PNOISE: check 100kOhm R1 noisetype=timedomain Voltage NOISE VNOISE1 noisetimepoints=[…] C1 1pF as alternative to ZOH. noiseskipcount=large might speed up things in this case. PSS pss period=100n maxacfreq=1.5G errpreset=conservative PNOISE ( Vrc_hold 0 ) pnoise start=0 stop=20M lin=500 maxsideband=10

Sampled Noise Spectrum

Density of sampled noise Sampled noise normalized including sinc distortion density corrected for sinc distortion

Sampled noise in

0 … fs/2: 62.2mV rms

(expect 64mV for 1pF)

Switched-Capacitor Integrator

- f ò 1 +

f2 C I T=1/fs f1 f2 Vin - forffsignal<< sampling

Cs Vo + fCs ´ s ®VVin dt 0 = CI ò Cs w0s=´f CI Main advantage: No tuning needed à critical frequency function of ratio of caps & clock freq.

C C f I I 1 f2 Vin Vin - - C C s s Vo Vo + +

f High 1 f2 High à C Charged to Vin s àCharge transferred from Cs to CI

Continuous-Time versus Discrete Time Design Flow

Continuous-Time Discrete-Time

• Write differential equation • Write difference equation à relates output sequence to input sequence • Laplace transform (F(s)) • Let s=jw à F(jw) Vo(nTsi)=-V[(n-1)Ts] ...... • Use delay operator Z -1 to • Plot |F(jw)|, phase(F(jw) transform the recursive realization to algebraic equation in Z domain

-1 Voi(ZZ) = ZV( )...... • Set Z= e jwT

• Plot mag./phase versus frequency

CI f1 f2 Vin Vs -

Cs Vo +

f Clock 1 f2 f1 f2 f1

Vin

Switched-Capacitor Integrator (n-3/2)Ts (n-1)T s (n-1/2)Ts nTs (n+1)Ts f Clock 1 f2 f1 f2 f1

Vin

F1 à Qs [(n-1)Ts]= Cs Vi [(n-1)Ts] , QI [(n-1)Ts] = QI[(n-3/2)Ts]

F2 à Qs [(n-1/2) Ts] = 0 , QI [(n-1/2) Ts] = QI [(n-1) Ts] + Qs [(n-1) Ts]

F1 _à Qs [nTs ] = Cs Vi [nTs ] , QI [nTs ] = QI[(n-1) Ts ] + Qs [(n-1) Ts]

Since Vo= - QI /CI & Vi = Qs / Cs à CI Vo(nTs) = CI Vo [(n-1) Ts ] -Cs Vi [(n-1) Ts ]

• Transforming the recursive realization to algebraic equation in Z domain: – Use Delay operator Z :

nTs...... 1® éù -1 ëû(n-1)Ts ...... Z® éù -1/2 ëû(n-1/2)Ts ...... Z® éù +1 ëû(n+1)Ts ...... Z® éù +1/2 ëû(n+1/2)Ts ...... Z®

Switched-Capacitor Integrator

CI f1 f2 Vin - f1

Cs Vo +

éùéù -CVIIo(nTs)=-+CVosë(n--1)TssûCVinëû(n1)T C Voso(nT)=-VVéùéù(n--1)Tsss (n1)T ëûëûCI in --11C Voo(Z)=-ZV(Z)Zs V(Z) CI in V o (Z)=-´Cs Z-1 CI 1-Z-1 Vin DDI (Direct-Transform Discrete Integrator)

• Consider variable Z=esT for any s in left-half-plane (LHP): S= - a+jb Z= e-aT . e jbT = e-aT (cosbT + jsin bT) |Z|= e-aT , angle(Z)= bT à For values of S in LHP |Z|<1 à For a =0 (imag. axis in s-plane) |Z|=1 (unit circle) if angle(Z)=p=bT then b=p/T=w

Then w=ws/2

z-Domain Frequency Response

• LHP singularities in s- Z plane imag. axis in plane map into inside of s domain unit-circle in Z domain • RHP singularities in s- plane map into outside of unit-circle in Z domain • The jw axis maps onto the unit circle

LHP in s domain

(cos(wT),sin(wT)) • Particular values: – f = 0 à z = 1

– f = fs/2 à z = -1 • The frequency response is obtained by evaluating f = fs/2 H(z) on the unit circle at f = 0 z = ejwT = cos(wT)+jsin(wT)

• Once z=1 (fs/2) is reached, the frequency response repeats, as expected

z-Domain Frequency Response

(cos(wT),sin(wT)) • The angle to the pole is equal to 360° (or 2p radians) times the ratio of the pole frequency to the 2pf f = fs/2 f sampling frequency S f = 0

Pole from fà0 in s-plane mapped to f1 z=+1 increasing (Z-1)

As frequency f = f /2 increases z domain s 1 pole moves on unit circle (CCW)

Once pole gets to (Z=- 1 ),(f=fs /2), frequency response repeats

DDI Switched-Capacitor Integrator

CI f1 f2 - f1 Vin V C C o ()w =-´s 1 s Vo CI éù( jwwT)23( jT) + Vin êú1+jwT+++-....1 2!3! ëûêú VC-1 Cs 1 os(Z)=-´Z =-´ C1- CI (wwTT)23( ) I 1Z- jwT-++.... Vin 2!3! forwT1<< VCos1 jTw (Z)=-´=,Ze V CI Z1- o ()w =-´Cs 1 Vin CI jTw Vin Cs =-´=1 SinceT= 1/fs CI e1jTw - Vo Cs fs 1 Seriesexpansionforex ()w =-´=- CI sCIRseq 234 Vin ex =+1x+++xxx..... 2!3!4! ® idealintegrator

CI f1 f2 Vin - f1

Cs Vo +

-1 Vo (Z)=-Cs ´=Z ,ZejTw CI 1-Z-1 Vin - jwT/2 =CCss´1 =´e CCII1--ejwTee- jwwT/2jT/2

=-jeCs ´´- jwT/2 1 CI 2sin(wT/2)

=-Cs 1 ´´wT/2 e- jwT/2 CI jTw sin(wT/2)

Ideal Integrator) Magnitude Error Phase Error

DDI Switched-Capacitor Integrator

CI f1 f2 Vin - f1

Cs Vo +

Vo (Z)e=-Cs 1 ´´wT/2 - jwT/2 CI jTw sin(wT/2) Vin Ideal Integrator) Magnitude Error Phase Error Example: Mag. & phase error for: 1- f / fs=1/12 à Mag. Error = 1% or 0.1dB Phase error=15 degree Q = -3.8 intg DDI Integrator 2- f / fs=1/32 à Mag. Error=0.16% or 0.014dB à magnitude error no problem Phase error=5.6 degree phase error major problem Qintg = -10.2

ws s-plane s-plane Coarse View Fine View

s s

Example: 5th Order Elliptic Filter Singularities pushed Pole -ws towards RHP due to Zero integrator excess phase

Switched Capacitor Filter Build with DDI Integrator H ( jw) Passband Peaking SC DDI based Filter

Zeros lost!

fs /2 Frequencyfs (Hz) 2fs f Continuous-Time Prototype

C C f I I 1 f2 f1 f2 Vin Vin - f1 - f2

Cs Vo Cs Vo + +

DDI Integrator LDI Integrator

Sample output ½ clock cycle earlier

à Sample output on f2

Switched-Capacitor Integrator (n-3/2)Ts (n-1)T s (n-1/2)Ts nTs (n+1)Ts f Clock 1 f2 f1 f2 f1

Vin

F1 à Qs [(n-1)Ts]= Cs Vi [(n-1)Ts] , QI [(n-1)Ts] = QI[(n-3/2)Ts]

F2 à Qs [(n-1/2) Ts] = 0 , QI [(n-1/2) Ts] = QI [(n-3/2) Ts] + Qs [(n-1) Ts]

F1 _à Qs [nTs ] = Cs Vi [nTs ] , QI [nTs ] = QI[(n-1) Ts ] + Qs [(n-1) Ts]

F2 à Qs [(n+1/2) Ts] = 0 , QI [(n+1/2) Ts] = QI [(n-1/2) Ts] + Qs [n Ts]