A Switched-Capacitor Rf Power Amplifier 2979

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011 2977 A Switched-Capacitor RF Power Ampliﬁer Sang-Min Yoo , Member, IEEE , Jeffrey S. Walling , Senior Member, IEEE , Eum Chan Woo , Member, IEEE , Benjamin Jann, Member, IEEE , and David J. Allstot , Fellow, IEEE

Abstract—A fully integrated switched-capacitor power amplifier given output power. For high-output-power applications (e.g., (SCPA) utilizes switched-capacitor techniques in an EER/Polar 1 W), this comes at the cost of increased die area and architecture. It operates on the envelope of a nonconstant envelope resistive losses in the capacitive and inductive elements used in modulated signal as an RF-DAC in order to amplify the signal efficiently. The measured maximum output power and PAE are the impedance transformation network. 25.2 dBm and 45 %, respectively. When amplifying an 802.11g The demands placed on a CMOS PA in a modern high-speed 64-QAM orthogonal frequency-division multiplexing (OFDM) communication system are exacerbated by the use of noncon- signal, the measured error vector magnitude is 2.6% and the stant envelope (non-CE) modulation that increases spectral average output power and power-added efficiencies are 17.7 dBm efficiency by encoding information in both the phase and and 27%, respectively. amplitude domains (e.g., quadrature amplitude modulation Index Terms—Class-D, CMOS, envelope elimination and (QAM), orthogonal frequency division multiplexing (OFDM), restoration (EER), linearization, polar transmitter, power-added and quadrature phase shift keying (QPSK) with root-raised efficiency, power amplifiers, RF DAC, SCPA, switched-capacitor circuits. cosine filtering). This necessitates a PA that can process signals with large peak-to-average ratios (PARs). Although CMOS PAs may never provide the high output power and peak efficiency I. I NTRODUCTION levels achievable with expensive nonsilicon technologies, fully integrated solutions that operate with high average efficiency CALED CMOS technology is unique in its potential to can be competitive in many applications. S fully integrate single-chip radio systems because of its Because the PA is the dominant energy consumer in a most demonstrated ability to accurately and simultaneously process RF transceivers, high average efficiency is important because it analog, digital, and RF signals. Although many examples of leads to longer battery life and greater mobility for the user. This integrated radio subsystems for Bluetooth [1], WLAN [2]–[4], coupled with increased switching speed has stimulated interest and cellular telephone systems [5], [6] have been demonstrated, in more efficient switching PA circuits (e.g., Class-D [7], [8], the RF power amplifier (PA) has yet to be integrated in high -E [9]–[12], and -F [10], [13]), and systems that can be used to volume in such systems. It remains one of the most challenging operate them linearly for non-CE modulation. Pulsewidth mod- blocks to integrate because it must operate at a high output ulation (PWM) [8], [11], outphasing [7], [14], [15], and enve- power level with high energy efficiency and sufficient linearity lope elimination and restoration (EER) [9], [16], [17] are three to satisfy system specifications [e.g., margin-to-spectral mask, viable candidates that have been studied extensively for lin- error vector magnitude (EVM), and bit error rate (BER)]. earizing such switching PAs. All have significant drawbacks. In Although the additional challenge of coexistence of the RF PA the PWM architecture, the minimum output power that can be with sensitive transceiver circuits eventually must be consid- transmitted, and hence the dynamic range of the PA, is limited ered, only the ability to efficiently and linearly deliver power by the minimum pulsewidth that can be processed without pulse is considered herein. swallowing. Moreover, the period of the pulse is inversely pro- Scaling of the minimum feature size and power supply portional to frequency so the PWM PA also exhibits frequency voltage in CMOS technology in accordance with Moore’s Law dependence. The minimum output power of the outphasing PA has allowed MOSFETs to switch at higher speeds with lower is limited by load mismatches that occur for large outphasing an- dynamic power consumption. However, a lower operating gles. Another drawback of this architecture is the requirement voltage is problematic for an RF PA because it requires the for two PAs and an area-consuming passive power-combining use of a larger impedance transformation ratio to produce a network. The EER architecture performs best for small output amplitudes but it usually uses a separate analog supply modu- Manuscript received April 11, 2011; revised June 20, 2011; accepted July lator that requires large die area and draws significant bias cur- 22, 2011. Date of publication September 06, 2011; date of current version rent that reduces the overall energy efficiency. November 23, 2011. This paper was approved by Guest Editor Hooman Darabi. There has been considerable interest recently in the so-called S.-M. Yoo, E. C. Woo, and David J. Allstot are with the Department of Elec- trical Engineering, University of Washington, Seattle, WA 98195 USA (e-mail: digital PA (DPA) architecture, which uses an array of small [email protected]; [email protected]). unit-cell PAs that are conditionally connected in parallel ac- J. S. Walling is with the Department of Electrical Engineering, University of cording to a digital code word [6], [18], [19]. Some imple- Washington, Seattle, WA 98195 USA, and also with the Department of Elec- trical and Computer Engineering, Rutgers University, Piscataway, NJ 08854 mentations of this technique require a current cell design with USA. high output impedance for high accuracy and linearity. It is B. Jann is with the Intel Corporation, Hillsboro, OR 97124 USA. well known that standard design techniques (e.g., cascodes) in- Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. crease the required voltage headroom which reduces the overall Digital Object Identifier 10.1109/JSSC.2011.2163469 energy efficiency. Cascodes are advantageous, however, when

0018-9200/$26.00 © 2011 IEEE 2978 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011 used to distribute voltage stresses on individual devices to en- able operation with a higher power supply voltage [11], [20], [21]. Finally, because the transfer characteristic of the conventional DPA is approximately linear (saturated) for low (high) output power levels, extra bits of resolution (i.e., more unit-cell PAs) are needed when digital predistortion is used to enhance the overall linearity. In this paper, we introduce a DPA architecture that achieves output amplitude control by precisely control- ling charge transfer in a capacitor array. The switched-capacitor PA (SCPA) comprises an array of capacitors that are either switched at the RF carrier frequency between the supply voltage and ground or held at a signal ground, depending on a digital Fig. 1. Block diagram of an ideal single-ended SCPA. code word applied at the sampling rate that represents the amplitude of the envelope [22]. The SCPA technique does not suffer the same nonidealities as the conventional DPA but achieves high accuracy by exploiting the precision capacitance ratios that CMOS traditionally provides. Moreover, the technique eliminates auxiliary analog/mixed signal circuitry (e.g., no separate power supply modulator), scales easily depending on the resolution required for the chosen application, and, in contrast to most previous approaches, beneﬁts from CMOS technology scaling. The theory of operation for the SCPA is detailed in Section II. Circuit details and experimental results are presented in Sections III and IV, respectively, and conclusions are given in Section V. Fig. 2. Top-plate and output amplitudes versus switched and not switched capacitors.

II. THEORY OF OPERATION

A. Ideal Operation The switched-capacitor technique has been used in high-volume data conversion and mixed-signal processing applications for more than three decades [23]–[25]. SC circuits exploit capacitors, which are area-efficient, native devices in CMOS technologies, precision capacitor ratios realized using well-known design and layout techniques, and MOSFET switches. SC techniques are also ubiquitous in current state-of-the-art RF transceivers while continued CMOS scaling promises direct switching at RF frequencies in future Fig. 3. Thévenin equivalent circuit of the SC array seen from the matching systems. network. An SCPA comprises an array of precision capacitors and a bandpass matching network (Fig. 1). Depending on an applied digital code proportional to the amplitude of the envelope accordance with the total number of bits and the total array signal, selected bottom plates are switched at the RF carrier capacitance, frequency between and . Unselected capacitors are not switched but remain connected to a signal ground (1) (i.e., or . The total capacitance connected to the matching network remains constant because no top-plate is ever Another way to view this is to derive the Thévenin equiva- switched. The bandpass matching network filters the top-plate lent circuit for the general case shown in Fig. 3. The Thévenin voltage and transforms the impedance of the antenna from 50 voltage is the source voltage (e.g., scaled by , to 4 so that high output power can be generated. Note that where is the number of unit capacitors whose bottom plates the SCPA operates like a class-D PA with a capacitive voltage are switched between and and is the total number divider in series resonance with the matching network. of capacitors. The Thévenin impedance is just that of the total Digital logic driven by the code bits selects the capacitors capacitance at the top plate of the array. Again, note that the top- whose bottom plates are switched between and plate capacitance is constant versus envelope amplitude (i.e., and those held at or and not switched digital code); hence, the frequency response is fixed and the (Fig. 2). Thus, a square wave at the RF carrier frequency can bandpass matching network does not need to be tuned versus be generated at the top-plate terminal that is quantized in envelope amplitude. YOO et al. : A SWITCHED-CAPACITOR RF POWER AMPLIFIER 2979

Fig. 4. Equivalent circuit for the calculation of .

Fig. 5. Equivalent circuits for the calculation of . The inductor approx- imates a constant current source (i.e., an open circuit) during fast switching transitions.

B. Output Power and Efficiency Fig. 6. Comparison of ideal PAE versus for a conventional DPA and several SCPAs. To calculate the output power, the Thévenin equivalent circuit is connected in series with an inductor and resistor (Fig. 4). The inductor represents the excess reactive impedance Ideal power-added efficiency is defined as of the bandpass matching network and is the optimum termination resistance (e.g., ) for the desired output power (7) level. Because of the bandpass nature of the structure, only the fundamental component at the RF carrier frequency flows to the Substitution of (3)–(6) into (7) yields output:

(2) (8) where is the voltage switched at the bottom plates and is the first coefficient of the Fourier series. Thus, the output This important result is validated using Spectre RF behavioral power is simulations with ideal passive components and ahdl-modeled (3) switches. The versus output power characteristics for a conventional DPA and several SCPAs with different values are compared in Fig. 6. The ideal peak efficiency is 100% The dynamic power required to charge and discharge the in all cases. However, the PAE of the DPA rolls off as the square array is needed to compute the overall efficiency root of the output power [18], [19], whereas the SCPA designs (4) are more efficient at typical power backoff levels. An important conclusion is that the SCPA always offers higher PAE and av- where is the input capacitance driven through the selected erage efficiencies for typical modulation envelopes. switches and is the RF carrier frequency. An equivalent cir- Several additional losses should be considered to better esti- cuit model of this operation is shown in Fig. 5. If the switching mate the PAE of an SCPA: waveforms have sharp edges, it is reasonable to assume that the inductor, , behaves as a constant current source (i.e., an open (9) circuit) during the transition times. Therefore, is simply the series combination of the two capacitances where is an empirical attenuation factor associated with parasitic losses in the passive elements used in the matching net- (5) work, represents losses caused by the ON resistance of the switches, and , and are dynamic power losses Finally, the loaded quality factor of the network is defined as owing to the switch , switch driver , and clock dis- tribution network parasitics, respectively, and are de- (6) fined as

Although higher means less capacitance and dynamic (10) power loss, its maximum value is limited by the of the in- (11) ductor; typical on-chip values (e.g., 10–15) limit to –3 for fully integrated CMOS implementations. (12) 2980 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011

via an nMOS device. If , the charging networks are identical for the two circuits so no AM-PM distortion is generated. Because , in a typical design, the RC charging network of Fig. 8(a) is different than that of Fig. 8(b). As a consequence, envelope amplitude modulation is transferred to the time domain as a change in the phase modulation—AM–PM distortion. Similar effects are responsible for AM–AM distortion. The origin of AM–PM and AM–AM distortion can also be understood from Fig. 9(a) and the Thévenin equivalent circuit of Fig. 9(b), wherein is the effective source resistance seen from the output matching network. In the ideal case when , all of the available power is delivered from the source to the output load, i.e., there are no losses or nonlinear effects due to the switch resistances, and hence, no generation of AM–PM Fig. 7. Nonoverlapping clocks are used to mitigate crowbar currents. or AM–AM distortion. Moreover, there is no distortion when if it remains constant for different envelope amplitude codes. Several important observations follow from these equations. Imperfections that depend on the envelope amplitude code First, the losses are less at typical output power backoff levels and ultimately cause AM–PM and AM–AM distortion include (i.e., ) because fewer devices are switched. Fundamen- the following. tally, the PAE of the SCPA increases with CMOS technology • The source impedance depends on the envelope amplitude scaling because of the reduced capacitive parasitics. For higher code. The bottom-plate voltage is generated using a CMOS RF carrier frequencies, however, the requirement for wider switch for each selected capacitor; hence, changes with switches increases dynamic power consumption in the driver the selected number of bottom-plate CMOS switches. For chain which reduces PAE. A useful rule-of-thumb to minimize full amplitude operation, [Fig. 9(a)], all capacitor attenuation at the output is that the ON resistance of the switches bottom-plates are switched during every cycle of the RF should be much less than . Optimization is recommended carrier frequency so is the overall effective average ON in order to finalize the switch sizes. resistance of bottom-plate CMOS switches in parallel. Another power loss owes to the crowbar current that flows For smaller amplitudes, however, the unselected when series nMOS and pMOS devices both remain ON during capacitors are connected to and not switched. Now, switching transitions. Nonoverlapping clocks, wherein it is is the overall effective average ON resistance including guaranteed by timing that only one switch is ON during an the effects of the bottom-plate CMOS switches in parallel output transition, are commonly used to mitigate this problem and the bottom-plate nMOS devices connected (Fig. 7). Moreover, if the output matching network is designed in parallel to . Moreover, changes dynamically to appear slightly more inductive to the switches, lagging during the RF clock cycle; it involves nMOS devices current from the resonant tank partially charges or discharges during one half cycle and pMOS and nMOS the parasitic capacitances which reduces . devices during the other. • The effective value is also affected by the power C. AM–PM and AM–AM Distortion supply and ground line parasitics. • The switching times at the input and output of MOS tran- An SCPA does not suffer the same efficiency/linearity trade- sistors are nonzero. Hence, there is a brief period of very offs as a conventional DPA. An SCPA with ideal switches and high output impedance, compared to the ON resistance, capacitors is perfectly linear with no amplitude or phase distor- when neither device is completely ON during the output tion of the signal, i.e., the switching waveforms applied to the transition of a bottom-plate CMOS switch. This effect also bottom plates of selected capacitors are ideal square waves. alters depending on the number of capacitors selected In reality, of course, various imperfections that depend on the by the envelope amplitude code. envelope amplitude code alter the timing and shape of the wave- • Another interesting effect occurs during the nonoverlap- forms and give rise to AM–PM and AM–AM distortion. To gain ping period when both devices in the CMOS bottom-plate an intuitive understanding of this concept, consider the simple switches are OFF. During this brief interval, lagging cur- 2-b SCPA of Fig. 8(a), where the envelope amplitude code is rent that continues to flow from the matching network in- , and Fig. 8(b), where . Assume the teracts with various nonlinear parasitics associated with the pMOS and nMOS devices have constant ON resistances of CMOS switches. and , respectively, and neglect all other nonideal effects in- • All of the effects described above are exacerbated with the cluding parasitic capacitances, resistances, and nonlinearities. use of cascode pMOS and nMOS switches. First, there Based on the code bits, the bottom plate of each selected capac- are more nonlinear parasitic resistors and capacitors than itor is charged from to via a pMOS switch while in the simple CMOS switch. Second, it takes longer for the bottom plate of each unselected capacitor is connected to the cascode structure to switch which means more time YOO et al. : A SWITCHED-CAPACITOR RF POWER AMPLIFIER 2981

Fig. 8. A 2-b SCPA wherein selected bottom-plates are charged from to corresponding to envelope amplitude codes of (a) nax a I aR and (b) nax a Q aR.

Fig. 9. (a) An SCPA wherein the bottom-plates of n selected capacitors are switched between and by CMOS switches and the bottom-plates of @x nA unselected capacitors are not switched but connected to by nMOS switches. (b) A Thévenin equivalent circuit where r is the effective resistance seen from the output matching network, and (c) simulations of an SCPA illustrating the code-dependent origins of AM–PM and AM–AM distortion.

in the problematic output high-impedance state. Hence, III. CIRCUIT DETAILS the overall output impedance variation during a switching event is much greater than for a simple CMOS switch. A top-level schematic of a single-ended SCPA is shown in The nonideal switching effects described above cause the ef- Fig. 10. A CORDIC processor (not shown and not implemented fective source resistance to change dramatically and dynami- on chip) converts each Cartesian modulation symbol to an cally as a function of the envelope amplitude code. As a con- equivalent polar form and inputs the resulting phase (PM) and sequence, the delays and shapes of the switching waveforms envelope amplitude (AM) information to the SCPA. The PM change with amplitude [Fig. 9(c)] which causes AM–PM distor- component is upconverted to the RF carrier frequency to create tion. The impact of these effects is minimized by careful layout the phase input signal, . A clock generator converts into and circuit design techniques. AM–PM distortion is improved nonoverlapping differential switching waveforms, and , with CMOS scaling because of the smaller channel resistances that are applied to selected drivers to switch selected bottom and faster transition times between states. plates of the capacitor array. A digital code word, , which AM–AM distortion is caused by the same effects as above. It represents the AM component (i.e., a sampled value of the is small in an SCPA because of the excellent capacitor matching envelope amplitude) is also input to the SCPA. achievable in CMOS technologies and it should be reduced even System simulations predict that 6-b code words should more with scaling. provide sufﬁcient reconstruction accuracy to meet EVM and 2982 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011

Fig. 11. Bit-slice circuitry that selectively switches the bottom plate of one capacitor in the array.

Fig. 10. Top-level schematic of a single-ended SCPA; the actual implementa- tion is fully-differential. margin-to-spectral mask speciﬁcations for IEEE 802.11g Fig. 12. Microphotograph of the prototype SCPA in 90-nm CMOS. 64-QAM OFDM signals. The four MSBs, – , of are applied to a binary-to-thermometer decoder that selects the drivers and switches that are connected to the bottom plates of selected unary capacitors; likewise, the two LSBs – control bottom-plate switching for the binary-weighted capacitors. The digital circuits use static logic techniques to minimize power dissipation. The SCPA is designed in a 90-nm RF LP CMOS process with eight metal layers (including an ultrathick metal layer) and MIM capacitors, and laid out in a bit-slice format (Fig. 10) to facilitate scaling of the resolution. Circuit details are described in the next sections.

A. Output Matching Network Choosing the total array capacitance in an SCPA is important in the design of the output matching network because it has a significant impact on efficiency. To demonstrate this point, (3) is inverted at maximum (i.e., ) to find the termination Fig. 13. Measured output power and PAE versus frequency. resistance as maximum for and minimum for and . (13) Hence, is also parabolic with respect to the envelope amplitude. This effect on efficiency is important for signals with large Recall that – as limited by – of the peak-to-average ratios wherein midrange envelope amplitudes on-chip spiral inductors. With determined from (13), the are most probable. A practical design approach is to first choose total array capacitance is found from (6) to yield for maximum , and then optimize its value to achieve the highest average PAE for the probability density function of the (14) envelope amplitudes. The switching action of the SCPA generates high-order har- As described earlier, PAE is reduced by the dynamic power monics at the output of the capacitor array. An ideal bandpass required to charge and discharge the bottom plates of the se- matching network eliminates all such spurious content; in re- lected capacitors. Specifically, is proportional to the bottom- ality, the suppression of harmonics is limited by the finite plate capacitance that is switched, , which is determined by factor. For this reason, matching networks that effectively block the envelope amplitude code; is harmonic components are favored, i.e., networks with inductors YOO et al. : A SWITCHED-CAPACITOR RF POWER AMPLIFIER 2983

Fig. 14. Measured (a) versus envelope amplitude and (b) PAE versus .

Fig. 16. Measured INL and DNL. Fig. 15. Measured distortion versus input code. connected in series with the output (e.g., the tapped-inductor matching network of Fig. 10) are desirable.

B. Bit Slice Design Layout parasitic capacitances are minimized to reduce dynamic power losses and maximize efﬁciency. Hence, all top Fig. 17. Measurement setup for characterizing the dynamic performance of the plates are connected whereas the bottom plates are laid out in a SCPA. pitch-matched format for the bit-slice circuit shown in Fig. 11. This approach facilitates scaling of the resolution of the SCPA. The low used with nanometer CMOS technologies is switch drivers control the nMOS (PMOS) switches the main limitation on the peak output power of an SCPA. Re- that discharge (charge) the bottom plate of the selected capac- call from (3) that is increased either by increasing or itor. The cascoded switch topology of Fig. 11 allows the bottom- decreasing . However, only reducing to increase plate switches of the SCPA to operate from 0 to 2 and it is not a complete solution because losses in the matching net- minimizes the voltage stresses on individual devices [20]. The work are related to the ratio of the antenna impedance to ; nMOS and pMOS switches are sized for small ON resistances losses caused by power/ground line impedances are also signif- compared with and to switch the bottom plate of the se- icant. Hence, a technique that increases is desired. lected capacitor at the RF carrier frequency. A level-shifting cir- Consider the bit-slice circuitry of Fig. 11. It uses an envelope cuit is required in the pMOS switching path because the pMOS data bit and logic circuits to gate and into the cor- cascode operates between and . A detailed descrip- responding switch drivers. The nonoverlapping outputs of the tion of this circuit is given by Serneels et al. [20]. 2984 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011

Fig. 18. Measured dynamic output characteristics for IEEE 802.11g 64-QAM OFDM signals.

IV. E XPERIMENTAL RESULTS for 8.2 pF, , and ; these empirical constants were obtained The SCPA was fabricated in a 90-nm RF LP CMOS process from simulations of the extracted layout. Generally, the mea- with eight layers of metallization (including an ultrathick sured performance is in good agreement with the theoretical layer), and it occupies an area of 1.4 mm 0.7 mm including analysis. the bonding and probe pads, as shown in Fig. 12. It com- AM–AM and AM–PM distortion are measured to determine prises a 6-b array of precision MIM capacitors, six bit-slice the linearity of the SCPA and its suitability for digital predis- bottom-plate switching circuits, and a fully integrated output tortion. Predistortion is applied effectively only if the distor- matching network. All circuits operate from 1.5 V except for tion is predictable and mild so that post-predistortion changes the cascode bottom-plate switches which operate from 3 V. It is due to process, voltage, and temperature variations are min- clear from the microphotograph that additional bits for higher imal. Predistortion is suitable because the SCPA exhibits only a resolution are easily added with little area penalty. mild second-order nonlinearity (Fig. 15). Note that the AM–PM characteristic shows ripples for small envelope amplitudes. To A. Static Measurements a ﬁrst order, this effect is caused by switching binary-weighted, Measured and PAE for the maximum envelope ampli- rather than unary-weighted, LSB capacitors. Although the LSB tude are plotted in Fig. 13. was designed to be 2–3 as- bit slices were also designed to be binary-weighted to the degree suming values of 10–15 for the on-chip inductors. Fig. 13 possible, there are unavoidable differences that cause errors in gives a 3-dB bandwidth of about 1 GHz, in good agreement timing that manifest as AM-PM distortion. The AM–AM per- with . formance of the SCPA is superior because of the high precision Fig. 14(a) plots versus envelope amplitude code, and of capacitance ratios in CMOS processes. Fig. 14(b) depicts PAE versus . The peak is 25.2 dBm Because the SCPA is essentially an RF-DAC, the integral and the peak PAE is 45%. varies quadratically with enve- (INL) and differential (DNL) nonlinearity characteristics are lope amplitude as expected from (3), and the PAE rolls off with also measured. Excellent performance is achieved: INL is reduced as predicted from (8), (9), and Fig. 6. The theoret- less than 3 LSB and DNL is less than 0.5 LSB at ical and PAE performance characteristics are also shown 25.2 dBm, as shown in Fig. 16. These results are another YOO et al. : A SWITCHED-CAPACITOR RF POWER AMPLIFIER 2985

Fig. 19. Measured (a) far-out and (b) close-in output power spectral densities for IEEE 802.11g signals ampliﬁed by the SCPA.

TABLE I COMPARISON OF THE SCPA TO PRIOR-A RT CMOS POWER AMPLIFIERS

indication that robust predistortion can be used to improve performance is also observed in the demodulated constellation linearity. diagram (upper left) wherein the measured data points are close to their ideal locations. B. Dynamic Measurements As shown in Fig. 19, the measured PSD characteristics The dynamic performance of the SCPA is evaluated by in- violate the IEEE 802.11g spectral mask specifications. Because putting a non-CE modulated signal and measuring the spectral these violations are not systemic, however, several design op- mask and EVM relative to target specifications. For these mea- tions can mitigate problematic spectral impurities. The aliased surements, a predistorted IEEE 802.11g 64-QAM OFDM WiFi signals around the RF carrier frequency caused by sampling signal is applied to the PA using the measurement setup detailed the envelope at 160 MHz [Fig. 19(a)] are attenuated by the in Fig. 17. The predistortion is accomplished first by measuring sinc function associated with the zeroth-order hold; hence, the the static AM–AM and AM–PM distortion characteristics and aliased artifacts are reduced simply by increasing the sampling then subtracting the distortion from the original AM and PM frequency. The use of more sophisticated signal processing polar signal components. The AM (PM) signal is loaded into a techniques (e.g., a first-order hold function) also increases the digital pattern (vector signal) generator. The two signals are syn- attenuation of the aliased terms [18], [26]. Finally, the close-in chronized using the 10-MHz reference signal combined with the shoulder height [Fig. 19(b)] is reduced with better time align- trigger signal from the vector signal generator. A vector signal ment of the AM and PM components [27]. Mitigation of this analyzer downconverts the signal to baseband and demodulates measurement issue can be achieved by better synchronization it. of the independent AM and PM signal generators and by pro- Fig. 18 shows the measured EVM (lower right) and in-band cessing the signals closer to the chip interfaces. As a practical power spectrum (lower left). The measured EVM of 2.6%-rms matter, it is difficult to synchronize the signal generators with is well below the specification of 5.6% rms. Excellent EVM such wideband signal modulation. 2986 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011

An overall goal in using EER/Polar techniques is to increase [8] T.-P. Hung, J. Rode, L. E. Larson, and P. M. Asbeck, “Design the average PAE of the PA as of H-bridge class-D power amplifiers for digital pulse modulation transmitters,” IEEE Trans. Microw. Theory Tech. , vol. 55, no. 12, pp. 2845–2855, Dec. 2007. [9] P. Reynaert and M. S. J. Steyaert, “A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE,” IEEE J. Solid-State (14) Circuits, vol. 40, no. 12, pp. 2598–2608, Dec. 2005. [10] J. N. Kitchen, I. Deligoz, S. Kiaei, and B. Bakkaloglu, “Polar SiGe class E and F amplifiers using switch-mode supply modulation,” where and are the maximum and minimum envelope IEEE Trans. Microw. Theory Tech. , vol. 55, no. 5, pp. 845–856, voltages, respectively, and is the probability density func- May 2007. [11] J. S. Walling, H. Lakdawala, Y. Palaskas, A. Ravi, O. Degani, K. tion of the envelope of the modulated signal. While amplifying Soumyanath, and D. J. Allstot, “A class-E PA with pulse-width and IEEE 802.11g 64-QAM OFDM signals, the SCPA achieves an pulse-position modulation in 65 nm CMOS,” IEEE J. Solid-State average PAE of 27% with an average of 17.7 dBm. Circuits, vol. 44, no. 6, pp. 1668–1678, Jun. 2009. [12] M. Apostolidou, M. P. van der Heijden, D. M. W. Leenaerts, J. Sonsky, A. Heringa, and I. Volokhine, “A 65 nm CMOS V. C ONCLUSION 30 dBm class-E RF power amplifier with 60% PAE and 40% PAE at 16 dB back-off,” IEEE J. Solid-State Circuits , vol. 44, A switched-capacitor PA for EER/polar transmitters is de- no. 5, pp. 1372–1379, May 2009. scribed. Through the use of CMOS switches and capacitor ratios [13] S. Hamedi-Hagh and C. A. T. Salama, “CMOS wireless phase-shifted transmitter,” IEEE J. Solid-State Circuits , vol. 39, no. 8, pp. as precision elements, the SCPA achieves superior linearity and 1241–1242, Aug. 2004. efficiency performance. The theoretical operation is described [14] S. Moloudi, K. Takinami, M. Youssef, M. Mikhemar, and A. Abidi, and a design methodology is proposed. Unlike many previous “An outphasing power amplifier for a software-defined radio,” in ISSCC Dig. Tech. Papers , Feb. 2008, pp. 568–569. PA approaches, the linearity and efficiency characteristics are [15] H. Xu, Y. Palaskas, A. Ravi, and K. Soumyanath, “A highly improved using scaled CMOS processes because of the faster linear 25 dBm outphasing power amplifier in 32 nm CMOS switches with smaller parasitics. A prototype fabricated in a for WLAN application,” in Proc. IEEE Eur. Solid-State Circuits Conf., 2010, pp. 306–309. 90-nm CMOS process achieves peak and PAE values of [16] F. Wang, D. F. Kimball, J. D. Popp, A. H. Yang, D. Y. Lie, P. M. 25.2 dBm and 45%, respectively. The potential to function Asbeck, and L. E. Larson, “An improved power-added efficiency as part of an EER transmitter is validated by applying IEEE 19-dBm hybrid envelope elimination and restoration power amplifier for 802.11g WLAN applications,” IEEE Trans. Microw. Theory Tech. , 802.11g 64-QAM OFDM signals; excellent EVM (2.6%-rms) vol. 54, no. 12, pp. 4086–4099, Dec. 2006. and average PAE performance (27%) is achieved. The SCPA is [17] J. S. Walling, S. S. Taylor, and D. J. Allstot, “A class-G supply-modu- compared to other recent CMOS PAs in Table I. lator and class-E PA in 130 nm CMOS,” IEEE J. Solid-State Circuits , vol. 44, no. 9, pp. 2339–2347, Sep. 2009. [18] A. Kavousian, D. K. Su, M. Hekmat, A. Shirvani, and B. A. Wooley, ACKNOWLEDGMENT “A digitally modulated polar CMOS power amplifier with a 20-MHz channel bandwidth,” IEEE J. Solid-State Circuits , vol. 43, no. 10, pp. The authors would like to thank Intel Corporation for valuable 2251–2258, Oct. 2008. measurement assistance. [19] C. D. Presti, F. Carrara, A. Scuderi, P. M. Asbeck, and G. Palmisano, “A 25 dBm digitally modulated CMOS power amplifier for WCDMA/ EDGE/OFDM with adaptive digital predistortion and efficient power EFERENCES R control,” IEEE J. Solid-State Circuits , vol. 44, no. 7, pp. 1883–1896, [1] W. W. Si, D. Weber, S. Abdollahi-Alibeik, M. Lee, R. Chang, H. Jul. 2009. Dogan, H. Gan, Y. Rajavi, S. Luschas, S. Ozgur, P. Husted, and M. [20] B. Serneels, M. Steyaert, and W. Dehaene, “A 5.5 V SOPA line driver Zargari, “A single-chip CMOS Bluetooth v2.1 radio SoC,” IEEE J. in a standard 1.2 V 0.13 mm CMOS technology,” in Proc. IEEE Eur. Solid-State Circuits, vol. 43, no. 12, pp. 2896–2904, Dec. 2008. Solid-State Circuits Conf., 2005, pp. 303–306. [2] I. Vassiliou, K. Vavelidis, T. Georgantas, S. Plevridis, N. Haralabidis, [21] D. Chowdhury, L. Ye, E. Alon, and A. M. Niknejad, “A 2.4 GHz mixed- G. Kamoulakos, C. Kapnistis, S. Kavadias, Y. Kokolakis, P. Merakos, signal polar power amplifier with low-power integrated filtering in 65 J. C. Rudell, A. Yamanaka, S. Bouras, and I. Bouras, “A single-chip nm CMOS,” in IEEE Custom Int. Circuits Conf. Dig. Tech. Papers , digitally calibrated 5.15–5.825-GHz 0.18-um CMOS transceiver for 2010, pp. 1–4. 802.11a wireless LAN,” IEEE J. Solid-State Circuits , vol. 38, no. 2, [22] S.-M. Yoo, J. S. Walling, E. C. Woo, and D. J. Allstot, “A switched- pp. 2221–2231, Dec. 2003. capacitor power amplifier for EER/polar transmitters,” in IEEE ISSCC [3] P. Zhang, L. Der, D. Guo, I. Sever, T. Bourdi, C. Lam, A. Zolfaghari, Dig. Tech. Papers , 2011, pp. 428–429. J. Chen, D. Gambetta, B. Cheng, S. Gowder, S. Hart, L. Huynh, T. [23] R. Suarez, P. R. Gray, and D. Hodges, “An all-MOS charge-redistri- Nguyen, and B. Razavi, “A single-chip dual-band direct-conversion bution A/D conversion technique,” in IEEE ISSCC Dig. Tech. Papers , IEEE 802.11a/b/g WLAN transceiver in 0.18-um CMOS,” IEEE J. 1974, pp. 194–195. Solid-State Circuits, vol. 40, no. 9, pp. 1932–1939, Sep. 2005. [24] D. J. Allstot, R. W. Broderson, and P. R. Gray, “MOS switched capac- [4] S. S. Mehta, D. Weber, M. Terrovitis, K. Onodera, M. P. Mack, B. J. itor ladder filters,” IEEE J. Solid-State Circuits , vol. SSC-13, no. 6, pp. Kaczynski, H. Samavati, S. H.-M. Jen, W. W. Si, M. Lee, K. Singh, S. 806–814, Dec. 1978. Mendis, P. J. Husted, N. Zhang, B. McFarland, D. K. Su, T. H. Meng, [25] S.-M. Yoo, J.-B. Park, H.-S. Yang, H.-H. Bae, K.-H. Moon, and B. A. Wooley, “An 802.11g WLAN SoC,” IEEE J. Solid-State Cir- H.-J. Park, S.-H. Lee, and J.-H. Kim, “A 10 b 150 MS/s cuits, vol. 40, no. 12, pp. 2483–2491, Dec. 2005. 123 mW 0.18 um CMOS pipelined ADC,” in IEEE ISSCC [5] P. Cruise, C.-M. Hung, R. B. Staszewski, O. Eliezer, S. Rezeq, K. Dig. Tech. Papers , 2003, pp. 326–327. Maggio, and D. Leipold, “A digital-to-RF-amplitude converter for [26] Y. Zhou and J. Yuan, “A 10-bit wideband CMOS direct digital RF GSM/GPRS/EDGE in 90-nm digital CMOS,” in Proc. IEEE Radio amplitude modulator,” IEEE J. Solid-State Circuits , vol. 38, no. 7, pp. Frequency Integrated Circuits (RFIC) Symp. , 2005, pp. 21–24. 1182–1188, Jul. 2003. [6] R. Staszewski, R. B. Staszewski, T. Jung, T. Murphy, I. Bashir, O. [27] D. Rudolph, “Kahn EER technique with single-carrier digital modula- Eliezer, K. Muhammad, and M. Entezari, “Software assisted digital RF tions,” IEEE Trans. Microw. Theory Tech. , vol. 51, no. 2, pp. 548–552, processor (DRP) for single-chip GSM radio in 90 nm CMOS,” IEEE J. Feb. 2003. Solid-State Circuits, vol. 45, no. 2, pp. 276–288, Feb. 2010. [28] D. Chowdhury, C. D. Hull, O. B. Degani, P. Goyal, Y. Wang, and A. [7] T.-P. Hung, D. K. Choi, L. E. Larson, and P. M. Asbeck, “CMOS out- M. Niknejad, “A single-chip highly linear 2.4 GHz 30 dBm power am- phasing class-D amplifier with Chireix combiner,” IEEE Microw. Wire- plifier in 90 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers , 2009, pp. less Compon. Lett., vol. 17, no. 8, pp. 619–621, Aug. 2007. 378–379. YOO et al. : A SWITCHED-CAPACITOR RF POWER AMPLIFIER 2987

Sang-Min Yoo (M’11) received the B.S and M.S. de- Benjamin Jann (M’05) received the B.S. and M.S. grees from Sogang University, Seoul, Korea, in 2000 degrees in electrical engineering from Oregon State and 2002, respectively, and the Ph.D. degree in elec- University, Corvallis, in 2000 and 2005, respectively. trical engineering from the University of Washington, From 2000 to 2002, he was with Network Ele- Seattle, in 2011. ments Inc., designing optical transceiver modules. From 2002 to 2007, he was with Samsung Elec- In 2005, he joined the Mobile Wireless Group, Intel tronics, Yongin, Korea, where he designed data con- Corporation, Hillsboro, OR, where he is currently an verters and baseband analog circuits. He held intern- RFIC Design Engineer. ship position at Mobile Wireless Group at Intel, Hills- boro, OR, from 2010 to 2011, where he was involved with the design of high-efficiency transmitter. His research interest includes RF and analog/mixed-signal circuits. Dr. Yoo was the recipient of the Analog Devices Outstanding Student De- signer Award in 2009. David J. Allstot (S’72–M’72–SM’83–F’92) received the B.S. degree from the University of Portland, Oregon, the M.S. degree from Oregon State University, Corvallis, and the Ph.D. degree Jeffrey S. Walling (SM’11) received the B.S. degree from the University of California, Berkeley. from the University of South Florida, Tampa, in 2000, He has held several industrial and academic and the M.S. and Ph.D. degrees from the University positions and has been the Boeing-Egtvedt Chair of Washington, Seattle, in 2005 and 2008, respec- Professor of Engineering at the University of Wash- tively. ington since 1999. He was Chair of the Department Prior to starting his graduate education, he was of Electrical Engineering from 2004 to 2007. He with Motorola, Plantation, FL working in cellular is currently on sabbatical as a Visiting Professor of handset development. He interned for Intel, Hills- Electrical Engineering with Stanford University, Stanford, CA. He has advised boro, OR, from 2006 to 2007, where he worked on approximately 100 M.S. and Ph.D. graduates and published about 300 papers. highly digital transmitter architectures and CMOS Dr. Allstot was the recipient of several awards for outstanding teaching and power amplifiers. He is currently an Assistant graduate advising. Awards include the 1980 IEEE W.R.G. Baker Award, the Professor with Rutgers, The State University of New Jersey, Piscataway, NJ. 1995 and 2010 IEEE Circuits and Systems Society (CASS) Darlington Award, His current research interests include low-power wireless circuits, energy 1998 IEEE International Solid-State Circuits Conference (ISSCC) Beatrice scavenging, high-efficiency transmitter architectures, and CMOS power ampli- Winner Award, 1999 IEEE CASS Golden Jubilee Medal, 2004 IEEE CASS fier design. He has authored or coauthored over 20 articles in peer-reviewed Technical Achievement Award, 2005 Semiconductor Research Corporation journals and refereed conferences. Aristotle Award, 2008 Semiconductor Industries Assoc. University Research Dr. Walling received the Yang Award for outstanding graduate research from Award, and 2011 IEEE CASS Mac Van Valkenburg Award. His service the University of Washington, Department of Electrical Engineering, in 2008, includes: 1990–1995 Associate Editor and Editor of IEEE TCAS, 1990–1993 an Intel Predoctoral Fellowship in 2007–2008, and the Analog Devices Out- Member of Technical Program Committee of the IEEE Custom IC Conference, standing Student Designer Award in 2006. 1992–1995 Member, Board of Governors of IEEE CASS, 1994–2004 Member, Technical Program Committee, IEEE ISSCC, 1996–2000 Member, Executive Committee of IEEE ISSCC, 1996–2000 Short Course Chair of IEEE ISSCC, 2000–2001 Distinguished Lecturer, IEEE CASS, 2001 and 2008 Co-General Eum Chan Woo (M’09) received the B.S. and M.S. Chair of IEEE ISCAS, 2006–2007 Distinguished Lecturer, IEEE Solid-State degrees in electronics from Changwon National Circuits Society, and 2009 President of IEEE CASS. University, Changwan, South Korea, in 2005 and 2007, respectively, and the M.S. degree in electrical engineering from University of Washington, Seattle, in 2009. His research and thesis focused on analog/mixed signal/RF CMOS integrated circuit design. He has authored or coauthored a number of publications on RF/mixed signal circuits as well as memory circuit design. From 2009 to 2011, he was with Telegent Systems, Sunnyvale, CA, working on free-to-air analog/digital mobile TV receiver circuits. Currently he is with Broadcom Corporation, Sunnyvale, CA. His research interests include integrated CMOS RF/wireless communication circuit design.