DYNAMICALLY RECONFIGURABLE ANALOG/DIGITAL HARDWARE - IMPLEMENTATION USING FPGA AND FPAA TECHNOLOGIES

Cornel Reiser1, Lech Znamirowski 2, Olgierd A. Palusinski 3, Sarma B.K.Vrudhula3, Daler Rakhmatov3 1 Institut fuer Theoretische Elektrotechnik, University of Karlsruhe, 76128 Karlsruhe, Germany E-mail: [email protected] 2 Instytut Informatyki, Technical University of Silesia, Ul. Akademicka 16, 44-100 Gliwice, Poland E-mail: [email protected] 3 Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721, USA E-mail: [email protected]

KEYWORDS the operations is not critical. Analog circuits offer advantages in applications where signal frequencies are Reconfigurable hardware, mixed-signal circuits, adaptive high and low power dissipation is essential. However, the filtering, analog and digital arrays. accuracy of analog circuits is limited and they can not be used to implement algorithms of high complexity. Consequently, processing in a large system is assigned ABSTRACT accordingly to analog and digital circuits to take advantage of specific circuit properties for overall performance In this paper we present a dynamically reconfigurable optimization, such as power minimization. If the processing mixed-signal circuit using the new technology of Field requirements and algorithms change over time, the optimal Programmable Analog Arrays (FPAA) combined with assignment of processing functions may change and existing well established technology of Field dynamic reassignment of functions and reconfiguration of Programmable Gate Arrays (FPGA). A FPAA can be used circuits may be necessary. The new technology of Field to build filters for analog signals as well as other kinds of Programmable Analog Arrays (FPAA) in combination with analog applications implemented in switched capacitor the well known technology of Field Programmable Gate technology (S/C-technology). The experiment described in Arrays (FPGA) provides a basis for the development of a this paper takes advantage of performance and dynamically reconfigurable analog/digital hardware. Such a programmability of the FPAA for filtering of an analog mixed-signal circuit is very suitable for applications in signal controlled by a digital system. Investigations of such mobile systems such as cell phones and other portable a hardware in application to adaptive signal filtering and telecommunication systems in general, because of the process control are in progress. The paper will present opportunity for reducing power dissipation through proper results of work on adaptive filtering with dynamic assignment of hardware processing functions to analog and reconfiguration based on 2 parallel FPAA chips digital circuits. cooperating with a digital control system. Theoretical studies and measurements of transition behavior of the switching process between the 2 FPAA chips and analysis THE FIELD PROGRAMMABLE ANALOG of limitations imposed by hardware imperfections will be ARRAY (FPAA) presented. The experimental system is an excellent vehicle to learn about intricacies in performance of mixed-signal A Field Programmable Analog Array (FPAA), built in circuits and is used for verification of theoretical CMOS technology, contains uncommitted operational predictions as well as for model modifications. amplifiers, switches, and banks of programmable switched capacitors (S/C) and can be used to build filters for analog signals as well as a large number of diverse analog INTRODUCTION applications. The parameters of a given application, such as a filter, are functions of the capacitor values. The chip is Digital circuits can be applied to implement high- divided into 20 identical, configurable analog blocks accuracy and high-complexity signal processing algorithms (CABs), each composed of an operational amplifier, five for low frequency signals where power dissipated during capacitor banks, and switches that can be used to interconnect the cell components and determine their Each macro is a pre-configured sub-circuit such as a operation. There are both static and dynamic CMOS gain-stage, filter, full-wave rectifier, or biquad, just to switches. The static switches are used to determine the mention some examples. Several macros can be placed configuration of cell components and inter-cell onto the chip and “wired” together as required by an connections. These switch settings are determined once application. There are also some “pre-wired” application during the programming phase of an application after which circuits, stored in a library, which can be selected and they remain unchanged. The dynamic switches are placed on the chip. Parameters of the library components associated with capacitors and are switched periodically can be selected and changed, as needed in the application, during the circuit operation changing the effective function using pull-down menus and pop-up windows. (Birk 1998; of capacitors as typically exploited in switched capacitor Palusinski et al. 1998) (S/C) circuits. Both static and dynamic switches are The FPAA technology is suitable for numerous electronically controlled and thus the functionality of each engineering applications like electrical signal filtering, CAB, the capacitor sizes, and the interconnections between construction of controllers and phase correctors for CABs are programmable. As a result many diverse circuit continuous and sampled data feedback systems, architectures can be implemented. conditioning of sensor signals and signal generation. The The FPAA used in this study is Motorola’s MPAA020 power of the FPAA is that it can be reconfigured “on the which contains 41 operational amplifiers, 100 fly” to implement different device or parameter settings programmable capacitors, 6864 electronic switches and that’s why the chip is so suitable for dynamic arranged into the 20 CABs, and 13 input/output buffers. The reconfiguration as it is demonstrated in the experimental array is structured in a grid that contains the 20 CABs investigations presented in this paper. arranged in a 4x5 matrix. Configuring an analog design within the array is performed by downloading 6K bits of data via RS232 communications from a PC or EPROM. SYSTEM DESCRIPTION The data stream contains information to configure the individual cells, the cell to cell interconnections, internal The basic concept of reconfigurable hardware is voltage reference as well as the input and output illustrated here using 2 parallel FPAAs which are being connections. During the configuration download process switched by a multiplexer. A digital system controls the all cells are placed in a power-down mode to protect the switching and provides communication to the FPAAs in CABs against undesirable high currents. The switches allow control of reconfiguration. At the moment all the control is control over the circuit connectivity and capacitor values in done by a PC and the software EasyAnalogä , but future addition to other features. implementations will use a FPGA. Future plans also include The complexity of control is so high that a supporting digitization of the analog signal input and output to the software was developed to facilitate the chip programming. FPGA in order to implement a digital feedback loop for The software allows a user to easily manipulate these field- comparison and control of the filter behavior. The control programmable switches in order to implement a specific signal for the multiplexer is generated on the FPAA during circuit. The chip programming software is called the programming phase. So when the FPAA starts to work EasyAnalogä and runs under Windows 3.1, Windows 95, after reconfiguration a high peak appears that enters into an and Windows NT operating systems. The basic interface adjustable time delay circuit on the control board and then window of EasyAnalogä displays a simplified view of 20 to the multiplexer in order to interchange the analog CABs, 13 I/O isolation amplifiers, and inter-cell outputs of the FPAAs. The block diagram of the system is connecting lines. With a “point and click” action the user shown in Figure-1. can select and place “macros” from a function library onto the chip in any feasible cell location. Digital Input Digital Feed Back PC/FPGA

Download

ADC Control 1 ADC FPAA 1 IN 1

Control Analog Input Board Analog Output

IN 2 FPAA 2

Control 2 Figure-1 Block diagram of the system composed of 2 parallel FPAAs In this system one FPAA can filter the analog input A delicate aspect of the dynamic reconfiguration is the signal while the other one is ‘off-line’ waiting for transition behavior of the switching from one FPAA to the reprogramming and subsequent switching to the on-line other. After the FPAA is reprogrammed it cannot be put mode by the multiplexer after which time the first FPAA immediately “on-line” because the signal needs some time can then be reprogrammed and prepared for future on-line to settle and reach a steady state. That’s why it is necessary filtering. This system provides a steady output signal to provide a time delay between the end of the without an interruption when there’s a need for redefinition programming phase and the actual physical switching. of the analog filter function. The described process is illustrated in Figure-2.

switching moment switching moment FPAA1

filtering signal off-line programming filtering signal

t

FPAA2

off-line filtering signal programming off-line programming

t

Output

t switching delay switching delay Figure-2 Timing diagram of reprogramming and filtering of 2 parallel FPAAs for uninterrupted processing of an analog input signal. We shall analyze this circuit using sinusoidal analog 2 2pf 0 2 2 input signals as this will demonstrate of how switching s + s + 4p f = 0 Q 0 (3) between the two FPAAs is carried out. For example if one changes the quality factor of a low-pass filter and switches For the unit-step input and the Laplace inversion obtained at the peak of the output signal there will be a jump in the the output time response is given by (Nagrath 1975) 2pf output as illustrated in Figure-3. Such a jump should be R - 0 t avoided because it causes an injection of high frequency | e 2Q h(t) = G 1- * components. For this reason it is necessary to switch at the S 1 | (1- 4Q2) zero crossing of the sinusoidal signal to avoid undesirable T jumps of the amplitude. However, if the corner frequency of the filter or the whole filter in general will be changed, sinL2pf (1- 1 )t + tan -1 (4Q2 -1)OU (4) M 0 4Q2 PV one has to deal with discontinuities in the amplitude as well N QW as a phase shift. The steady-state value of h(t) is given as

hss = lim h(t) = G t®¥ (5) It can be observed that the time response h(t) oscillates between a pair of envelopes before reaching steady-state for Q>0.5. The transient is comprised of a product of an 2pf - 0 t exponentially decaying term e 2Q and a sinusoidally

1 -1 2 oscillating term sin 2pf0 (1- 4Q 2 )t + tan (4Q -1) . Q The time constant of the exponential envelope is T = . pf0 The settling time t is defined as the time period the signal Figure-3 High pass filter switching from Q=20 to s Q=0.5 after time delay needs to get within a certain tolerance band around the steady-state value and stays within these bounds. To properly control the switching of the system it is Considering only the exponentially decaying envelope for a necessary to investigate the system transitions in order to tolerance band of 1% the settling time is given by determine the settling time which would allow a selection pf0 - ts of appropriate time delay. e Q = 0.01 (6) 1 (1- 4Q2 )

ND pf 0 SETTLING TIME OF SYSTEMS OF 2 - t s For Q>>0.5 we have e Q » 0.01 . ORDER This yields the settling time t The analysis presented here is applicable to any second- s order system (biquad). The transfer function of a low pass biquad is 4.605Q ts = (7) 2 2 pf0 4p f0 G Hlow pass (s) = - 2pf 2 s2 + 0 s + 4p 2 f (1) Q 0 This formula (7) is applicable for all biquad filters. where G is the pass-band gain (DC-Gain), Q is the quality factor, and f0 is the corner frequency of the filter. The time response of this system is characterized by the roots MEASUREMENTS OF SETTLING TIME of the denominator polynomial q(s), which in fact are the poles of the transfer function. The denominator polynomial The measurements were performed to verify the q(s) is therefore called the characteristic polynomial and analytical results and to demonstrate that the described q(s) = 0 (2) settling behavior is observable for an input step function as well as sinusoidal signals. A constant pass-band gain of is called the characteristic equation. The characteristic G=1 was used in all measurements. equation of the system under consideration is An example of a measurement performed to determine The relative error between the calculated and the linear a settling time in the system is given in Figure-4. fit of this measured values is 2.05% and is mainly caused by reading errors of the oscilloscope because of the low resolution. The errors of other filter measurements are shown in Table-1.

The settling behavior of biquad filters for various quality factors and corner frequencies are shown in Figure-6. Inspection of the graph indicates that the settling time increases significantly for very low corner frequencies and follows linearly with increasing quality factor. This means that one has to switch with a long time delay for filters with low corner frequency and high quality factor in order to avoid perturbations. Figure-4 Settling behavior of band pass filter after Title: /home/cornel/matlab/plots/HQ3D_lf_plot.eps switching Creator: MATLAB, The Mathworks, Inc. CreationDate: 10/02/98 17:03:39 Cumulative results of measurements of the settling time as a function of the biquad quality factor are shown in Figure-5. The plot shows that the behavior of a high pass biquad filter (high Q) with corner frequency of 25 kHz follows the analysis presented here. For linearization of the distributed measured values the method of linear regression was used (Allen and Holberg 1975).

Title: /home/cornel/matlab/plots/HPHQ25_linR_plot.eps Creator: MATLAB, The Mathworks, Inc. CreationDate: 10/23/98 11:55:42

Figure-6 Settling time behavior versus quality factor and corner frequency During various measurements it was observed that for both inputs, step function and sinusoidal signal, the output is wedged into the exponential envelope described before. This means that the measured settling time of a step input is also the time period within which the sinusoidal signal settles in.

Figure-5 Settling behavior of high pass filter at corner frequency of 25 kHz

Table-1 Relative errors of the measured settling time of various filters Filter high pass band stop band pass band pass low pass Corner frequency 100 kHz 50 kHz 50 kHz 10 kHz 25 kHz Relative error 0.55% 1.35% 1.46% 3.42% 6.32% CASCADING BIQUADS systems show also the analogous behavior of the settling time with respect to changes of the characteristic values, For filters of higher order it is also necessary to the corner frequency and the quality factor, to that of a investigate the settling behavior. In a simple experiment we biquad filter. investigated how the chip behaves when identical biquads with known settling time are cascaded. All the cascaded (2 up to 10) biquads are identical with the same corner ACKNOWLEDGEMENTS frequency and quality factor. The cumulative results are shown in Figure-7. This work was carried out at the Center for Low Power Electronics which is supported by the National Science Title: /home/cornel/matlab/plots/Cas2Q1_plot.eps Foundation, the Department of Commerce of the State of Creator: MATLAB, The Mathworks, Inc. Arizona, and companies in the microelectronics industry, CreationDate: 10/09/98 11:54:31 including Ambit, Analog Devices, Analogy, Burr Brown, Gain Technology, Intel, InterHDL, Microchip, Motorola, Raytheon, Rockwell, Texas Instruments, and Western Design.

REFERENCES

Allen, P.E. and D.R. Holberg. 1975. CMOS Analog Circuit Design, Oxford University Press, New York

Birk, C. 1998. “Evaluation of Filters implemented using a Field Programmable Analog Array”,WMC’98 - ICSEE, San Diego, California, Jan. 11-14, 1998.

Figure-7 Settling behavior of identical cascaded high Nagrath, I.J. 1975. Control systems engineering, John pass biquad filters versus corner frequency. Wiley & Sons, New York Additional measurements with different quality factors showed the same result with regard to the shape of the Palusinski, O.A.; D.M. Gettman; D. Anderson; H. Anderson; curve. It can be easily observed that the settling time of the C. Marcjan. “Filtering applications of Field Programmable entire circuit follows the reciprocal value of the corner . Journal of Circuits, Systems and frequency. This is analogous to the theoretical and Computers. World Scientific Pub, Oct. 1998 (in print). measured results for the settling time of a particular biquad shown in the previous sections.

SUMMARY

This paper presents a model for dynamic reconfiguration of analog filters using 2 parallel Field Programmable Analog Arrays controlled by a digital system and switched by a multiplexer. Performance imperfections caused by the switching process are discussed. In order to determine a certain time delay to “hide” these perturbations, analytical investigations about settling behavior of filters of 2nd order were done and compared to measured values. It is shown that this theoretical rule can be used for determination of the time delay for optimization of the transition behavior switching from one FPAA to another. Measurements of cascaded