Cmos Logic Circuit Design Cmos Logic Circuit Design

CMOS LOGIC CIRCUIT DESIGN CMOS LOGIC CIRCUIT DESIGN

John P. Uyemura Georgia Institute of Technology

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This book is dedicated to

Christine and Valerie

for all of the joy and happiness that they bring into my life Preface

This book is based on the earlier Kluwer title Circuit Design for CMOS/VLSI which was published in 1992. At that time, CMOS was just entering the main- stream as a technique for high-speed, high-density logic circuits. Although the technology had been invented in the 1960’s, it was still necessary to include Sec- tion 1.1 entitled Why CMOS? to justify a book on the subject. Since that time, CMOS has matured and taken its place as the primary technology for VLSI and ULSI digital circuits. It therefore seemed appropriate to update the book and gen- erate a second edition. Background of the Book

After loading the old files and studying the content of the earlier book, it became clear to me that the field is much more stable and well-defined than it was in the early 1990’s. True, technological advances continue to make CMOS better and better, but the general foundations of modern digital circuit design have not changed much in the past few years. New logic circuit techniques appearing in the literature are based on well-established ideas, indicating that CMOS has matured. As a result of this observation, the great majority of the old files were abandoned and replaced with expanded discussions and new topics, and the book was reorganized to the form described below. There are sections that didn’t change much. For example, Chapter 1 (which introduces MOSFETs) includes more derivations and pedagogical material, but the theme is about the same. But, many items are significantly different. For example, the earlier book contained about 60 pages on dynamic logic circuits. The present volume has almost three times the number of pages dedicated to this important area. In addition, the book has been written with more of a textbook flavor and includes problem sets. Contents Chapter 1 introduces the MOS system and uses the gradual-channel approximation to derive the square-law equations and basic FET models. This sets the notation for the rest of the book. Bulk- charge models are also discussed, and the last part of the chapter introduces topics from small- device theory, such as scaling and hot electrons. viii

Chapter 2 is an overview of silicon fabrication and topics relevant to a CMOS process flow. Basic ideas in lithography and pattern transfer are covered, as are items such as design rules, FET sizing, isolation, and latch-up. This chapter can be skipped in a first reading, but it is important to understanding some problems that are specific to layout and fabrication issues. It is not meant to replace a dedicated course in the subject. Circuit design starts in Chapter 3, which is a detailed analysis of the static CMOS inverter. The study is used to set the stage for all of the remaining chapters by defining important DC quantities, transient times, and introducing CMOS circuit analysis techniques. Chapter 4 concentrates on a detailed study of the electrical characteristics of FETs when used as voltage-controlled electronic switches. In particular, the treatment is structured to emphasize the strong and weak points of nFETs and pFETs, and how both are used to create logic networks. This feeds into Chapter 5, which is devoted entirely to static logic gates. This includes fully complementary designs in addition to variants such as pseudo-nMOS circuits and novel XOR/XNOR networks. Chapter 6 on transmission gate logic completes this part of the book. Dynamic circuit concepts are introduced in Chapter 7. This chapter includes topics such as charge sharing and charge leakage in various types of CMOS circuit arrangements. RC modelling is introduced, and the Elmore formulas for the time constant of an RC ladder is derived. Clocks are introduced and used in various types of clocked static and dynamic circuits. Dynamic logic families are presented in Chapter 8. The discussion includes detailed treatments of precharge/evaluate rip- ple logic, domino logic cascades, self-resetting logic gates, single-phase circuits and others. I have tried to present the material in an order that demonstrates how the techniques were developed to solve specific problems. Chapter 9 deals with differential dual-rail logic families such as CVSL and CPL with short overviews of related design styles. The material in Chapter 10 is concerned with selected topics in chip design, such as interconnect modelling and delays, crosstalk, BSD-protected input circuits, and the effects of transmission lines on output drivers. The level of the presentation in this chapter is reasonably high, but the topics are complex enough so that the discussions only graze the surface. It would take another volume (at least) to do justice to these problems. As such, the chapter was included to serve as an introduc- tion for other courses or readings. Use as a Text There is more than enough material in the book for a 1-semester or 2-quarter sequence at the senior undergraduate or the first-year graduate level. The text itself is structured around a first-year graduate course entitled Digital MOS Integrated Circuits that is taught at Georgia Tech every year. The course culminates with each student completing an individual design project. My objectives in developing the course material are two-fold. First, I want the students to be able to read relevant articles in the IEEE Journal of Solid-State Circuits with a reasonable level of comprehension by the end of the course. The second objective is more pragmatic. I attempt to structure the content and depth of the presentation to the point where the students can answer all of the questions posed in their job interviews and plant visits, and secure positions as chip designers after graduation. Moreover, I try to merge basics with current design techniques so that they can function in their positions with only a minimum amount of start-up time. Problem sets have been provided at the end of every chapter (except Chapter 2). The questions are based on the material emphasized in the chapter, and most of them are calculational in nature. Process parameters have been provided, but these can easily be replaced by different sets that might be of special interest. Most of the problems have appeared on my homeworks or exams; others are questions that I wrote, but never got around to using for one reason or another. I have tried to include a reasonable number of problems without getting excessive. Students that can follow the level of detail used in the book should not have many problems applying the material. SPICE sim- ulations add a lot to understanding, and should be performed whenever possible. ix Apologies

No effort was made to include a detailed list of references in the final version of the book. I initially set out to compile a comprehensive bibliography. However, after several graduate students performed on-line literature searches that yielded results far more complete than my list, I decided to include only a minimal set here. The references that were chosen are books and a few papers whose contents are directly referenced in the writing. The task is thus left to the interested reader. I have tried very hard to eliminate the errors in the book, but realize that many will slip through. After completing six readings of the final manuscript, I think that I caught most of the major errors and hope that the remaining ones are relatively minor in nature. I apologize in advance for those I missed. Acknowledgments

Many thanks are due to Carl Harris of Kluwer who has shown amazing patience in waiting for this project to be completed. He never seemed to lose hope, even when I was quite ill (and crabby) for several months and unable to do much. Of course, those who know Carl will agree with me that he is a true gentlemen with exceptional qualities. And a real nice guy. Dr. Roger P. Webb, Chair of the School of Electrical & Computer Engineering at Georgia Tech, has always supported my efforts in writing, and has my never ending thanks. Dr. William (Bill) Sayle, Vice-Chair for ECE Undergraduate Affairs, has also helped me more times than I can count during the many years we have known each other. I am grateful to my colleagues that have taken the time to discuss technical items with me. On the current project, this includes Dr. Glenn S. Smith, Dr. Andrew F. Peterson, and Dr. David R. Hertling in particular. I am grateful to the reviewers that took the time to weed through early versions of the manuscript that were full of typos, missing figures, and incomplete sections to give me their comments. Feedback from the many students and former students that have suffered through the course have helped shape the contents and presentation. Finally, I would like to thank my wife Melba and my daughters Valerie and Christine that have put up with dad sitting in front of the computer for hours and hours and hours. Their love has kept me going through this project and life in general!

John P. Uyemura Smyrna, Georgia Table of Contents

Preface vii

Table of Contents xi

Chapter 1 Physics and Modelling of MOSFETs 1

1.1 Basic MOSFET Characteristics 1 1.1.1 The MOS Threshold Voltage 3 1.1.2 Body Bias 9 1.2 Current-Voltage Characteristics 10 1.2.1 Square-Law Model 14 1.2.2 Bulk-Charge Model 18 1.2.3 The Role of Simple Device Models 19 1.3 p-Channel MOSFETs 19 1.4 MOSFET Modelling 22 1.4.1 Drain-Source Resistance 23 1.4.2 MOSFET Capacitances 24 1.4.3 Junction Leakage Currents 35 1.4.4 Applications to Circuit Design 37 1.5 Geometric Scaling Theory 37 1.5.1 Full-Voltage Scaling 40 1.5.2 Constant-Voltage Scaling 43 1.5.3 Second-Order Scaling Effects 44 1.5.4 Applications of Scaling Theory 44 1.6 Small-Device Effects 45 1.6.1 Threshold Voltage Modifications 45 1.6.2 Mobility Variations 50 1.6.3 Hot Electrons 52 1.7 Small Device Model 53 1.8 MOSFET Modelling in SPICE 56 1.8.1 Basic MOSFET Model 56 xii

1.9 Problems 58 1.10 References 59

Chapter 2 Fabrication and Layout of CMOS Integrated Circuits 61

2.1 Overview of Integrated Circuit Processing 61 2.1.1 Oxides 61 2.1.2 Polysilicon 63 2.1.3 Doping and Ion Implantation 64 2.1.4 Metal Layers 67 2.2 Photolithography 68 2.3 The Self-Aligned MOSFET 71 2.3.1 The LDD MOSFET 72 2.4 Isolation and Wells 73 2.4.1 LOCOS 74 2.4.2 Improved LOCOS Process 77 2.4.3 Trench Isolation 78 2.5 The CMOS Process Flow 78 2.5.1 Silicide Structures 83 2.5.2 Other Bulk Technologies 83 2.6 Mask Design and Layout 85 2.6.1 MOSFET Dimensions 88 2.6.2 Design Rules 90 2.6.3 Types of Design Rules 90 2.6.4 General Comments 94 2.7 Latch-Up 94 2.7.1 Latch up Prevention 97 2.8 Defects and Yield Considerations 99 2.8.1 Other Failure Modes 100 2.9 Chapter Summary 101 2.10 References 102 xiii

Chapter 3 The CMOS Inverter: Analysis and Design 103

3.1 Basic Circuit and DC Operation 103 3.1.1 DC Characteristics 106 3.1.2 Noise Margins 109 3.1.3 Layout Considerations 112 3.2 Inverter Switching Characteristics 113 3.2.1 Switching Intervals 114 3.2.2 High-to-Low Time 115 3.2.3 Low-to-High Time 117 3.2.4 Maximum Switching Frequency 118 3.2.5 Transient Effects on the VTC 119 3.2.6 RC Modelling 120 3.2.7 Propagation Delay 122 3.2.8 Use of the Step-Input Waveform 124 3.3 Output Capacitance 125 3.4 Inverter Design 134 3.4.1 DC Design 134 3.4.2 Transient Design 137 3.5 Power Dissipation 140 3.6 Driving Large Capacitive Loads 144 3.7 Problems 152 3.8 References 154

Chapter 4 Switching Properties of MOSFETs 155

4.1 nFET Pass Transistors 155 4.1.1 Logic 1 Input 156 4.1.2 Logic 0 Input 158 4.1.3 Switching Times 159 4.1.4 Interpretation of the Results 159 4.1.5 Layout 161 4.2 pMOS Transmission Characteristics 163 4.2.1 Logic 0 Input 163 xiv

4.2.2 Logic 1 Input 164 4.2.3 Switching Times 165 4.3 The Inverter Revisited 166 4.4 Series-Connected MOSFETs 167 4.4.1 nFET Chains 167 4.4.2 pFET Chains 168 4.4.3 FETs Driving Other FETs 169 4.5 Transient Modelling 170 4.5.1 The MOSFET RC Model 171 4.5.2 Voltage Decay On an RC Ladder 173 4.6 MOSFET Switch Logic 185 4.6.1 Multiplexor Networks 186 4.7 Problems 189

Chapter 5 Static Logic Gates 193

5.1 Complex Logic Functions 193 5.2 CMOS NAND Gate 195 5.2.1 DC Characteristics 197 5.2.2 Transient Characteristics 201 5.2.3 Design 205 5.2.4 N-Input NAND 205 5.3 CMOS NOR Gate 206 5.3.1 DC Transfer Characteristic 207 5.3.2 Transient Times 210 5.3.3 Design 213 5.3.4 N-Input NOR 213 5.3.5 Comparison of NAND and NOR Gates 213 5.3.6 Layout 214 5.4 Complex Logic Gates 215 5.4.1 Examples of Complex Logic Gates 217 5.4.2 Logic Design Techniques 219 5.4.3 FET Sizing and Transient Design 221 5.5 Exclusive OR and Equivalence Gates 224 5.5.1 Mirror Circuits 226 5.6 Adder Circuits 230 5.7 SR and D-type Latch 232 5.8 The CMOS SRAM Cell 234 xv

5.8.1 Receiver Latch 237 5.9 Schmitt Trigger Circuits 238 5.10 Tri-State Output Circuits 243 5.11 Pseudo-nMOS Logic Gates 245 5.11.1 Complex Logic in Pseudo-nMOS 248 5.11.2 Simplified XNOR Gate 251 5.12 Compact XOR and Equivalence Gates 253 5.13 Problems 256

Chapter 6 Transmission Gate Logic Circuits 259

6.1 Basic Structure 259 6.1.1 The TG as a Tri-State Controller 260 6.2 Electrical Analysis 262 6.2.1 Logic 1 Transfer 263 6.2.2 Logic 0 Transfer 264 6.3 RC Modelling 266 6.3.1 TG Resistance Estimate 266 6.3.2 Equivalent Resistance 267 6.3.3 TG Capacitances 270 6.3.4 Layout Considerations 271 6.4 TG-Based Switch Logic Gates 271 6.4.1 Basic Multiplexors 272 6.4.2 OR Gate 273 6.4.3 XOR and Equivalence 274 6.4.4 Transmission-gate Adders 276 6.5 TG Registers 276 6.6 The D-type Flip-Flop 278 6.7 nFET-Based Storage Circuits 281 6.8 Transmission Gates in Modern Design 283 6.9 Problems 284 xvi

Chapter 7 Dynamic Logic Circuit Concepts 287

7.1 Charge Leakage 287 7.1.1 Junction Reverse Leakage Currents 289 7.1.2 Charge Leakage Analysis 291 7.1.3 Subthreshold Leakage 295 7.1.4 pFET Leakage Characteristics 296 7.1.5 Junction Leakage in TGs 297 7.2 Charge Sharing 303 7.2.1 RC Equivalent 305 7.3 The Dynamic RAM Cell 311 7.3.1 Cell Design and Array Architecture 314 7.3.2 DRAM Overhead Circuits 319 7.4 Bootstrapping and Charge Pumps 319 7.4.1 Physics of Bootstrapping 324 7.4.2 Bootstrapped AND Circuit 326 7.5 Clocks and Synchronization 326 7.5.1 Shift Register 327 7.5.2 TGs as Control Elements 330 7.5.3 Extension to General Clocked Systems 330 7.6 Clocked-CMOS 331 7.7 Clock Generation Circuits 335 7.8 Summary Comments 345 7.9 Problems 345

Chapter 8 CMOS Dynamic Logic Families 349

8.1 Basic Philosophy 349 8.2 Precharge/Evaluate Logic 350 8.2.1 NAND3 Analysis 352 8.2.2 Dynamic nMOS Gate Examples 358 8.2.3 nMOS-nMOS Cascades 359 8.2.4 Dynamic pMOS Logic 363 8.2.5 nMOS-pMOS Alternating Cascades 367 xvii

8.3 Domino Logic 369 8.3.1 Gate Characteristics 371 8.3.2 Domino Cascades 374 8.3.3 Charge Sharing and Charge Leakage Problems 377 8.3.4 Sizing of MOSFET Chains 381 8.3.5 High-Speed Cascades 389 8.4 Multiple-Output Domino Logic 392 8.4.1 Charge Sharing and Charge Leakage 395 8.4.2 Carry Look-Ahead (CLA) Adder 396 8.5 Self-Resetting Logic 404 8.6 NORA Logic 408 8.6.1 NORA Series-Parallel Multiplier 414 8.7 Single-Phase Logic 416 8.8 An Overview of Dynamic Logic Families 430 8.9 Problems 431 8.10 References 433

Chapter 9 CMOS Differential Logic Families 435

9.1 Dual Rail Logic 435 9.2 Cascode Voltage Switch Logic (CVSL) 437 9.2.1 The pFET Latch 437 9.2.2 CVSL Buffer/Inverter 438 9.2.3 nFET Switching Network Design 440 9.2.4 Switching Speeds 445 9.2.5 Logic Chains in CVSL 445 9.2.6 Dynamic CVSL 447 9.3 Variations on CVSL Logic 448 9.3.1 Sample-Set Differential Logic (SSDL) 448 9.3.2 ECDL 451 9.3.3 DCSL 453 9.4 Complementary Pass-Transistor Logic (CPL) 453 9.4.1 2-Input Arrays 456 9.4.2 3-Input Arrays 459 9.4.3 CPL Full-Adder 462 9.5 Dual Pass-Transistor Logic (DPL) 462 xviii

9.6 Summary of Differential Design Styles 465 9.7 Single/Dual Rail Conversion Circuits 468 9.7.1 Single-to-Dual Rail Conversion 468 9.7.2 Dual-to-Single Rail Conversion 468 9.7.3 A Basic Current Source 472 9.8 Problems 473 9.9 References 475

Chapter 10 Issues in Chip Design 477

10.1 On-Chip Interconnects 477 10.1.1 Line Parasitics 477 10.1.2 Modelling of the Interconnect Line 480 10.1.3 Clock Distribution 490 10.1.4 Coupling Capacitors and Crosstalk 492 10.2 Input and Output Circuits 498 10.2.1 Input Protection Networks 498 10.2.2 Output Circuits 504 10.3 Transmission Lines 510 10.3.1 Ideal Transmission Line Analysis 510 10.3.2 Reflections and Matching 513 10.4 Problems 521 10.5 References 523

Index 525 CMOS LOGIC CIRCUIT DESIGN