CE3101: DIGITAL ELECTRONICS AND COMPUTER INTERFACING

LABORATORY LW5: DIGITAL LOGIC FAMILIES

INTRODUCTION

The development of digital integrated circuits naturally parallels the maturation of the semiconductor industry. The discovery in 1947 of the point‐contact transistor by Bardeen and Britain was followed by Shockley’s discovery in 1948 of the bipolar junction transistor. These discoveries changed the world and together these three Bell Labs researchers shared the 1972 Nobel Prize in Physics. The MOSFET transistor was not fully realized until the successful experiments of Kahng and Atalla, another set of Bell Labs researchers, in 1959. The ten‐year maturation lead held by the BJT device ensured that BJT‐based digital logic circuits would dominate throughout most of the 1960s, and 1970s. However, the advantages of MOSFET switches in size and power made CMOS the dominant technology by the 1990s. Logic equations require the ability to form the complement of a signal. The design of a family of digital integrated circuits begins with the design of the inverter. Circuit theory equations are developed to achieve output performance goals for the inverter such as the output low voltage, power consumption, or propagation delay. These equations are solved to determine the required component values in the circuit. The results from this reference inverter are then scaled to n‐input logic gates. The inverter drives the output to two different logic values using the pull‐up circuit and the pull‐down circuit. This is diagrammed abstractly in Figure 1.

Figure 1: The basic structure of a digital logic gate

Dr. Russ Meier, Milwaukee School of Engineering, Last Update: April 9, 2018 CE3101: DIGITAL ELECTRONICS AND COMPUTER INTERFACING

LABORATORY LW5: DIGITAL LOGIC FAMILIES

Each circuit can include passive components such as resistors and capacitors, as well as semiconductor components such as diodes and transistors. The classic logic families shown in Figure 2 achieve their performance goals through different configurations of these devices.

INTEGRATED CIRCUIT LOGIC FAMILY INVERTER CIRCUIT Resistor‐transistor logic (RTL) VCC  Fairchild Semiconductor, 1961  Passive pullup resistor  Active pulldown BJT RC Advantage: Y  Simple design RB A NPN Disadvantages: Q1

 Speed  Resistor Size  Static Power  Input current must be sourced

Diode‐transistor logic (DTL) VCC  Signetics, 1962  Passive pullup resistor  Active pulldown BJT RB RC Advantage: Y  Better noise margin than RTL

Disadvantages: A NPN Q1 D1 D2  Speed  Resistor Size  Static Power  Current flows out of input

Figure 2: Inverters in Various Logic Families

Dr. Russ Meier, Milwaukee School of Engineering, Last Update: April 9, 2018 CE3101: DIGITAL ELECTRONICS AND COMPUTER INTERFACING

LABORATORY LW5: DIGITAL LOGIC FAMILIES

INTEGRATED CIRCUIT LOGIC FAMILY INVERTER CIRCUIT Transistor‐transistor logic (TTL) VCC  Sylvania Universal, 1963  Passive pullup resistor  Back‐to‐back N‐P‐P‐N input diodes of DTL replaced with NPN transistor RB1 RC2  Active pulldown BJTs

Advantages: Y

 Only one semiconductor structure NPN  Better speed than DTL A NPN Q2 Q1 Disadvantages:

 Resistor Size  Static Power  Current flows out of input

MOS logic (PMOS) -VDD  General Microelectronics, 1964  Passive pulldown resistor to ‐VDD  Active pullup resistor to 0V  Historical point: Intel 4004 was PMOS RD Advantage:

Y  MOSFET size smaller than BJT  No input current

Disadvantage: A

 Resistor Size  Static Power  Negative voltages

Figure 2 Continued: Inverters in Various Logic Families

Dr. Russ Meier, Milwaukee School of Engineering, Last Update: April 9, 2018 CE3101: DIGITAL ELECTRONICS AND COMPUTER INTERFACING

LABORATORY LW5: DIGITAL LOGIC FAMILIES

INTEGRATED CIRCUIT LOGIC FAMILY INVERTER CIRCUIT Complementary MOSFET (CMOS) VDD  RCA, 1965‐1968  Active pullup PMOS  Active pulldown NMOS

PMOS Advantage:

 Speed Y  Size  No static power  No input currents A NMOS Disadvantage:

 Two types of transistors  Sensitive to electrostatic discharges

Figure 2 Continued: Inverters in Various Logic Families Engineers optimize speed, size, power, and cost. These four areas are balanced in trade‐off decisions during design. Design decisions lead to advantages and disadvantages. Figure 2 lists some advantages and disadvantages of each family; and arguably there are more that could be included. Historically, engineers made modifications to the basic circuits in Figure 2 as they attempted to overcome disadvantages. These modifications formed family sub‐types by adjusting component values or by adding additional passive and active components in the pullup and pulldown networks. One example subtype is low power TTL (74LS) which used larger pullup resistances to reduce current and power consumption. The quest to optimize speed, size, and power led to continual development of new configurations. Today, the industry has settled on CMOS as the dominant circuit because the advantages far outweigh the disadvantages. MOSFET scaling followed Moore’s Law and continually reduced conduction distance. This allowed frequency scaling to high‐speed. Also, MOSFET devices are smaller than BJTs and more CMOS gates can be fabricated on a given surface area. Finally, the strongest advantage is no static power consumption. CMOS does not allow current to flow between the power supply and ground when the output is stable at either logic‐1 or logic‐0.

Dr. Russ Meier, Milwaukee School of Engineering, Last Update: April 9, 2018 CE3101: DIGITAL ELECTRONICS AND COMPUTER INTERFACING

LABORATORY LW5: DIGITAL LOGIC FAMILIES

The electrical performance of an inverter is measured in the voltage and time domains. Voltage domain plots examine how the output changes as the input changes voltage. The resulting plot is called a voltage‐transfer characteristic (VTC). Figure 3 provides an example for a +5V inverter. Note the input voltage is plotted from 0 to 5V and the output responds as an inverter shape from 5V to 0V.

5.0V VOH

VIL (569.620m,4.9739)

4.0V

3.0V

2.0V

VM (743.514m,746.692m) 1.0V

VIH (778.481m,136.750m)

VOL 0V 0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V v(4) VA Figure 3: An Inverter Voltage Transfer Characteristic There are five points of interest on the voltage‐transfer characteristic. They are:

 VOH: the output high voltage,  VOL: the output low voltage,

 VIL: the last input considered low by the circuit (first point where dVY/dVA = ‐1),

 VIH: the first input considered high by the circuit (second point where dVY/dVA = ‐1), and  VM: the point where the input and output voltages equal. These five points can be manipulated by changing the design of the pullup and pulldown networks or by adjusting the semiconductor parameters. The Figure 3 inverter has a very low input voltage noise margin. Consider the input signal held low at logic‐0. Any noise present on the signal will move the plot on the VA axis. There is only approximately 0.5V margin before this noise would be misinterpreted as a logic‐1 and inverted. The plot also shows a very wide high noise‐margin. The ideal noise margins would be balanced with a sharp output transition occurring at VDD/2.

Dr. Russ Meier, Milwaukee School of Engineering, Last Update: April 9, 2018 CE3101: DIGITAL ELECTRONICS AND COMPUTER INTERFACING

LABORATORY LW5: DIGITAL LOGIC FAMILIES

A digital logic gate is design to be driven by the output of another logic gate from the same family. The input of any gate will transition from the previous gate VOL to the previous gate VOH. This gives these equations for the noise‐margin widths: logic‐low noise margin: NML = VIL – VOL logic‐high noise margin: NMH = VOH ‐ VIH Time domain plots examine input‐to‐output propagation delay, output signal rise time, and output signal fall time. Figure 4 shows one example measurement.

6.0V

4.0V

50% input (50.002n,2.5104)

2.0V

0V v(1) 6.0V

TPHL = 50% output - 50% input 4.0V 50% output (50.026n,2.5104)

2.0V

SEL>> 0V 48.0ns 48.5ns 49.0ns 49.5ns 50.0ns 50.5ns 51.0ns 51.5ns 52.0ns v(4) Time Figure 4: Measuring Output Time to Propagate High‐to‐Low in the Time Domain Time domain analysis has at least four values of interest:

 TPHL: the time for the output to propagate high to low,  TPLH: the time for the output to propagate low to high,  Tr: the time for the output to rise from low to high voltage, and  Tf: the time for the output to fall from high to low voltage. Different manufacturers use different measurement techniques when stating time domain delays. The standard for propagation delays is to measure from 50% of the input change to 50% of the output change. Rise times and fall times typically use either 10% to 90% or 20% to 80%. The times are then quoted as 10‐90 rise‐time or 20‐80 rise time, for example.

Dr. Russ Meier, Milwaukee School of Engineering, Last Update: April 9, 2018 CE3101: DIGITAL ELECTRONICS AND COMPUTER INTERFACING

LABORATORY LW5: DIGITAL LOGIC FAMILIES

LABORATORY OBJECTIVES

 Use SPICE to identify the voltage transfer characteristic of digital inverters.  Use SPICE to characterize the static power of digital inverters.  Use SPICE to determine the noise margins of digital inverters.  Build and test multiple inverters in the laboratory.  Document the laboratory work in a laboratory report. REQUIRED SOFTWARE

 PSPICE AD Lite  Digilent Waveforms  Word processor REQUIRED HARDWARE FROM EECS TECH SUPPORT

 Blue Wire Box  Two (2) 3.9KΩ resistors  One (1) 2n7000 NMOS transistor  One (1) BS250 PMOS transistor  Two (2) 2N3904 NPN transistors  Two (2) 1N4148 signal diodes  Analog Discovery USB instrumentation kits TEST CIRCUIT

Function Generator Power Supply Oscilloscope V+ gnd V- gnd V+ gnd 1+ 1- 2+ 2-

RC

Y

RB A NPN Q1

Dr. Russ Meier, Milwaukee School of Engineering, Last Update: April 9, 2018 CE3101: DIGITAL ELECTRONICS AND COMPUTER INTERFACING

LABORATORY LW5: DIGITAL LOGIC FAMILIES

PRE‐LABORATORY SIMULATION

1. Use SPICE to complete two labeled plots in the same Probe window for each inverter in Figure 2. Hint: use the “Add Plot to Window” command from the Probe plot menu. The first plot is a voltage‐transfer characteristic with input voltage VA stepping from 0 to 5V at 0.001V increments (PMOS logic should step ‐5V to 0V in 0.001V increments). The second plot is the power supplied by the power supply. Use this PSPICE information.

SYMBOL DEVICE PSPICE Resistors R1 node1 node2 3.9K

NPN .model npnt NPN BF=100 IS=1.8f collector base Q1 collector base emitter npnt emiiter

diode .model diode D IS=1pA n=1.8 BV=75 anode cathode

D1 anode‐node cathode‐node diode

power VDD positive negative DC value

NMOS .model nmod NMOS KP=200U VTO=0.6V drain gate M1 drain gate source substrate nmod W=4U L=2U substrate source

PMOS .model pmod PMOS KP=80U VTO= ‐ 0.7V drain gate M1 drain gate source substrate pmod W=10U L=2U substrate source

ANALYSIS PSPICE STATEMENTS DC sweep VA node1 node2 DC max‐value

.DC VA 0 5 0.001 .PROBE .END

Dr. Russ Meier, Milwaukee School of Engineering, Last Update: April 9, 2018 CE3101: DIGITAL ELECTRONICS AND COMPUTER INTERFACING

LABORATORY LW5: DIGITAL LOGIC FAMILIES

2. Use your SPICE plots to measure and record this data.

PARAMETER RTL DTL TTL PMOS CMOS VOH

VIL

VM

VIH

VOL

NMH

NML

logic‐0 power

logic‐1 power

Dr. Russ Meier, Milwaukee School of Engineering, Last Update: April 9, 2018 CE3101: DIGITAL ELECTRONICS AND COMPUTER INTERFACING

LABORATORY LW5: DIGITAL LOGIC FAMILIES

LABORATORY EXPERIMENTS

1. Breadboard the RTL circuit from Figure 2 as a unit under test (UUT). Refer to transistor datasheets for lead (terminal) orientation. 2. Connect the RTL circuit to the Analog Discovery instrumentation kit. a. Use Analog Discovery waveform generator 1 (W1) as voltage input VA. Configure W1 as a 1KHz ramp‐up from 0 to 5V. b. Use the Analog Discovery Scope Channels 1 and 2 to visualize input VA and output VY respectively. Configure Channel 1 and Channel 2 at 2V/div with a time base of 100µs/div. Configure the trigger condition to be rising‐edge of Channel 1 at 2.5V level. c. Enable a +5V power supply. 2. View the waveforms on the oscilloscope. Use single‐sample rather than run mode. a. The sudden ramp input drop from 5V to 0V will have substantial signal noise around both signals. This is an artifact of the sample technique. The Waveform software defaults the oscilloscope channels to averaging of samples rather than instantaneous display. Use the Gear icons for Channels 1 and 2 to set the sample mode to Min/Max and then redo the single sample. This will remove the artifacts of averaging around the fast transition points. 3. Measure the five VTC points using the cursors and tools (View  Measurements) a. Measurements for VOH, VOL, and VM can be completed using cursors. b. You can estimate VIL and VIH using the cursors. 4. Repeat steps 1‐3 for the remaining inverters in Figure 2. LABORATORY REPORT

Submit a laboratory report using the preferred method of your instructor with these sections:

 Abstract: This section should be no more than one to two paragraphs describing the circuits and the work you have completed. This section should use text to convey to the reader the foundational principles of the circuits, outline the steps you took to complete the experiments, and summarize the success of your experiments.  Experiments: This section that includes the circuit diagrams, equations, plots, and any other text you wish to include that demonstrates your understanding of the work. Grab oscilloscope photos using your cell‐phone camera and add them to your document.  Conclusion: This short section describes how the laboratory reinforced your learning of the course material. Include any questions you still have so that the instructor can provide additional help if needed. Report submission deadline: 5 p.m. on the Sunday after your laboratory period.

Dr. Russ Meier, Milwaukee School of Engineering, Last Update: April 9, 2018