JAMES G. PALMER

COMPUTER SYSTEM ARCHITECTURES FOR FUTURE NAVY TACTICAL SYSTEMS

The Navy relies on real-time embedded computers for the operation of radar, missile, and decision support systems. Dramatic advances in computer technology offer possible solutions to the unique prob­ lems of future tactical systems. Candidate architectures based on the technology options are examined and related to selected Navy projects.

INTRODUCTION Since the introduction of computers as an integral part projects such as the Automatic Identification System, the of weapons systems, the performance of many Navy sys­ Cooperative Engagement Program, and the NATO AAW tems has depended on the processing capacities of their System. embedded computers. Because of constraints on equip­ The study reported here identifies some of the options ment space, weight, and cost, many Navy embedded sys­ in computer system technology and associated issues for tems have been tailored to initial requirements, only to Navy systems and focuses on the integration of promis­ find that long-term growth required costly redesign and ing technologies into computer system architectures that replacement of computer equipment. Computer technol­ are appropriate for meeting future needs of the embed­ ogy has progressed rapidly in recent years and consider­ ded computer systems. The study was originally oriented ation of new Navy embedded computer system architec­ to requirements for the NATO AAW System; the need for tures is warranted. Pressures are growing for substantially highly flexible, adaptable architectures to accommodate increased processing power to solve critical problems in multinational needs applies to a more general set of Navy real time, such as engagement-level sensor integration for problems, however. the NATO Anti-Air Warfare (AAW) System, the Coopera­ GENERAL COMPUTER SYSTEM tive Engagement Program for the Battle Group AAw Coordination Program, and numerous others. REQUIREMENTS AND DESIGN GOALS The military shipboard environment also poses a ma­ Requirements for Navy embedded computer systems jor challenge to the design of future high-performance include system performance, physical constraints, and computer equipment. The severe shock, vibration, tem­ the need for flexibility in applications to different com­ perature, and humidity that can occur during battle would bat system configurations. The specific system require­ rapidly disable most commercial computers; military ments for any application are typically defined in a equipment is built to environmental specifications to over­ corresponding system specification. The following are come these problems. No equipment will survive local­ generally important for any embedded system, however. ized battle damage or a serious fire, however, and most System Response Time. Requirements for system re­ ships are not designed with sufficient redundancy to main­ sponse time must be met, and certain mission-critical tim­ tain system operation when local damage occurs to their ing requirements must be satisfied under all conditions, computer systems. The redundancy and flexible recon­ regardless of other processing in progress. Response time figllrability necessary to achieve survivability could now requirements drive the specifications for computer pro­ be provided by improved data distribution techniques, cessing power, interface throughput, and appropriate redundant processors, and distributed software tech­ control to support quick response without operator in­ niques. tervention. Performance evaluation must be made on Planned upgrades to the Navy's standard shipboard the basis of threat scenarios that exercise the full range computers offer substantial performance improvement of required response times and capacities. and compatibility with existing software (although con­ Operational Availability/Survivability. The mission­ sideration of the standard computers in this article relates critical nature of many embedded applications means that primarily to the current versions of these computers). the computer system must be able to recover automati­ Also, the Next Generation Computer Resources Project cally from the failure of any element or of any intercon­ is a program to standardize several computer system tech­ nection of the computer system. The computer system. nologies for fleet use. Efforts toward an open architec­ design should provide for the maximum feasible avail­ ture for a backplane bus (i.e., local to a single chassis) ability and survivability. To offer survivability from lo­ and local area network (LAN) are important to future cal damage, it is essential that multiple processors and Navy systems. Similar technologies are being put to im­ associated interconnections be physically distributed and mediate use by experimental and prototype development have alternate interconnection paths.

226 Johns Hopkins APL Technical Digest, Volume 10, Number 3 (1 989) Space and Weight. Designs must accommodate deployment on ships that have small space and weight COMPUTER PROCESSING LOAD ANALYSIS margins or in even tighter constraints, such as on air­ The required computer processing load is a primary fac­ craft or placement in existing shipboard enclosures. tor in determining the computer system architecture for a Design Goals. In addition to the above critical require­ system. The processing load is the instruction execution rate ments, the following system-level design constraints are required by the computer system to perform all required often imposed on the computer system: functions within specified system time constraints. It is dif­ 1. Navy directives require that all future applications ficult to determine accurately the required processing load software be written in Ada, the DoD standard program­ without implementing the required program in the target ming language. language on the selected target computer system; however, 2. The design should be adaptable to system varia­ it becomes necessary to estimate processing requirements tions and should maximize reuse of software among at various stages of system development. these variations. Processing load requirements of programs or subpro­ 3. The design must provide for substantial growth grams can be expressed in various ways, such as millions (e.g., a factor of at least two to allow for enhancements of instructions per second (MIPS), floating-point operations during development and major additions through the per second (FLOPS), or as a percentage of a known com­ system life cycle). puter CPU capability. Use of FLOPS is relevant for programs 4. The design must support flexible control without that are primarily mathematical. Use of millions of instruc­ requiring a unique program code for each tactical sit­ tions per second can be misleading because of variances in uation. machine instruction efficiencies and methods of instruction time measurement. The percentage of processing load of SOFTWARE ARCHITECTURE a specific CPU is a useful metric when comparing programs targeted for the same computer and language, but conver­ CONSIDERATIONS sion of estimates to other target computers can introduce In developing a computer system architecture, the re­ inaccuracies. quirements and design constraints of the software im­ For real-time programs, the averaging of required pro­ pose critical, but often overlooked, requirements on the cessing over some time period (typically 1 s) may mask short­ computer equipment architecture. A few of the many term response requirements in the 1 to 10 ms range. Ac­ software ramifications are presented in this section. curate analysis therefore requires that the processing load be examined over the critical time intervals of the target sys­ Programming Language and Run Time tem. Also, use of multiprocessor subsystems to handle a A system's programming language can have a major common load via task sharing must account for the limita­ impact on run-time performance, program development tions of load balancing that can practically be achieved. cost, reuse of existing software, and maintainability over On the basis of several existing and planned Navy tacti­ the system's life cycle. Although the use of assembly lan­ cal embedded systems (e.g., NATO AAW, Aegis 2000, and guage can often give the best run-time performance, the Cooperative Engagement Capability), it appears that the pri­ development and maintenance processes would be so in­ mary need is for computer system capacity in the range of efficient that assembly language would be used only as 5 to 50 million instructions per second. There is also a need a last resort for small portions of programs that cannot for fewer systems with computationally intensive applica­ be implemented otherwise. Very few high-order languages tions to operate in the range of 50 to 200 million instruc­ provide adequate code execution efficiency for real-time tions per second, such as antisubmarine warfare sonar applications. For the Navy standard computers, the Navy­ processing and electronic warfare/electronic warfare sup­ unique CMS-2 language has been used for real-time pro­ port measures processing. Architectures in this study will grams. It is the Navy's intent (and a DoD requirement) therefore concentrate on solutions that can be easily con­ that Ada fulfill real-time computing needs for future figured for the range of 5 to 50 million instructions per sec­ mission-critical systems. The Ada Language SystemlNavy ond, with possible incorporation of additional processing is now available for the Navy's ANIUYK-43 and ANIUYK-44 capabilities to extend performance to the 200 million in­ computers, with a multiprocessing version due in 1990. structions per second range. Assessment of the run-time efficiency of UYK-43 and UYK-44 code is in progress. For certain minicomputers and microcomputers, rapid progress in the implementation of improvements are under consideration for revision to the various Ada compilers has resulted in acceptable real-time Ada standard. products for many applications. For very time-critical real­ time applications, some Ada run-time performance prob­ System Adaptability lems remain. Certain run-time features are optional or One of the architectural goals for many computer sys­ are stated ambiguously in the Ada specification, which tems is to provide adaptability to subsystem variations hinders progress in achieving critical run-time goals. For without major impact on the bulk of the computer hard­ effective Navy use of Ada, the optional features must be ware or software. System-unique features that can be supported, and the conventions for the unspecified task­ processed in a "front-end" processor can avoid impact ing characteristics should be defined consistently. Such on other software throughout the system. A design ap- fohns Hopkins APL Technical Digest, Volume 10, Number 3 (1989) 227 Palmer proach that isolates the device-specific processing from 2. Minimize interprocessor interface loads and device-independent processing can often be used to response-time requirements; minimize shared data, and achieve maximum configuration adaptability. Figure 1 design for routine message-passing interface versus high­ shows a software design that incorporates such layered priority interrupts where possible. design concepts. 3. Limit projected processing load per central process­ Prototype designs indicate that significant benefits ac­ ing unit (CPU) to 50%; provide for adequate performance crue to so-called loosely coupled systems, whereby the and initial growth reserve. processing of elements is primarily via message passing, 4. Isolate device-dependent processing to separate thus keeping the use of shared data to a minimum. Es­ processors where feasible; simplify development and tablishment of a controlled message dictionary to define maintenance of system variants. messages within and among systems then becomes an 5. Distribute local bus usage (where applicable) to ac­ effective means of management and process coordi­ commodate peak and average loads; provide for adequate nation. response time and growth. Subprogram Partitioning ARCHITECTURE OPTIONS Clear partitioning of functional elements is an essen­ Computer system architecture encompasses both equip­ tial element of good system design; the same principle ment and software aspects of computer system design. applies to software. Although large programs in single The physical (equipment) aspects include the processor computers can be partitioned by design convention to technology to be used; the processor interconnection tech­ achieve functional separation and well-defmed interfaces, niques; and the configuration of selected computers, in­ partitions are rarely maintained consistently throughout terconnection equipment, and computer system the life-cycle evolution of the program. peripherals. The use of separate processors within computer sys­ Computer Technology Options tems to create well-defined program partitions can sim­ plify the logical as well as the developmental and control Critical system requirements driving the selection of aspects of the system design. For very large systems (e.g., Navy embedded computers are processing speed (instruc­ C 3 systems), there may be acquisition advantages to in­ tions per second), response-time constraints, interface crementally developing, testing, and deploying subsys­ characteristics, extensibility to meet growth needs, com­ tems versus one large development. Carrying this concept patibility with the Ada language, commonality with other too far, however, can result in fragmentation and inter­ systems, reliability, survivability, and cost. facing inefficiency; therefore, optimal partitioning is a For Navy ships, the Navy standard UYK-43 and UYK-44 critical aspect of the computer system architecture. computers provide rugged, reliable service; they are sup­ It is important that the design goals related to parti­ ported routinely in the Navy's logistics and maintenance tioning be identified and followed consistently, allow­ training programs. The UYK-43 is a 32-bit computer that ing exceptions only when merited. The following is a set can be configured as a single or dual CPU multiproces­ of processor partitioning guidelines: sor to provide 2.25 or 4.5 million instructions per second, respectively. I The UYK-44 is a smaller 16-bit minicom­ 1. Associate subprograms with clearly defined func­ puter that is rated at approximately 0.9 million instruc­ tions, grouping one or more subprograms per processor. tions per second. 2 Each computer also includes fast-response, multiple-channel input/output capabilities. Performance upgrades are in development for both the Processing node UYK-43 and UYK-44, which will increase the useful life of these computers. Validated Ada compilers for the UYK-43 Application processes and UYK-44 are now available for general use. The widespread use of certain commercial minicom­ puters (e.g., Digital Equipment Company's vAX) has led to licensing agreements for production of militarized ver­ sions of these computers. Since the processing power of Communication Device-dependent system single-board microprocessors is now equivalent to many message Device-independent independent minicomputers, the introduction of vendor-unique mini­ messages message computers is not an effective approach for future Navy Direct control tactical systems. Board-level computers based on 32-bit microproces­ 3 Device-dependent translators sors such as the Motorola 68020 or Intel 80386 are be­ ing adopted extensively in the United States and in NATO LOW-level protocols countries for commercial, industrial, and military appli­ Interface hardware cations. Very-large-scale integration techniques have yielded major improvements in the performance-to­ weight ratio, yielding 4 to 6 million instructions per sec­ Other nodes Connected systems ond from current single-board microcomputers. Single­ Figure 1. Software layering concepts. board computer performance is rapidly increasing as evi-

228 Johns Hopkins APL Technical Digest, Volume 10, Number 3 (1989) Computer System Architectures for Navy Tactical Systems denced by recently announced microprocessors in the 10 To provide communication within a chassis, several million instructions per second range. Board-level com­ commercial standards exist for high-speed local (back­ puters are being militarized and embedded into combat plane) buses. A local bus provides a flexible method of systems (e.g., the AN/SPS-48C search radar and Mk 74 interfacing board-level computers, memories, and inter­ Tartar Fire Control System). With the availability of low­ face cards within a single chassis, with the option to recon­ cost, single-board computers, the clustering of multiple figure dynamically in case of failure. Although bus speeds boards on a high-speed bus provides even greater pro­ of 10 MB/s and higher are commonplace, care must be cessing power. By carefully designing to minimize bus taken in system design to avoid overloading the bus. 4 contention, a cluster of five microcomputer boards on The VMEbus and Multibus II are buses that are candi­ a backplane bus can now achieve processing on the or­ dates for Navy applications. Although the VMEbus is used der of 20 million instructions per second. By adopting in more applications, Multibus II has the advantages of an industry standard backplane bus (e.g., VMEbus, Mul­ interprocess message handling and dynamic reconfigura­ tibus II, or Futurebus) for communication within a pro­ tion over the VMEbus. The IEEE 896.1 (Futurebus) has been cessing cluster, the resulting open architecture will selected as a future Navy bus standard; since the Future­ accommodate upgrades of processors as growth requires. bus standard is still evolving, however, it is not yet avail­ The significant reduction in the number of replaceable able for Navy use. card types for microprocessor-based computers poten­ For system-wide (longer distance) interconnections, var­ tially simplifies logistics support and maintenance over ious LAN options are available. Communication among computers requiring a larger number of card types. Real­ many users is provided by LAN'S, using time or frequen­ time executives and efficient high-order languages now cy division multiplexing of a common media-typically exist for most microprocessors. Several validated Ada coaxial or fiber-optic cable. As the number of system in­ compilers are now available for the M68020 family, and terconnections increases, networks can offer advantages run-time performance is approaching that of other lan­ over point-to-point, including fewer interfaces per sub­ guages commonly used for real-time systems. system, less cable weight and space, flexibility for system Several companies have developed "super-micro" growth, and simpler casualty/survivability reconfigura­ computers based on multiple-microprocessor parallel ar­ tion; however, data transfer delays can be significantly chitectures. By providing a central task scheduler for larger than point-to-point interconnections. Commercially typically 10 to 30 microprocessors, a multiple-instruction­ popular networks such as Ethernet may provide adequate stream, multiple-data-stream (MIMD) parallel architecture overall bandwidth; for some real-time applications, how­ is achieved as exemplified by the Transputer and Con­ ever, they do not offer adequate responsiveness (latency) vex computers. Ada compilers being developed for such for high-priority transfers, although Ethernet performance machines will offer true concurrent real-time processing can be significantly improved by designs such as the in the future. militarized triple Ethernet design for the Royal Nether­ For some applications, another effective form of par­ lands Navy. Token passing bus and token passing ring allel processing uses a single-instruction-stream, multiple­ designs are intended to provide responsiveness to real-time data-stream (SIMD) architecture (e.g., Goodyear's milita­ events and are becoming popular in industry (e.g., OM'S rized Associative Processor). Operations on data arrays Manufacturing Automation Protocol [MAP] and the Na­ can be performed very rapidly; detailed analysis of can­ vy's SAFENET I). Furthermore, very high speeds (100 MB/s didate applications, however, is important to determine and higher) are achievable in fiber-optic-based networks how the mix of parallel versus sequential operations will such as the proposed Fiber Distributed Data Interface affect overall efficiency. MIMD and SIMD technologies can (FDDI) standard that is being adapted for Navy use (SAFE­ perform in the 20 to 200 million instructions per second NET II). Prototype FDDI-based interface units are being de­ range, which may be applicable to certain classes of veloped for military use by companies such as UNISYS, problems. Martin Marietta, and Farranti. 5 Other networks for the Canadian, United Kingdom, and German navies are also Processor Interconnection Options being developed. All approaches need to be appropriate­ The method of interconnecting processors and system ly configured to provide casualty and survivability mode elements is a key aspect of computer system architecture. operation. Significant requirements for interconnection methods are OPTIONS FOR COMPUTER SYSTEM speed of data transfer (bandwidth), response time of transfer (latency), ability to reconfigure to alternate paths, CONFIGURATIONS susceptibility to electromagnetic interference, weight and The development of a computer system architecture space of cables, and commonality of protocol and equip­ for an embedded application involves configuring the ment. Often a combination of interconnection methods required computer(s), integrated by appropriate inter­ is desirable within a system. connection method(s), to support processing loads, in­ Point-to-point methods can provide high-speed, dedi­ terface requirements, internal software tasking control, cated channels with guaranteed access (except in cases of casualty reconfiguration, and other system requirements failure). Weight can be minimized by using serial or fiber­ as summarized earlier. To analyze a cross section of ar­ optic techniques rather than parallel cables. Reconfigu­ chitectures, possible configurations were first represented ration requires redundant cable paths with electronic or by generic configurations distinguished by the degree of mechanical switching. centralization versus distribution and by interconnection

Johns Hopkins APL Technical Digest, Volume 10, Number 3 (1989) 229 Palmer methods. Variants could then be compared on the basis for casualty reconfiguration with the centralized approach, of alternative computers, specific interconnection sys­ fully redundant input/ output and an option to switch to tems, and casualty configuration options. Selected ex­ either of the UYK-43 cpu's and associated input/output amples are discussed in this article. controllers are indicated by alternate interconnection paths. This configuration provides no survivability mode Centralized Architecture in case of local battle damage. A highly centralized configuration that provides all pro­ To provide additional processing power and survivabil­ cessing in a single large processor or in a tightly coupled ity options, a second computer is required and must be multiprocessor (e.g., dual CPU UYK-43) is shown in con­ located in a separate space (configuration IB), supplying figuration IA. Navy shipboard computers typically in­ up to 9 million instructions per second if the UYK-43 is terface with 4 to 10 or more other devices such as sensor selected. This configuration uses point-to-point (parallel equipment, weapons equipment, other computers, oper­ or serial) channels. Backup input/output channels are ator interface equipment, and computer system peripher­ again provided for all interfaces; interfaces for this op­ als (disk, tape drive, printer). In configuration lA, all tion, however, require reconfiguration to the alternate interfacing subsystems connect directly to the computer computer. To extend the approach to accommodate com­ by point-to-point interconnections. For smaller applica­ binations of failed computers and interface channels can tions (less processing and/or input/output capability), the require a complex array of switches or redundant con­ central computer could be replaced by the UYK-44 or nections. ANI A YK-14 (airborne-equivalent) computers. To provide This configuration can be simplified by using a local area network (LAN). One possible LAN configuration is shown in configuration IC, using dual networks with a network bridge or some form of internal network reconfiguration for casualty options. The LAN connec­ tions require that either a network interface be built into A VAILABILITY AND SURVIVABILITY OPTIONS each subsystem (as shown) or that separate network in­ Achieving high system availability and survivability from terface adapters be connected between subsystems and local battle damage is a critical requirement for Navy sys­ the network. (Configuration IC shows a generic network tems. The following are options for achieving high system with no attempt to distinguish bus versus ring topolo­ availability: gies.) The LAN option permits flexible channel selection at each interfacing subsystem, independent of which 1. By designing components for extremely high reliabil­ computer is connected to the subsystem. ity and low mean-time-to-repair, high availability (percent A similar architecture may be achieved by using up­ of time operational) is achieved. Extremely-high-reliability graded UYK-43 or UYK-44 computers or militarized super­ components should be a goal; however, this approach does minicomputers to attain better performance and growth not offer immunity to battle damage. Consequently, this potential. option alone is not sufficient. 2. Reconfiguration of multiple computers to bypass a failed computer is a common approach to provide a fail­ soft capability (e.g., the Aegis Combat System and the Federated Architecture AN/ SYS-2 Integrated Automatic Detection and Tracking Sys­ To provide federation of subsystem control, assure tem use this approach). In some cases, this requires provi­ timely interface servicing of connected subsystems, and sion of spare computer capacity so that mission-critical relieve the processing load on the central computer, con­ performance is maintained. Physical separation of proces­ figuration 2A shows computers dedicated to subsystem sors is required to provide survivability; however, the ca­ processing in keeping with goals for a layered design. pacity of remaining processors in the event of battle damage This approach is commonly applied for independent sen­ may be inadequate. sor or fire-control processing in combat systems. The 3. Full redundancy of all critical computers and relat­ UYK-44 is typically used for applications not requiring the ed components permits rapid automatic reconfiguration capacity of the larger UYK-43 computer. from a failed component to a ready spare and permits recon­ Configuration 2B adds redundancy for survivability. figuration to alternate equipment in the case of local battle Again, providing for survivable reconfiguration options damage without loss of mission-critical performance. This as shown in configuration 2B creates problems of logical requires effective fault localization, a reassignment mecha­ and physical switching complexity. Consequently, design nism, and avoidance of single-point failure modes. compromises that limit reconfiguration flexibility and af­ Redundant interconnection among critical subsystems is fect computer system load balancing are often necessary. necessary to ensure connectivity if any single input!output As the number of interconnected systems and subsystems controller or cable fails. This redundant interconnection ap­ increases, it is particularly beneficial to simplify interfac­ proach was adopted with Aegis for all computer interfaces. ing and improve reconfiguration flexibility by using a Cable space and weight can become significant if point-to­ LAN, as shown in configuration 2C. These configurations point parallel (versus serial) cable is used for this form of might use any mix of UYK-43 or UYK-44 computers, but redundancy. reconfiguration is simplified if only one computer type is used.

230 Johns Hopkins APL Technical Digest, Volume 10, Number 3 (1989) Computer System Architectures for Navy Tactical Systems CONFIGURATION 1 OPTIONS

I Display I Display I ~ periPheralsl I I I I T 1 Connected Connected systems I III systems I J I I AN/UYK-43 I computer I I I I I I I I I I I I r l I I I I ~

I Configuration 1A. I I I I Central control with casua~ y mode input/output. I

Display I Display I IPeripherals I T ~ I I 1 Connected Connected systems I I systems I I I I AN/UYK-43 I I computer I I I I I I

I ~ rl I I 1 I I ~ ~ I AN/UYK-43 computer

Configuration 1B. Dual UYK-43, survivable pomt-to-pomt option.

Network Display Display rPeripherals I I I I ~ I bridge I I I I T T I I I I I I Connected I Connected systems I T systems I J I AN/UYK-43 I I I I computer I I I I I I I I I I I I I I I AN/UYK-43 - I computer -

--- Primary elements --- Casualty elements Configuration 1C . Central control, survivable networked option.

fohns Hopkins APL Technical Digest, Volume 10, Number 3 (1989) 231 Palmer

CONFIGURATION 2 OPTIONS

Connected

AN/UYK-43 1------; computer 1------; ~-~----~ ~----~

Configuration 2A. Distributed subsystem control.

Connected systems

I---+---i AN/UYK-43 1--+-_--1 computer

AN/UYK-43 computer

Configuration 2B. Distributed subsystem control, survivable point-to-point option.

Connected Connected systems

Primary elements Configuration 2C. Casualty elements Distributed subsystem control, survivable networked option.

232 Johns Hopkins APL Technical Digest, Volume 10, Number 3 (1989) Computer System Architectures f or Navy Tactical Systems Distributed Multiple Microprocessors RESULTS OF EMBEDDED The availability of high-speed local buses with com­ COMPUTER SYSTEMS AT APL patible high-performance, single-board microcomputers With the development of prototype computer-based has led to clustering of microcomputers, shared memo­ systems at APL, there is substantial evidence of the ry, and cards for subsystem interfacing on single­ above-cited benefits of open-system architectures. The backplane buses using open-system (nonproprietary) ar­ Fleet Systems Department has contributed to the com­ chitectures. Configuration 3A illustrates a system that puter system design of major Navy systems since the uses a single cluster of 4 microcomputers and 10 inter­ 1960s; examples from past developments illustrate the face boards on a single local bus. In a relatively small benefits and problems of selected computer system ar­ enclosure (approximately 2 ft3), a processing capacity chitectures. of 16 million instructions per second is easily achieved Since earlier Navy computers were relatively large and with industry-standard microcomputers. Recently an­ expensive, designs were limited to central architectures, nounced processors may at least double this perfor­ with priority given to software techniques for optimizing mance. In addition, each interface board can also include demanding real-time designs to run on limited comput­ a microprocessor to permit data conversions and front­ ing resources. The advanced multifunction array radar end processing for each device. Within the chassis, recon­ (AMFAR) developed at APL in the late 1960s included a ra­ figuration to eliminate a failed processor or interface card dar control and automatic tracking system implemented is possible. For major systems, a single bus may not yet in a single computer. It served as the advanced develop­ adequately support data-transfer volume or the number ment radar for the Aegis AN/ SPY-I radar. Also, the Na­ of processors required. In addition, a single cluster is vy's AN/ SYS-I Integrated Automatic Detection and not survivable in case of local damage. Tracking System began with an APL prototype. The AM­ The advantages of the multiple microprocessor ar­ FAR and SY~1 computer system designs are similar to con­ chitecture can be realized without incurring bus over­ figurations lA and IB; they are characterized by highly load by appropriate partitioning of the bus. Two or more efficient, event-driven, real-time executives and by exten­ clusters of microcomputers can be configured with each sive use of global data to minimize data transfers among cluster on a separate high-speed local bus. Interconnec­ modules. For these and other Navy systems, the necessi­ tion of processing clusters can be accomplished by any ty for highly optimized software designs created difficul­ of several methods. Configuration 3B illustrates a four­ ties in software maintenance and limited the margin for cluster configuration with point-to-point connections upgrade. among selected clusters. Navy combat systems have been developed and evolved Interconnections between clusters and connection with by integrating separate systems, each of which, when de­ other combat system elements using a LAN (configura­ livered, was within about 20010 of its processing capacity tion 3C) would not only improve reconfiguration flexi­ limit (the margin required by Navy standards). With this bility, but would significantly reduce the number of constraint, needs for major upgrades (requiring more than individual input/output ports (circuit boards and soft­ the 20% growth reserve) can be accommodated by one ware) on the microcomputer clusters. The network would of two alternative design approaches. The first is to rede­ accommodate additional system interfaces without point­ sign the existing system to accommodate additional com­ to-point cabling of each required data path. Standard puting resources, which typically entails major recoding network interface adapters can be incorporated into the of the existing program before developing the added func­ processing cluster. To ensure that data transfers within tion. Once a program is under formal Navy maintenance, the computer system are responsive to timing needs, the cost of redesign, development, test, and documenta­ selected point-to-point channels or an auxiliary network tion is often prohibitive. The second approach is to cre­ reserved for high-priority use could be added if LAN per­ ate a new system for each major combat system upgrade, formance is not adequate to simultaneously support preferably with minor impact to interfacing systems. This latency requirements of all data transfers. All data paths approach leads to configurations similar to configuration are redundant, including the use of multiple-network 2A and has been used successfully by APL for prototypes data-transfer paths. Battle damage to the computer sys­ of the Shipboard Gridlock System 6 and Automatic tem can be tolerated to the extent that redundant clusters Identification System for fleet use. As additional require­ and input/output cables are physically separated. ments develop, however, the proliferation of separate fed­ By using current technology in microcomputers, back­ erated systems creates problems of interconnectivity, plane buses, and networks, it is possible to implement reconfiguration, and maintenance. a fully redundant computer system (every processor Recognition of the limitations of previous computer spared) without imposing inordinate space and weight re­ system architectures has led to application of distribut­ quirements on the ship. Three or more clusters can be ed multiple-microprocessor architectures such as config­ packaged in a single cabinet. Additional microprocessors urations 3A through 3C. Most real-time computer-based can be incorporated into each cluster, and clusters can prototypes begun in the past three years in the Fleet Sys­ be added to the network to provide extensibility for fu­ tems Department have adopted various elements of the ture growth. Furthermore, bus-compatible and software­ multiple-microprocessor architectures. One of the earli­ compatible upgrades to microcomputers of higher per­ er examples is the dual Motorola 68000 microprocessor­ formance can be introduced as necessary. based Detection Data Converter (DOC) developed by the

Johns Hopkins A PL Technical Digest, Volume 10, Number 3 (1989) 233 Palmer

CONFIGURATION 3 OPTIONS

I Display I Display I IPer ipherals I

Connected Multimicroprocessing cluster Connected systems systems INTF INTF I INTF INTF I I J INTF - - INTF I I I I INTF INTF I J ;--- INTF INTF - I I l I MP1 - - MP3 I MP2 MP4 I I I Local bus I I I I Configuration 3A. I I . . I I Distributed multiple microprocessor, single cluster .

Display II Display I Peripherals I J I Connected Connected systems systems INTF - ~ INTF - J LiNTF r---~ INTF I ~ MP1 - '"- MP2 MP1 I-- r-- MP4 ~ I r----- INTF - '"- MP3 MP2 I-- r-- INTF r-- I- - INTF - - MP4 MP3 I-- INTF I- f- r- I t INTF INTF INTF INTF H I INTF INTF I INTF - - INTF INTF I-- - INTF - I INTF - - INTF - --- INTF I-- - INTF !-- INTF - - INTF INTF r--- - INTF I MP1 - - MP2 MP1 I-- - MP4 I INTF MP3 MP2 INTF ~ ~ MP4 MP3 Configuration 38. Distributed multiple microprocessor, survivable quad cluster.

Display Display Network I I II IPeripherals I bridge I I I I I j I 1 I I I Connected Connected systems systems LAN ~ ~ MP4 LAN - - MP4 I r--- LAN - ~ ~ LAN - - ~ ~ - I MP1 - MP1 - ~ MP2 - ~ MP 2 - - I t= MP3 MP3 ~ I

I ~ LAN - ~ MP4 MP1 r--r-- LAN r--- R I - LAN - r- MP2 ~ ~ LAN r--- MP1 - r- MP3 r--r-- I ~ MP2 - r-- MP4 r--r-- tj I MP3

Configuration 3C. MP = Microprocessor card Primary elements Distributed multple microprocessor, INTF = Device interface card Casualty elements survivable networked option. LAN = Local area network interface

234 fohns Hopkins APL Technical Digest, Volume 10, Number 3 (1989) Computer System A rchitectures j or Navy Tactical Systems

Digital Systems Development Group at APL. The DDC control, multiship/multisensor data fusion, and automatic has subsequently been incorporated into the AN/ SPS-48C gridlock of both track and selected detection-level data, search radar by lIT as an upgrade to their original de­ posed a formidable computer processing task. The de­ tection processor. Similar technology was applied on a sign that evolved is an expandable configuration of five larger scale to provide multisensor range tracking and clusters of microcomputers (Fig. 3) similar to configura­ display at the Barking Sands Missile Range. A total of tion 2B that provides the required processing power and 57 Motorola 68020 single-board microcomputers dis­ growth reserve. As shown in Figure 3, a primary bus tributed over three radar sites and including backup serves processors for track management, display control, redundant processors make up the computer system for and gateways to four other buses, which serve the sensor the Automated Precision IFF Surveillance System. Sur­ interfaces, gridlock, and track update functions, with one face and air reports are received from three sites and then bus for expansion. The system includes a message-passing are tracked, correlated, and displayed by the system as method that provides a common applications program shown in Figure 2. Far more processing power than any view for transfer across the VMEbus and between buses previous Navy shipboard system in a fraction of the using the point-to-point gateways. The entire computer space and cost was clearly demonstrated. system, including peripherals and interactive maintenance The requirements for a Cooperative Engagement Capa­ panel, is housed in a 4-ft-high ruggedized enclosure. The bility had been evolving since battle group coordination prototype computer program and associated computer concepts were formulated in 1975. At the heart of the equipment are being developed by several groups in the problem was the need for a high-capacity, electronic­ Ship Systems Branch at APL. countermeasures-immune data link and substantial com­ In 1987, a consortium of six NATO nations agreed to puter processing capacity on each participating ship. Anal­ undertake jointly the concept development of a revolu­ ysis showed the benefits of a computer-controlled direc­ tionary short-range anti-air defense system for their re­ tional data-transfer system among ships of a battle group. spective navies. The NATO AAW System, as now defined, The requirements for a prototype system, including link includes advanced sensors of several types (radar, in-

Video display terminal Kokee Optional Peak

Makaha

Oahu ...- .... NTDS

Video &} To Kokee 1 1I.!!::::.:.:.::~=j~~~~~~~~~~====::sweeps NTDS '- consoles Peak Makaha Video &}TO Niihau 1 1I~~~~!l------:';-~ sweeps SPA '- repeaters

~ ______IRIG-B time ref.

Surface Tracking Display Video) To Subsystem Subsystem .....,;;~ __...!------~~~tr i ggers displays

I/OC-OX = InpuVoutput channel/data extraction IFF = Identification, friend or foe NTOS = Naval Tactical Data System IIOC = InpuVoutput controller GPIB = General purpose interface bus BOSS = Barking Sands Operations Support Systems

Figure 2. Automated precision IFF Surveillance System phase 1111 configuration.

Johns Hopkins APL Technical Digest, Volume 10, Number 3 (1989) 235 Palmer

Read-only- Bus Touch Data Sun display Track memory Gateway Gateway Gateway controller screen extract controller management board

Primary bus

rJ) rJ) :J rJ) rJ) :J .0 :J :J .D .0 .0 ~ ~ ~ ~ ca ,------,.~ ca ca "0 "0 "0 C c C C o o 0 0 u u u Cll '---_..... ~ ~ Cll rJ) rJ) rJ) ~ Cll c uo 0 '5 cu °en a. "0 ,------,. '0 c '5 a. ca 0 ::> ~ a. :;:, x :J UJ a. .E DDS = Data Distribution System CDS = Combat Direction System Growth INTF = Device interface card Figure 3. Configuration of prototype Cooperative Engagement Program hardwareo

frared, electronic warfare support measures), a high­ isting sensor integration programs that have been written performance short-range missile, a control system to per­ in the C language. The results showed that, for the com­ form multisensor integration, hard kill/soft kill coordi­ pilers compared, the Ada implementation is compara­ nation, and an automatic reaction to threats based on ble to the performance of one of the more efficient C doctrine defined in the Combat Direction System. To compilers; this is in contrast to benchmarking with ear­ be effective, the computer system must perform substan­ lier versions of Ada compilers, which resulted in sub­ tially more sophisticated tracking and control processes stantially less efficient code than other compilers. than past systems in a fraction of the time. There is also Although it is expected that even higher-performance a need to accommodate Combat Direction Systems and microprocessors will be used for the fmal NATOAAW Sys­ other interfacing systems of various navies, as well as tem, the excellent performance of current processors, such to provide for substantial future growth and casualty as the M68020, with most recent versions of off-the-shelf reconfiguration. Ada compilers has been comparable to processors using One of the computer system architectures studied in the more commonly used C compilers. On the basis of depth by the international government team is the dis­ these fmdings, the use of Ada with state-of-the-art tributed multiple-microprocessor architecture similar to microprocessors is considered a feasible building block configuration 3C. An experimental subset was assem­ for the NATO AAW computer system. bled at APL that consisted of three clusters of M68020 To support real-time performance needs and ease of microcomputers interconnected by a triply-redundant processor upgrade, it is desirable that a high-capacity, LAN developed by the Royal Netherlands Navy. The industry-standard backplane bus be used to integrate goals of the experimental system were to examine the multiple microprocessors. The local backplane bus select­ adequacy of the computer system architecture to satisfy ed for NATO AAw-critical experiments and the Cooper­ the projected requirements and to investigate possible ative Engagement Program was the vMEbus, which software design concepts for improving adaptability to provides a reasonably fast (theoretically 40 MB/s) bus national system variants. and a wide variety of commercial boards to facilitate rap­ At the individual processor level, the key issue was id prototype implementation. The lack of message­ the performanc~ of programs written in the Ada lan­ passing features and rigid board configuration methods, guage for the currently available microprocessors. The however, is viewed as a serious drawback that the Mul­ Ready Systems' RTAda compiler was selected on the ba­ tibus II bus has overcome. Consequently, we are recom­ sis of run-time performance of compilers for the M68020 mending that these features be added to the Futurebus in late 1987. Numerous benchmarks were run to assess standard, which the Navy has adopted for future Ada performance with the M68020. The most wide­ systems. spread benchmark for Ada programs is the set of bench­ The focus of the experimental development relative marks from the Performance Issues Working Group, to data communications was the message-passing sys­ which is valuable in comparing the performance of var­ tem, which provides a common applications program ious Ada compilers because it includes computational, view for transfers within a processor, across each back­ logical, and task-control-oriented programs. plane bus, and across the LAN. Of particular interest is Since multisensor integration potentially poses a large the decoupling of program modules by the generation processing load in the NATO AA W System, a candidate of messages that can be concurrently transferred to all Kalman fIlter algorithm was implemented in both C lan­ receiver modules registered for the message. It is antici­ guage and Ada, providing a basis of comparison for ex- pated that substantial independence of module design

236 Johns Hopkins A PL Technical Digest, Volume 10, Number 3 (1989) Computer System Architectures jor Navy Tactical Systems can be achieved by this technique, thereby facilitating ist; SAFENET I and II are Navy adaptations of token program development, maintenance, on-line data reten­ passing-ring standards. tion for rapid reconfiguration, and adaptability to sys­ Multiple high-performance processors coupled with ef­ tem variants. It appears that the added processing and fective underlying data communications techniques­ memory overhead required to support this concept can backplane buses and LAN's-offer the framework for a now be accommodated by recent microprocessor tech­ breakthrough in the design of Navy software that could nology. greatly simplify the development and life-cycle evolution The experimental NATO AAW computer system was the of large systems. By suffIciently decoupling functions, fIrst (or one of the fIrst) Navy project(s) to integrate mul­ removing dependency on shared data, and providing tight tiple real-time microprocessor clusters over a LAN. Al­ task synchronization, a level of modularity can be though conceptually simple, there are signifIcant technical achieved that has heretofore been unattainable. The pro­ issues associated with real-time data distribution. Once visions of Ada packages and object-oriented design tech­ resolved, however, the benefIts promise a major break­ niques are compatible with these goals. through in the design of combat systems and Navy soft­ ware. As stated earlier, benefIts include (1) extensibility REFERENCES by adding clusters, (2) a flexible means of reconfIgura­ 1 AN/UYK-43 Technical Description, UNISYS (1987). tion, especially for survivability from battle damage, (3) 2 AN/UYK-44 Technical Description, UNISYS (1987). less complex system development because of the reduced 3 MC68020 32-Bit Microprocessor User's Manual, Motorola, Prentice-Hall, Inc. number of interfaces to each computer, (4) the potential (1985). 4 James, J., "Performance and Programmability Considerations for VMEbus for simultaneous access by all users because data are Multiprocessors," in Proc. BUSCON East, DY-4 Systems Inc., pp. 225-239 provided on the network, and (5) the potential for a sys­ (1987). 5 Marien, K., "Emerging Standards, Hardware and Software Light the Way to temwide data dictionary and associated control procedures. FDDI," Compo Des., 51-56 (1989). 6 Miller, J. T., and David, E. W. G., " Battle Group Gridlock Demonstration," SUMMARY AND CONCLUSIONS Johns Hopkins APL Tech. Dig. 2, 314-320 (1981). Navy computer systems typically undergo substantial ACKNOWLEDGMENT-The author acknowledges the technical contribu­ evolution to accommodate changing needs over a life tions of Eric Conn, Robyn LeGrys, Larry Norcutt, and John Zouck. cycle that may span 20 years. Advances in computer sys­ tem technology now pennit the use of industry-standard, open architectures that can provide for substantial ex­ tensibility to satisfy future growth needs. THE AUTHOR Open architectures imply the use of industry-standard backplane buses versus vendor-unique bus designs, which JAMES G. PALMER, supervisor of the Computer Systems Develop­ is essential to the smooth evolution of processors, mem­ ment Group in the Fleet Systems ory, and interfaces for future upgrades or to solve un­ Department, received a B.S.E.E. foreseen performance problems during development. In degree in 1966 from Drexel Univer­ most cases, careful system design, such as bus partition­ sity and an M.S. degree in numeri­ ing, will accommodate the performance limitations of cur­ cal science in 1970 from The Johns Hopkins University. Since 1966 he rent standards. Later upgrade to higher-performance has been employed at APL, work­ buses (e.g., Futurebus) will better meet future needs. ing in the areas of radar control, Compatibility with industry standards appears appropri­ sensor integration, real-time systems ate if alterations to withstand environmental constraints design, and software engineering. His experience includes development are implemented. of radar control software for a pro­ The need for flexible reconfIguration, particularly for totype of the Aegis AN/ SPY-I radar, local damage survivability, has led to complex methods development of an experimental Ae­ of point-to-point interconnection in past systems. As gis sensor integration program, and combat system complexity increases, the only viable ap­ supervision of prototype system development for the Battle Group Anti­ Air Warfare Coordination and ATO AAW programs. In 1975, Mr. proach to adequate reconfigurability will be the use of Palmer participated in the Department of Defense Weapon Systems LAN'S to interconnect computers and ship systems. Many Management Study. He has been an instructor at The Johns Hopkins options remain open. Numerous industry standards ex- University G. W. C. Whiting School of Engineering.

Johns Hopkins APL Technical Digest, Volume 10, Number 3 (1989) 237