APPLICATION AP-28 NOTE

© Intel Corporation, 1977.

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INTELLEC Microcomputer Development System Hardware Reference Manual,98-132.

System 80/10 Microcomputer Hardware Reference Manual, 98-316.

8080 Microcomputer Systems User's Manual, 98-153.

SBC 501 Direct Memory Access Controller Hardware Reference Manual, 98-294.

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ICE-30 MCS ICE-80 MEGACHASSIS INSITE MICROAMP INTEL MULTIBUS INTELLEC PROMPT LIBRARY MANAGER UPI Contents

INTRODUCTION...... 1

INTEL MULTIBUS ...... , ...... 1 Intel MUL TIBUS Interfacing MULTIBUS SIGNAL DESCRIPTIONS .... . OPERATING CHARACTERISTICS...... 3

MULTIBUS INTERFACE CIRCUITS...... 8 ADDRESS DECODING ...... 8 BUS DRIVERS...... 9 CONTROL SIGNAL LOGIC...... 9

GENERAL PURPOSE SLAVE INTERFACE...... , ...... 10 FUNCTIONAL/PROGRAMMING CHARACTERISTICS...... 10 THEORY OF OPERATION ...... 11 USER SELECTABLE OPTIONS ...... 12 PROTOTYPING APPLICATIONS ...... 14

SUMMARy ...... 14

APPENDIX A MULTIBUS PIN ASSIGNMENT ...... 15

APPENDIXB MULTIBUS DC REQUIREMENTS ...... 16

APPENDIXC GPSI INTERF ACE SCHEMATIC AND WIRE LIST...... 17

APPENDIX D MECHANICAL SPECIFICATIONS ...... 18

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. INTRODUCTION share resources on the same bus. Actual transfers A significant measure of the power and flexibility via the bus, however, proceed asynchronously with of the Intel OEM Computer Product Line can be respect to the bus clock. Thus, the transfer speed attributed to the design of its system bus, the Intel is dependent on the transmitting and receiving MULTIBUSTM. The bus structure provides a com­ devices only. The bus design prevents slow master mon element for communication between a wide modules from being handicapped in their attempts variety of system modules which include: Single to gain control of the bus, but does not restrict Board Computers, memory and I/O expansion the speed at which faster modules can transfer boards, peripherals and controllers. data via the same bus. Once a bus request is granted, single or multiple read/write transfers The purpose of this application note is to help you can proceed. The most obvious applications for develop a basic understanding of the Intel MULTI­ the master-slave capabilities of the bus are BUS. This knowledge is essential for configuring a multi-processor configurations and high-speed system containing multiple modules. Another direct-memory-access (DMA) operations. However, purpose is to provide you with the information the master-slave capabilities of the MULTIBUS necessary to design a bus interface for a slave are by no means limited to these two applications. module. One of the tools that will be used to achieve this goal is the complete description of a general purpose slave interface. The detailed MULTIBUS SIGNAL DESCRIPTIONS description includes a wire list that you can use to build the interface on a prototype board. This section defines the signal lines that comprise Thus, you can connect your external logic to the the Intel MULTIBUS. Most signals on the MULTI­ MULTIBUS via this interface. BUS are active-low. For example, the low level of a control signal on the bus indicates active, while Other portions of this application note provide the low level of an address or data signal on the bus an indepth examination of the bus signals, oper­ shows logic" I " value. ating characteristics (AC and DC requirements), and bus interface circuits.

INTEL MULTIBUS NOTE The Intel MULTIBUS includes the following signal In this application note a signal will be lines: 16 address lines, 16 bidirectional data lines, designated active-low by placing a slash and 8 multi-level interrupt lines. The address and character (/) after the mnemonic for the data lines are driven by three-state devices, while signal. the interrupt and some other control lines are open-collector driven. Modules that use the MULTIBUS have a master­ slave relationship. A bus master module can drive Appendix A contains a pin· assignment list of the the command and address lines: it can control following signals. the bus. A Single Board Computer is an example of a bus master. On the other hand, a bus slave Initialization Signal Line cannot control the bus. Memory and I/O expansion INIT/ boards are examples of bus slaves. Initialization Signal; resets the entire system to a Notice that a system may have a number of bus known internal state. INIT/ may be driven by masters. Bus arbitration results when more than one of the bus masters or by an external source one master requests control of the bus at the same such as a front panel reset switch. time. The bus clock is usually provided by one of the bus masters and is derived independently from the processor clock. The bus clock provides a Address and Inhibit Lines timing reference for resolving bus contention among multiple requests from bus masters. For ADR~/-ADRF / example, a processor and a DMA (direct memory 16 address lines; used to transmit the address of access) module may both request control of the the memory location or I/O port to be accessed. bus. This feature allows different speed masters to ADRF / is the most significant bit. INHI/ BPRO/ Inhibit RAM signal; prevents RAM memory Bus priority out signal; used with serial (daisy devices from responding to the memory address chain) bus priority resolution schemes. BPRO/ on the system address bus. INH I / effectively is passed to the BPRN/ input of the master allows ROM memory devices to override RAM module with the next lower bllS priority. BPRO/ devices when ROM and RAM memory are is synchronized with BCLK/. This signal is not assigned the same memory addresses. INHI/ bused on the motherboard. may also be used to allow memory mapped I/O devices to override RAM memory. BUSY/ INH2/ Bus busy signql; driven by the bus master cur­ Inhibit ROM signal; prevents ROM memory rently in control to indicate that the bus is devices from responding to the memory address currently in use. BUSY / prevents all other on the system address bus. INH2/ effectively master modules from gaining control of the allows auxiliary ROM (e.g., a bootstrap pro­ bus. BUSY / is synchronized with BCLK/. gram) to override ROM devices when ROM and auxiliary ROM memory are assigned the same memory addresses. INH2/ may also be used BREQ/ to allow memory mapped I/O devices to over­ Bus request signal; used with parallel bus prior­ ride ROM memory. ity network to indicate that a particular master module requires use of the bus for one or more Data Lines data transfers. BREQ/ is synchronized with DAT~/-DATF/ BCLK/. This signal is not bused on the mother­ 16 bidirectional data lines; used to transmit or board. receive information to or from a memory location or I/O port. DATF / being the most significant bit. In 8-bit systems, only lines DAT~/-DAT7 / are used (DAT7/ being the Information Transfer Protocol Lines most significant bit). A bus master provides separate read/write com­ Bus Contention Resolution Lines mand signals for memory and I/O devices: MRDC/, MWTC/, 10RC/ and 10WC/, as explained below. BCLK/ When a read/write command is active, the address Bus clock; the negative edge (high to low) of signals must be stabilized at all slaves on the bus. BCLK/ is used to synchronize bus contention For this reason, the protocol requires that a bus resolution circuits. BCLK/ is asynchronous to master must issue address signals (and data signals the CPU clock. It has a 100 ns minimum period if write) at least 50 ns ahead of issuing a read/write and a 35% to 65% duty cycle. BCLK/ may be command to the bus, initiating the data transfer. slowed, stopped, or single stepped for debug­ The bus master must keep address signals un­ ging. changed until at least 50 ns after the read/write command is turned off, terminating the data CCLK/ transfer. Constant clock; a bus signal which provides a A bus slave must provide an acknowledge signal to clock signal of constant frequency for unspeci­ the bus master in response to a read or write com­ fiedgeneral use by modules on the system bus. mand signal. CCLK/ has a minimum period of 100 ns and a 35% to 65% duty cycle. MRDC/ BPRN/ Memory read command; indicates that the Bus priority in signal; indicates to a particular address of a memory location has been placed master module that no higher priority module on the system address lines and specifies that the is requesting use of the system bus. BPRN/ is contents of the addressed location are to be read synchronized with BCLK/. This signal is not and placed on the system data bus. MRDC/ is bused on the motherboard. asynchronous with BCLK/.

2 MWTC/ work. INT~/ has the highest priority, while Memory write command; indicates that the INT7/ has lowest priority. address of a memory location has been placed on the system address lines and that a data word (8 or 16 bits) has been placed on the system data bus. MWTC/ specifies that the data word is Power Supplies to be written into the addressed memory loca­ The power supply bus pins are detailed in Appen­ tion. MWTC/ is asynchronous with BCLK/. dix A which contains the pin assignment of signals on the MULTIBUS motherboard. 10RC/ It is the designer's responsibility to provide ade­ I/O read command; indicates that the address of quate bulk decoupling on the board to avoid cur­ an input port has been placed on the system rent surges on the power supply lines. It is also address bus and that the data at that input port recommended that you provide high frequency is to be read and placed on the system data bus. decoupling for the logic on your board. 10RC/ is asynchronous with BCLK/.

10WC/ Reserved I/O write command; indicates that the address of an output port has been placed on the system Several bus pins are unused. However, they should address bus and that the contents of the system be regarded as reserved for dedicated use in future data bus (8 or 16 bits) are to be output to the Intel products. addressed port. 10WC/ is asynchronous with BCLK/.

XACK/ Transfer acknowledge signal; the required re­ OPERATING CHARACTERISTICS sponse of a memory location or I/O port which Beyond the definition of the MUL TIBUS signals indicates that the specified read/write operation themselves it is important to examine both the AC has been completed. That is, data has been placed on, or accepted from, the system data and DC requirements of the bus. The AC require­ ments outline the timing of the bus signals and in bus lines. XACK/ is asynchronous with BCLK/. particular, define the relationships between the various bus signals. On the other hand, the DC requirements specify the bus driver characteristics, AACK/ maximum bus loading per board, and the pull-up/ Advanced acknowledge signal; a bus signal used down resistors. as a special acknowledge signal with 8080 CPU­ based systems. AACK/ is an advance acknowl­ edge, in response to a memory read or write command. This signal allows the CPU to com­ plete the specified operation without requiring AC Requirements it to wait. Interfaces which use AACK/ must The AC requirements are best presented by a dis­ also provide XACK/. This requirement must be cussion of the relevant timing diagrams. Table 1 met because not all bus masters will respond to contains a list of the MULTIBUS AC requirements. the AACK/ signal. AACK/ is asynchronous with The most basic bus operations are those of read BCLK/. and write data transfers. A majority of the user designed bus interfaces will provide a slave func­ Asynchronous Interrupt Lines tion with direct I/O rather than memory mapped I/O or master module capability. Because of this, INT~/-INT7 / you may only be interested in data transfers and 8 Multi-level, parallel interrupt request lines; can therefore skip the other timing diagrams dis­ used with a parallel interrupt resolution net- cussed in this section.

3 Table 1 MUL TIBUS AC REQUIREMENTS

PARAMETER MIN. MAX. DESCRIPTION REMARKS

tsCY 100 ns Bus Clock Period tsw 0.35 X tsCY 0.65 X tsCY Bus Clock Width tAS 50 ns Address Setup Time Relative to Active Command tos 50 ns Write Data Setup Time Relative to Active Command tAH 50 ns Address Hold Time Relative to Command Removal tOH 50 ns Write Data Hold Time Relative to Command Removal toxL o ns Read Data Setup Time Relative to Acknowledge (XACK/) toxT o ns Read Data Hold Time Relative to Command Removal tcx o ns 100 ns Acknowledge Hold Time Relative to Command Removal tXACK o ns 10 ms G> Acknowledge Delay tACC o ns tXACK-tOXL Read Access Time

tCMo 100 ns Command Pulse Width tCI 100 ns Inhibit Delay· Relative to Address tACCS 1.5 flS 8:> Acknowledge of Inhibiting slave

D> The max. is imposed only if 8:> tACCS is a function of the the bus timeout feature is engaged cycle time of the inhibited slave (a field option)

Data Transfers Valid data should not be driven onto the bus prior The MULTIBUS provides a maximum bandwidth to command, and must not be removed until com­ of 5 MHz for single or multiple read/write trans­ mand goes away. The XACK/ signal, which is a fers. response indicating the specified read/write oper­ ation has been completed, must coincide or follow Figure 1 shows the read data transfer timing dia­ both the read access (tACe) and valid data (tDXL). gram. XACK/ must be held until the command goes away (tcx).

Read Data Write Data The address must be stable (tAS) for a minimum of The write data transfer timing diagram is shown in 50 ns before command. This time is typically used Figure 2. During a write data transfer, valid data by the bus interface to decode the address and thus must be presented in parallel with a stable address. provide the required device selects. The device Thus, the write data setup time (tDS) has the same selects establish the data paths on the user system requirement as the address setup time (tAS). The in anticipation of the strobe signal (command) requirement for stable data both before and which will follow. The minimum command pulse after command enables the bus interface circuitry width is 100 ns. The address must remain stable to latch data on either the leading or trailing edge for at least 50 ns following the command (tAR). of command. 4 I COMMAND! I I 1--1 l-tDXL XACK! I I

Figure 1. Read Data Transfer

tCMD rtDStAS tDHl STABLE ADDRESS! I I I VALID DATA! I I

COMMAND!

XACK!

Figure 2. Write Data Transfer

Inhibit Operations which has actual memory occupying the memory mapped I/O address space, may need to inhibit Hus inhibit operations are required by certain boot­ RAM or ROM memory to perform its functions. strap and memory mapped I/O configurations. The There are two essential requirements for a success­ purpose of the inhibit operation is to allow a com­ ful inhibit operation. The first is that the inhibit bination of RAM, ROM, or memory mapped I/O signal must be asserted as soon as possible, within to occupy the same memory address space. In the a maximum of lOO ns (tCl), after stable address. case of a bootstrap, it may be desirable to have The second requirement for a successful inhibit both ROM and RAM memory occupy the same operation is that the acknowledge must be delayed address space, selecting ROM instead of RAM for (tACCB) to allow the inhibited slave to terminate low order memory only when the system is reset. any irreversible timing operations initiated by A system designed to use memory mapped I/O, detection of a valid command prior to its inhibit. 5 This situation may arise because a command can be address is stable, local selects are generated for asserted within 50 ns after stable address (tAS) and both the PROM and the RAM. The PROM local yet inhibit is not required until 100 ns (tCI) after select produces the INHI/ signal which then stable address. The acknowledge delay time removes the RAM local select and its driver enable. (tACCB) is a function of the cycle time of the Because the slave RAM has been inhibited after it inhibited slave memory. Inhibiting the SBC 016 had already begun its cycle, the PROM XACK/ RAM board, for example, requires a minimum of must be delayed (tACCB) until after the latest 1.5 J..lsec. Less time is typically needed to inhibit possible acknowledgement from the RAM (tACCA). other memory modules. For example, the SBC 104 board requires 475 ns. Bus Control Exchange Operations Figure 3 depicts a situation in which both RAM The bus control exchange operation (Figure 4) and PROM memory have the same memory ad­ illustrates the relationship among the bus conten­ dresses. In this case PROM inhibits RAM, produc­ tion resolution signals using the parallel bus prior­ ing the effect of PROM overriding RAM. After ity technique.

ADDRESS! ---...,

r----READ DATA

DATA!

COMMAND

DRIVER ENABLE!

SLAVE A (RAM) XACK! I ----1-I ------

LOCAL SELECT!

DRIVER ENABLE!

-j

XACK!

SLAVE B (PROM)

INH1!

LOCAL SELECT!

Figure 3. Inhibit Operation

6 BCLK/

TRANSFER REQUEST/ ______~~------+_--~------~------~------

MASTER A

BREQ/ ------~------_+----~------+_------

BPRN/

TRANSFER REQUEST/

MASTER E' BREQ/

BPRN/

"NOTE: BUS PRIORITY MUST BE RESOLVED WITHIN ONE BCLK/ PERIOD. MASTER A MAST~R B ON BUS ON BUS

BUSY/

ADDRESS/

MASTER A COMMAND/

DRIVER ENABLE/ ------~~

ADDRESS/

MASTER B COMMAND/

DRIVER ENABLE/

Figure 4. Bus Control Exchange Operation

7 In this example master A has been assigned a lower The initial step in designing the address decode priority than master B. The bus exchange occurs portion of a MUL TIBUS interface is to determine because master B asserts a bus request during a the required number of unique address locations. time when master A has control of the bus. This decision is influenced by the fact that address The exchange process begins when master B decoding is usually done in two stages. The first requires the bus to access some resource such as an stage decodes the base address, producing an I/O or memory module. This internal transfer enable for the second stage which generates the request is synchronized with the falling edge of actual device selects for the user logic. A conveni­ BCLK/ to generate a bus BREQ/ signal. The active ent implementation of this two stage decoding BPRN/ signal to master A goes inactive because of scheme utilizes a single decoder driven by the high the BREQ/ from master B. When the BPRN/ signal order bits of the address for the first stage and a to master A is inactive and master A has completed second decoder for the low order bits of the a command which may have been in operation, the address bus. This technique forces the number of falling edge of BCLK/ is used to synchronize unique address locations to be a power of two, BUSY / going inactive. This allows the actual based at the address decoded by the first stage. exchange to occur because control of the bus has Consider the scheme illustrated in Figure 5. been relinquished and another master may then assume control. During this time the drivers of master A are disabled. Master B must take control AO--______--I DSo of the bus with the next falling edge of BCLK/, Al DECODER DSI A2 DS2 completing the actual bus exchange. Master B takes DS3 DS4 control by asserting BUSY/and enabling its DSs BASE DS6 tb DECODER drivers. Thus a full BCLK/ period in addition ADDRESS El DS7 the synchronization of the internal transfer request 2ND STAGE: is required for the bus exchange between masters USER DEVICE SELECTS 1ST STAGE: and must be included in bus latency calculations. BASE ADDRESS DECODER DC Requirements The drive and load characteristics of the bus signals are listed in Appendix B. The physical locations of the drivers and loads, as well as the pull-up/down Figure 5. Two Stage Decoding Scheme resistor of each bus line, are also specified. The As shown in Figure 5, the address bits A7-A3 are MULTIBUS DC requirements for drive and loading used to produce switch selected data outputs of are guidelines only. These guidelines are used on the first stage of decoding. A one of eight decoder Intel OEM products. has been used, with two of the address bits (A6 and MULTIBUS INTERFACE, CIRCUITS . A7) driving enable inputs. The address bits A2-AO There are three basic elements of a bus interface: enter the second stage decoder to produce 8 user address decoders, bus drivers, and control signal device selects when enabled by an address that logic. This section discusses each of these elements corresponds to the switch-selected base address. in general terms. A description of a detailed imple­ Address decoding must be completed before the mentation of a slave interface is presented in a later arrival of a command. Since the command may section of this application note. become active within 50 ns after stable address, the decode logic should be kept simple with a ADDRESS DECODING minimal number of layers of logic. Furthermore, This logic decodes the appropriate MULTIBUS the timing is extremely critical in systems which address bits into RAM requests, ROM requests, or make use of the inhibit lines. I/O selects. Care must be taken in the design of th,e A linear select scheme in which no decoding is address decode logic to ensure flexibility in the performed is not recommended for the- following selection of base address assignments. Without this reasons. First, the scheme offers no protection in flexibility, severe restrictions may be placed upon case multiple devices are simultaneously selected. various system configurations. Ideally, switches And second, the addressing within such a system and jumper connections should be associated with is restricted by both the lack of flexibility in base the decode logic to permit field modification of address selection and by the extent of the address base address assignments. space occupied by such a scheme. 8 BUS DRIVERS Another signat, advanced acknowledge (AACK/), The Intel MULTIBUS requires three-state drivers can be used in some 8080 based systems as an on the bidirectional data lines. For user designed advance notification that requested data will be logic which simply receives data from the MULTI­ valid when the bus master is ready to use it. This BUS, this portion of the bus interface logic may early acknowledge may decrease by one the num­ only consist of buffers. Buffers would be required ber of Wait states needed to complete a read or to ensure that maximum allowable bus loading is write operation. You should have a thorough not exceeded by the user logic. knowledge of the 8080 (as provided in the 8080 Microcomputer System User's Manual, 98-153) In systems where the user designed logic must before attempting to use AACK/. place data onto the MULTIBUS, three-state drivers are required. These drivers should be enabled only AACK/ can be used in certain applications where when a memory read command (MRDC/) or an I/O an early acknowledgment to the 8080 is needed read command (lORC/) is present and the module to allow it to proceed to the T3 state following the has been addressed. current T2 or Wait state. Such applications have the following characteristics - XACK/ is generated When both the read and write functions are re­ too late for the 8080 to detect it in the current quired, parallel bidirectional bus drivers (e.g., Intel state, but 8216/8226) are used. A note of caution must be included for the designer who uses this type of 1. valid read data will be placed on the bus by device. A problem may arise if data hold time the time the 8080 needs it in the current requirements must be satisfied for user logic fol­ state, or lowing write operations. When bus commands are 2. write data will be accepted from the bus by used to directly produce both the chip select for the time the 8080 has completed its write the bidirectional bus driver and a strobe to a latch operation. in the user logic, removal of that signal may not In either case, AACK/ is sent to the 8080 CPU­ provide the user's latch with adequate data hold based bus master early enough in the current state time. Depending on the specifics of the user logic, (T2 or Wait) to prevent the CPU from entering a this problem may be solved by permanently subsequent Wait state. The read or write transac­ enabling the data buffer's receiver circuits. tion is completed during the current T2 or Wait CONTROL SIGNAL LOGIC state and the CPU moves on to T3. The control signal logic consists of the circuits that It is important to note that XACK/ must be driven forward the I/O and memory read/write commands whether or not AACK/ is used. This requirement to their respective destinations, provide the bus exists because not all bus masters will respond to with transfer acknowledge responses, and drive the AACK/. system interrupt lines. Since XACK/ and AACK/ timing requirements Bus Command Lines depend on both the CPU of the bus master and characteristics of the user logic, a circuit is needed The MUL TIBUS information transfer protocol which will provide a range of easily modified lines (MRDC/, MWTC/, 10RC/ and 10WC/) should acknowledge responses. be buffered by devices with very high speed switch­ ing. Because the bus DC requirements specify that The transfer acknowledge signals must be driven each board may load these lines with 2.0 mA, by three-state drivers which are enabled when the Schottky devices are recommended. The com­ bus interface is addressed and a command is mands are gated with the signal indicating whether present. or not the base address has been decoded to gener­ ate read and write strobes for the user logic. Interrupt Signal Lines Transfer/Advance Acknowledge Generation The asynchronous interrupt lines must be driven The user interface transfer/advance acknowledge by open collector devices with a minimum drive generation logic provides a transfer acknowledge of 16 mAo response, XACK/, to notify the bus master that In a typical system, logic must be provided to write data provided by the bus master has been assert and latch up an interrupt signal. The latched accepted or that read data it has requested is interrupt signal would be removed at a later time available on the MULTIBUS. XACK/ allows the by an I/O operation such as reading the module's bus master to conclude its current instruction. status. 9 GENERAL PURPOSE SLAVE INTERFACE MULTIBUS INTERFACE USER LOGIC

Learning by example is often the most effective "" DEVICE ~ ) SELECTS ADDRESS means for absorbing technical information. With ADRO/-AORF/ \ ~ ) I DECODING C/D . this idea in mind, a detailed description of a '-/ r BASE general purpose slave interface (GPSI) has been I ADDRESS included in this application note. The description is .. generally directed towards the implementation of MRDC/ BD ENABLE/ MWTC/ CONTRDL RD/ an I/O interface. However, the GPSI can also be IORC/ LOGIC WRT/ IOWC/ used as a slave memory interface by simply buffer­ ing the additional address signals and using the .. appropriate MUL TIBUS memory commands. 8 f,. A Y-- ~ A BIDIRECTIONAL DATO/-DAT7/ BUS II The most significant aspect of the GPSI is that all ) DRIVERS !\ L DATA LINES ~ ~ y ~ '-/ V the information required to actually construct the

interface is contained in Appendix C. You can XACK/ ACKNOWLEDGE I ACKND WLEDGE make use of the schematic and wire list to proto­ AACK/ type your application.

INTERRUPT '---~- INTERRUPT FUNCTIONAL/PROGRAMMING INTO/-INT7/ LINE REQUEST CHARACTERISTICS BUFFERS .-----c-+- LIN ES This section briefly describes the organization of Figure 6. GPSI Block Diagram the GPSI from two points of view. The principal functions performed by the hardware are identified Effectively, this signal is used to select one of the and the general data flow is illustrated. This first two 8 device address groups, yielding a total of 16 point of view is intended as an introduction to the device addresses. The control/data line can also be detailed information provided in the next section, used directly with Intel peripheral chips such as Theory of Operation. In the second point of view the 825l. the information needed by a programmer to access The GPSI may be configured to provide either the GPSI is summarized. direct or memory mapped I/O for program access to its devices. When direct I/O is used, the various Functional Description devices are accessed by the addresses shown in The function of the GPSI is to provide bus inter­ Table 2. face logic which consists of those circuit elements Table 2 most directly involved with communication be­ GPSI ADDRESSING tween the bus master and the GPSI. These ele­ ments include bus address/control line receivers, DEVICE C/D = 0 C/D = 1 bidirectional data buffer, device select decode 1 XO X1 logic, transfer acknowledge generation, and line 2 X2 X3 driver circuits. 3 X4 X5 A functional block diagram of the GPSI is shown in Figure 6. 4 X6 X7 5 X8 X9 Programming Characteristics 6 XA XB The GPSI addressing provides 8 unique device 7 XC XD selects and a single line which may be used to indicate control/data. The module's base address 8 XE XF is assigned through the use of wire wrap connec­ X ~ Any hex digit; assigned by jumper; X is the same for all tions on the prototype board. Two such jumpers GPSI devices. are part of the board's address decode circuit for When the GPSI is configured for memory mapped system address bits ADR4/~ADR7/. They allow I/O, the low order 8 bits of the 16-bit address are the selection of a base address for the GPSI on a identical to those shown in Table 2 for direct I/O. l6-byte boundary. Address bits ADR1/~ADR3/ However, the upper 8 bits of the address must be are decoded by other logic to provide 1 of 8 device all ones. Thus, the addressable devices occupy selects for the user. A single line to implement a space within the upper 256 bytes of memory, control/data select function is provided by ADRtp/. FFtptp Hex to FFFF Hex. 10 THEORY OF OPERATION The base address is decoded by an Intel 8205 one In . the preceding section each of the GPSI func­ of eight binary decoder (Ag). This device is enabled tional blocks was identified and briefly defined. by either ADR7/ or ADR7, as determined by the This . section explains how these functions are wire-wrap connections. When enabled, Ag decodes implemented. For detailed circuit information, address bits ADR4/, ADR5/, and ADR6/ into one refer to the GPSI schematic in Appendix C. The of eight outputs. The base address enable (BASE schematic is on a foldout page so that you can ADR/) may be taken from anyone of the eight Ag relate the following text to the schematic. outputs. The GPSI contains those logic elements that When the ADR4/ through ADR 7 / bits correspond participate directly in the following types of to the selected base address, an enable is provided MULTIBUS activity. by Ag to a device select generator (A9) and the' read/write command gates (Ad. 1. Bus address, control, and data buffering The device select generator consists of an Intel 2. Bus address decoding 8205 decoder (A9) that is enabled by the base 3. Bus control signal propagation address. When enabled, A9 decodes address bits 4. Advance/Transfer acknowledge generation ADRI/, ADR2/, and ADR3/ into one of eight 5. Interrupt signal buffers. device select outputs. The five groups of logic responsible for these tasks When memory mapped I/O is used, the high order are described in the following paragraphs. 8 bits of the address bus are also decoded. The Bus Address, Control, and Data Buffers address bits ADR8/ through ADRF/ are used as inputs to a 74LS27 (A7). The outputs of A7 are Only one bit 'of the bus address is buffered and ANDed by a 74Sl0 (A2), producing an active low passed directly onto the user logic. The rest of the output only when ADR8/-ADRF / are all active. address bits are used to drive decoders. ADRf/J/ is This output signal, MMIO/, is used to generate buffered by a 74LS02 (Al3). The control signal optional inhibit signals as well as to enable the buffer circuit consists of a 74S32 (AI) and a 74Sl0 memory read and write commands when a connec­ (A2) for the memory and I/O read/write com­ tion is made between A2-g and A4-3. mands. These circuits are used to provide very high switching speed. The MMIO/ signal is inverted twice, first by a 74S04 (AI4) and then by 7406 open collector The data buffers are formed by two Intel 8226 drivers (A6). At that point the signal can be con­ inverting bidirectional driver/receiver chips (AlO nected to the system INHI/ and/or INH2/ bus and All). The system data bus is connected to the signal lines. device's DB pins. The DO and DI pins of each chip can be connected to the user logic, providing either The only situation in which the inhibit lines are an independent input and output bus or a bidirec­ required is if there is ROM or RAM in the system tional bus. which physically occupies the upper 256 bytes of memory. When this is the case, you may choose to Directional control (DIEN/) for the 8226's is exer­ disable the memory mapped I/O capability and use cised by the I/O read command (lORC/) or the direct I/O. Otherwise, you must select the proper memory read command (MRDC/) in situations inhibit connection to allow use of the memory where memory mapped I/O is used. If the read mapped I/O. INHI/ is used to inhibit RAM, while command is asserted by the bus master and the INH2/ inhibits ROM. module's base address is present, the data buffer's receiver circuits are enabled. With a worst case delay of 53 nanoseconds, the The chip select (CS/) for the data buffer is enabled decode circuit that produces the inhibit signals when a command is gated onto the board. meets the bus AC requirement for inhibit delay (tCI). However, the acknowledge of the inhibiting Bus Address Decoding slave (tACCB) is a much more difficult specification The bus address decoding logic decodes the appro­ to satisfy. The difficulty arises because the latest priate address bits into device selects. When mem­ possible acknowledgement from the inhibited slave ory mapped I/O is used, all ones on the high order memory (tACCA) must be known to ensure an 8 bits of the address are decoded. The GPSI logic adequate tACCB. In the worst case tACCB must be also produces an enable for the read/write com­ at least 1.5 microseconds. The acknowledge delay mand decode logic and the MUL TIBUS inhibit circuit, which will be described later, provides for signals. a maximum of approximately 800 nsec. In situa- 11 tions where a 1.5 Ilsec tACCB is required, the clock Advance/Transfer Acknowledge Generation frequency of the delay circuit must be halved or The advance/transfer acknowledge generation logic another device added to extend the selectable provides a transfer acknowledge response, XACK/, delay to 1.5 Ilsec. In this situation it may well be a to notify the bus master that data has either been better choice to disable the memory mapped I/O accepted from the MULTIBUS (during a write in favor of the simple direct I/O technique. operation) or placed on the MULTIBUS (during a read operation). An advance acknowledge re­ If the GPSI module is to reside in an Intel Micro­ sponse, AACK/, is also provided for use in certain computer Development System (lntellec) the 8080-based systems, where it can decrease by one memory mapped I/O capability must be disabled. the number of Wait states needed to complete a This restriction exists because the Intellec has read or.write operation. ROM program memory which occupies the entire memory mapped I/O region (FFCPCPH to FFFFH) Both acknowledge responses are generated by A12, and must not be overridden by the GPSI. an 8-bit serial in, parallel out shift register. When enabled by CMD, A12 shifts CCLK/ pulses. This produces a sequence of high true pulses at AI2'S Q outputs. The outputs occur at approximately 100 Bus Control Signal Propagation ns intervals. A pair of 74S32 OR gates (AI) buffer the MRDC/ The appropriate Q outputs are selected by wire­ (memory read command) and MWTC/ (memory wrap connections to the inputs of a pair of three­ write command) inputs from the MULTIBUS. state gates (A3). These gates drive the XACK/ and These gates are enabled by the MMIO/ (memory AACK/ outputs onto the MULTIBUS when mapped I/O) signal from the high order address enabled by BD ENABLE/. decoder. As mentioned in the previous discussion on inhibit operations, the maximum of about 800 ns delay The gated and buffered memory read and write provided by Al2 may not be adequate. This can be commands are then each ORed and buffered with extended by either using a flip-flop to pre-divide their respective I/O read and write commands by a CCLK/ or by adding a second shift register in series pair of 74S10 NAND gates (A2). The output of with A12. Although both techniques douqle the these gates are active high read and write com­ range, the first cuts the resolution in half. mands. Interrupt Signal Buffers The GPSI only provides buffering for the bus inter­ These commands are passed on to the advance/ rupt signal lines. Two 7406 open collector drivers transfer acknowledge generator via NOR gate A13. (As and A6) are used for this function. The output of Al3 is designated CMD/. CMD/ is enabled by the decoded base address at OR gate The MULTIBUS interrupt signals should be driven Al to produce the board enable. This signal, BD with levels rather than pulses, unless the bus master ENABLE/, controls the three-state gates that drive has an edge triggered interrupt controller. The AACK/ and XACK/ onto the MULTIBUS. BD user's logic must latch and hold the interrupt signal ENABLE/ also controls the chip selects for the until serviced by the bus master. data bus buffers. USER SELECTABLE OPTIONS The output of the I/O and memory write buffer is In this section, each of the options available to the inverted with a 74S04 (AI4) and forwarded as user is reviewed and the specific information WRT/ to the user logic. This internal write enable required to implement the desired characteristic should be qualified at each of these destinations is summarized. by the appropriate device select. The output of the I/O and memory read buffer is Base Address Selection inverted and then enabled by the decoded base The GPSI's base address is selected by wire-wrap address at AI- The resulting internal read enable, connections from one of the output pins of A8 to RD/, is applied to the user logic and to the direc­ an enable input (E2) of A9. Table 3 identifies the tion control (DIEN) on the bidirectional bus driver base address that is implemented for each jumper chips (AlO and All). combination. 12 Table 3 BASE ADDRESS SELECTION

BASE BASE FROM TO FROM TO FROM TO FROM TO ADDR ADDR

P1-52 A8-6 A8-7 A9-5 00 P'1-52 A8-5 A8-7 A9-5 80 GND A8-5 A8-9 A9-5 10 A4-1 A8-6 A8-9 A9-5 90 A8-10 A9-5 20 A8-10 A9-5 AO A8-11 A9-5 30 A8-11 A9-5 80 A8-12 A9-5 40 A8-12 A9-5 CO A8-13 A9-5 50 A8-13 A9-5 DO A8-14 A9-5 60 A8-14 A9-5 EO A8-15 A9-5 70 A8-15 A9-5 FO

Advance/Transfer Acknowledge Timing because of the skew introduced into the acknowl­ The GPSI's advance acknowledge and transfer edge circuit by the use of CCLK/ to drive A12. acknowledge response timing is selected in approxi­ Actual time values for these periods depend, of mately 100 ns increments by wire-wrap connec­ course, on the frequency of CCLK/. For the SBC 'tions at the outputs of A12- Table 4 shows the 80/10 or 80/20 bus masters, CCLK/ is 9.216 MHz, range of response timing for each possible connec­ which provides a clock period of 108.5 nano­ tion in terms of CCLK/ periods. This range occurs seconds.

Table 4 ADVANCE/TRANSFER ACKNOWLEDGE TIMING

DELAY FROM RECEIPT OF CMD PIN CONNECTIONS TO ACK GENERATION AACK XACK FROM: TO: FROM: TO: A4-4 A3-12 A4-4 A3-14 Immediate A12-3 A3-12 A12-3 A3-14 o to 1 CCLK/ Periods A12-4 A3-12 A12-4 A3-14 1 to 2 A12-5 A3-12 A12-5 A3-14 2 to 3

A12~6 A3-12 A12-6 A3-14 3 to 4 A 12-10 A3-12 A12-10 A3-14 4 to 5 A 12-11 A3-12 A 12-11 A3-14 5 to 6 A 12-12 A3-12 A 12-12 A3-14 6 to 7 A 12-13 A3-12 A 12-13 A3-14 7 to 8 CCLK/ Periods

13 PROTOTYPING APPLICATIONS SUMMARY The GPSI should be well suited for most prototyp­ This application note has shown the structure of ing applications by constructing the interface on a the Intel MULTIBUS. The structure supports a SBC 905 Universal Prototype Board. A complete wide range of system modules from the Intel OEM wire list is provided in Appendix C to further Computer Product Line that can be extended with simplify the task. The complete general purpose the addition of user designed modules. Because the slave interface requires 14 IC's and can best be laid user designed modules are no doubt unique to out by placement from left to right, AI-A14, particular applications, a goal of this application across the bottom of the SBC 905 (Figure 7). note has been to describe in detail the singular Using the GPSI constructed on an SBC 905, you common element - the bus interface. Material have the capacity for an additional 80 16-pin loca­ has also been presented to assist the systems tions for wire-wrap sockets or the equivalent mix designer in understanding the bus functions so that of 14,16, 18,22,24,28 or 40-pin sockets. successful systems integration can be achieved.

SBC-905 (COMPONENT SIDE)

Figure 7. Prototype Board Layout

14 APPENDIX A MULTIBUS PIN ASSIGNMENT

(COMPONENT SlOE) (CIRCUIT SIDE) PIN MNEMONIC DESCRIPTION PIN MNEMONIC DESCRIPTION

1 GND Signal GND 2 GND Signal GND 3 +5 +5 VDC 4 +5 +5VDC Power 5 +5 +5 VDC 6 +5 +5VDC Supplies 7 +12 +12 VDC 8 +12 +12 VDC 9 -5 -5 VDC 10 -5 -5VDC 11 GND Signal GND 12 GND Signal GND 13 BCLK/ Bus Clock 14 INIT/ Initialize 15 BPRN/ Bus Priority In 16 BPRO/ Bus Priority Out 17 BUSY/ Bus Busy 18 BRED/ Bus Request 19 MRDC/ Memory Read Command 20 MWTC/ Memory Write Command 21 IORC/ I/O Read Command 22 10WC/ I/O Write Command Bus 23 XACK/ XFER Acknowledge 24 INH1/ Inhibit 1 Disable RAM Controls 25 AACK/ Special Acknowledge 26 INH2/ Inhibit 2 Disable PROM or ROM 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 CCLK/ Constant Clk 32 Reserved 33 Reserved 34 Reserved 35 INT6/ 36 INT7/ 37 INT4/ 38 INT5/ Interrupts Parallel Interrupt Requests Parallel Interrupt Requests 39 INT2/ 40 INT3/ 41 INTO/ 42 INT1/ 43 ADRE/ 44 ADRF/ 45 ADRC/ 46 ADRD/ 47 ADRA! Address Bus 48 ADRB/ Address Bus 49 ADR8/ 50 ADR9/ Address 51 ADR6/ 52 ADR7/ 53 ADR4/ 54 ADR5/ 55 ADR2/ 56 ADR3/ 57 ADRO/ 58 ADR1/ 59 DATE/ 60 DATF/ 61 DATC/ 62 DATD/ 63 DATA/ Data Bus 64 DATB/ Data Bus 65 DAT8/ 66 DAT9/ Data 67 DAT6/ 68 DAT7/ 69 DAT4/ 70 DAT5/ 71 DAT2/ 72 DAT3/ 73 DATO/ 74 DAT1/ 75 GND Signal GND 76 GND Signal GND 77 -10* -10 VDC 78 -10* -10 VDC Power 79 -12 -12 VDC 80 -12 -12 VDC Supplies 81 +5 +5 VDC 82 +5 +5VDC 83 +5 +5VDC 84 +5 +5VDC 85 GND Signal GND 86 GND Signal GND

*For MDS 800 compatibility.

15 APPENDIX B MUL TIBUS DC REQUIREMENTS

DRIVER LOAD PER BOARD BUS SIGNALS PULL-UP/DOWN LOCATION DRIVE (Min) LOCATION SOURCING (Max) RESISTOR INIT/ Master TTL, 32 mA All 1.8 mA None BCLK/, CCLK/ Master TTL, 48 mA Master 2.0mA 220/330,Q termination on Motherboard BRED/ Master TTL, 16 mA 2.0mA 1 k,Q pull-up on Motherboard BPRN/ Master TTL, 16 mA Master 2.0mA None BPRO/ Master TTL, 32 mA Master 2.0mA None BUSY/ Master OC, 20 mA Master 2.0mA 1.0 k,Q pull-up MRDC/, MWTC/ Master TRI, 32 mA Slave 2.0mA 1.1 k,Q pull-up

10RC/, 10WC/ Master TRI, 32 mA I/O Board 2.0mA 1.1 k,Q pull-up XACK/, AACK/ Slave TRI, 16 mA Master 2.0mA 510 ,Q pull-up DATF /-DAnA/ Master TRI, 15 mA Slave 0.5 mA 2.2 k,Q pull-up ADRF/-ADR0/ Master TRI, 15 mA Slave 0.5mA 2.2 k,Q pull-up

INH1/,INH2/ All ~C, 16 mA RAM, PROM, 2.0mA 1 k,Q pull-up Memory Mapped I/O INn/-INT0/ All OC,16 mA Master 2.0mA 1 k,Q pull-up

NOTES: 1. Input voltage levels: High 2.4V to 5.0V Low O.OV to O.BV 2. Output voltage level: High 2.0V to 5.25V Low O.OV to 0.45V OC - open collector TTL - totem-pole output TRI - three-state

3. Leakage current of an input ~40 p.A Leakage current of an output';; 100 p.A 4. Maximum number of Master devices = 16 using parallel priority network. 5. Maximum bus capacitance is 300 pF.

16 APPENDIX C GPSI INTERFACE SCHEMATIC AND WIRE LIST

(FOLDOUT)

17 GPSI WIRE LIST GENERAL-PURPOSE SLAVE BUS INTERFACE SIGNAL NAME BOTTOM SIGNAL NAME BOTTOM TOP

ADRO/ P1·57 A13·2 BASE ADR/ A9·5 A1·4 A1·4 A1·1 4' INTO/ ~ o_-~~;.;-~v:1------« XINTRO

ADR1/ P1·58 A9·1 RD/ A1·6 A11·15 A11·15 A1O·15 4' INT1/ ~ >------'-O(~I-:;-:-,------______---«XINTR' ADR2/ P1·55 A9·2 BD ENABLE/ A1·3 A3·15 A3·15 A11·1 39 INT'/ ~ o-----~o('A51_:,-.-::..------«XINTR' ADR3/ P1·56 A9·3 A11·1 A10·1 401NT3/ E----<> 0 ~------«XINTR3

ADR4/ P1·53 A8·1 8A7 A7·8 A2·9 371NT4/ ~ >----~1..,,5---==------·------«XINTR4

ADR5/ P1·54 A8·2 6A7 A7·6 A2·10 381NT5{ ~ '~ ~------(XINTR5 ADR6/ P1·51 A8·3 12A7 A7·12 A2·11 35 INT6/ E----<> >-__-.; (XINTR6 A5 ~~~I ,...______---«XINTR7 ADR8/ P1·49 A7·9 MMIO/ A4·3 A14·3 A14·3 A1·12 36 INT71 E---o 0-----_ AS "3 , ADR9/ P1·50 A7·10 A1·12 A1·10 ~~ ~~~~; )>------.::------?8I-'~-4L-SO-'------7) C/O 55 ADR2/ ADRA! P1·47 A7·11 4A14 A14·4 A6·1 A6·1 A6·3 56 ADR3/ - '5 o '5 ADRB/ P1·48 A7·3 11A1 A1·11 A2·1 A2·1 A2·2 53 ADR4/ o ~ AO OSO/ 54 ADRSI ! 1:0 ,~ A, , '4 DS1! -1 , '3 ADRC/ P1·45 A7·4 8A1 A1·8 A2·3 51 ADR6/ 3 A,' ,~ I A, oS2/ A2·3 A2·4 3~-o 3 12 OS3/ AB 4 P!;\-o A9 4 0S4/ ADRD/ lK rcc lK"tVcc :4 '0" P1·46 A7·5 12A2 A2·12 A14·9 A14·9 A13·5 ~4 5 5 OS5/ 6 p!%---o 6 9 E3 E3 6 OS6/ 5 6~--o 5 7 ADRE/ P1·43 A7·1 6A2 A2·6 A14·5 A14·5 A13·6 52 ADR71 )-0 E, 7 7 E, 7 oS7/ E, E, ADRF/ P1·44 A7·2 8A14 A14·8 1. 8205 A1·5 -t 8205 t MRDC/ P1·19 A1·13 CMD/ A13·4 A1·2 A1·2 9 74LS27 BASE ADRI A14·1 4Z) ,'\ORRI B MWTC/ P1·20 A1·9 2A14 A14·2 A12·9 E"O :'\0'19/ >-~A7 Vcc 47 ADAA/ " 3 9 74510 A4 IORC/ P1·21 A2·13 48 ADRB/ ," 6 '0 B 45 ADRC/ ~ A7 A, 3 IOWC/ P1·22 A2·5 4A4 46 ADRDI MMIO/ A4·4 A12·1 A12·1 A12·2 >--. "'r, " CCLK P1·31 A12·8 INIT A3·3 A3·4 43 ADRE/ , 44 ADRF/ A7 '2 INIT/ P1·14 A3·2 6A9 '3 3 A'4 4 A9·6 A4·2 7~ -=- , A ' XACK/ P1·23 A3·13 24 lNH1/ ~ 26 INH2/ ~47~A6 AACK/ P1·25 A3·11 VCC A4·16 74832 ~11 DATAO/ P1·73 A11·3 A8·16, A9·16, A11·16, A10·16, A12·14 19MRDC/ , 13 A, 74S32 1 74510 74504 9 A, l 20 MWTC! -='~ B ~65 A, RD/ DATA1/ P1·74 A11·6 , A,./ 9 A'4 A1·14, A2·14, A14·14, A3·16, A7·14 21 IORC/ , - ~" ~ '~~O 74504 DATA2/ P1·71 A11·10 A6·14, A5·14, A13·14 6 6 5 A'4 WAT/ 22 lowel , ~A, 5- 74532. DATA3/ P1·72 A11·13 5 ---l4LS02 CMO/ ~3, A, BD ENABLE/ ~A13 4 DATA4/ P1·69 A10·3 VSS A3·1, A7·13, A8·4, A9·4, A13·3 I ...... , ~ DATA5/ P1·70 A10·6 A8·8, A9·8, A11·8, A10·8, A12·7 A'4 ':cc , 74504 DATA6/ P1·67 A10·10 A1·7, A2·7, A14·7, A3·8, A7·7 ," A4 DATA7/ P1·68 A10·13 A6·7, A5·7, A13·7 9 , , eLR A8 0A 12 11 AACK/ DB 0- A3 DC ~ ~ '€8098 8 DO PARTS LIST 31 CCLK elK A12 0E DF ~ f-!;!;-....o 14 13 XACK/ A1 74S32 A8 8205 DG ~ A3 -4-- 74'64 °H f2L-o ~ A2 2 3 4· 5 74S10 A9 8205 14 INITI A3 A3 BO INIT/ A3 8098 A10 8226 ~ BO INIT 23 XACK! A4 1K-RP A11 8226 25 AACK/ ( '\' A5 7406 A12 74164 CS 4 3 01 0 , OBINO 73 DATAOI DBO 000 A6 7406 A13 74LS02 7 OBOUTO 6 DI, OBIN1 74 DATA1f 5 DB, A" DO, 9 OBoun A7 74LS27 A14 74S04 01 OBIN2 '0 8226 2 11 71 DATA2! DB, DO? OBOUT2 12 01 OBIN3 '3 3 ,. 72 DATAl DB3 DlENo03 OBOUT3

'5 , cs 4 3 010 OBIN4 69 DATA4! 000 , 080 7 DBOUTtI 01, OBIN5 6 5 70 DATASI OBOUT6 DB, A,O DO, 9 002 OUINII '0 8226 11 67 DATA6! DB2 01 2 12 onouro 01 3 OBIN] '3 '4 68 DATA7! )( DB3D1ENo03 OIJOUT7 y APPENDIX D

MECHANICAL SPECIFICATIONS

12.00 ±O.OOS 0.25 X 450 11.500 2 PLACES ~ ~, 0.25 0.25 ~0 01-.----- 0.109 DIA/ 3HOL ES

COMPONENT SIDE 5.950 iO.OOS D> 6.20

6.7 5 REF

[3> D> 01- ---- 1--1- 0.0 6R j;I HI ---nr T YP 0.55 L O. 30 I. 3.080 .1' ~ 0.390 I. 6.767 ±0.005 . 1. 4.570 0,015 ± 0.005 X 450 CHAMFER ALL 2 PLACES CONNECTOR EDGES 0.040 X 45°

NOTES:

BOARD THICKNESS: 0.062 EJECTOR TYPE: SCANBE #S203

MULTIBUS CONNECTOR: 8S-PIN. 0.156 SPACING 5. BUS DRIVERS AND RECEIVERS SHOULD BE LOCATED AS CLOSE AS POSSIBLE TO CDC VFBOl E43DOOA 1 THEIR RESPECTIVE MULTIBUS PIN CONNECTIONS VIKING 2VH43/1ANE5 6. BOARD SPACING: 0.6 AUXILIARY CONNECTOR: 60·PIN, 0.100 SPACING 7. COMPONENT HEIGHT: 0.435 CDC VPBOl B30DOOA 1 TI H311130 8. CLEARANCE ON CONDUCTOR NEAR EDGES: 0.050 AMP PE5·14559

18 Intel MULTI BUS Interfacing AP-28

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Abraham Lincoln Strasse 30 Box 20092 46-50 Beam Street 6200 Wiesbaden 1 S-16120 Bromma Nantwich, Cheshire CW5 5LJ Tel: (06121) 74855 Sweden Tel: (0270) 62 65 60 TELEX: 04186183 Tel: (08) 98 53 90 TELEX: 36620 Intel Semiconductor GmbH TELEX: 12261 0-7000 Stuttgart 80 Ernsthaldenstrasse 17 Tel: (0711) 7351506 ORIENT MARKETING OFFICES TELEX: 7255346 JAPAN TAIWAN Intel Japan Corporation- Taiwan Automation Co,- Flower HIII-Shinmachl East Bldg. 6th Floor, 18-1, Lane 14 1-23-9, Shlnmachi, Setagaya-ku Chi-Lin Road Tokyo 154 Taipei Tel: (03) 426-9261 Tel: {02} 551726-9 TELEX: 781-28426 TELEX: 11942 TAIAUTO INTERNATIONAL DISTRIBUTORS ARGENTINA DENMARK HONG KONG JAPAN (cont) SOUTH AFRICA S.I.E.S.A. Scandinavian Semiconductor ASTEC International Ryoyo Electric Corp. Electronic Buliding Elements Av. Pte. Rogue Saenz Pena 1142 9B Supply A/S Oriental Centre Konwa Bldg. P.O. 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Alfred Neye Enatachnik GmbH Tel: (01) 60 22 30 Eledra 3S S.P.A.· Inelco Nederland 220 Park Street Schillerstrasse 14 TELEX: 56788 0-2085 Quickborn-Hambuig Viale Elvezla, 16 AFD Elektronic South Melbourne, Victoria 3205 Tel: (04106) 6121 20154 Milan, Joan Muyskenweg 22 UNITED KINGDOM AUSTRIA TELEX: 02-13590 Tel: (02) 3493041 NL-1006 Amsterdam Rapid Recall, Ltd. Bacher Elektronische Gerate GmbH Electronic 2000 Vertriebs GmbH TELEX: 39332 Tel: (020) 934824 11-15 BeUerton Street MeidlJnger Hauptstrasse 76 Neumarkter Strasse 75 Eledra 3S S.PA· T~LEX: 14622 Drury Lane Via Paolo Galdano, 141 0 London WC2H 9BS A 1120 Vienna 0-8000 Muenchen 80 NORWAY Tel: (0222) 836396 Tel: (089) 434061 10137 Torino Tel: (01) 379-6741 TEL: (011) 30 97 097 - 30 97114 Nordisk Elektronik (Norge) A/S TELEX: 28752 TelEX: (01) 1532 TELEX: 522561 Mustads Vei 1 Eledra 3S S.PA· G.E.C. ,Semiconductors Ltd. BELGIUM Jermyn GmbH N-Oslo 2 Postfach 1146 Via Giuseppe Val marana, 63 East Lane Inelco Belgium SA Tel: (02) 55 38 93 Wembley HA9 7PP D-6277 Kamberg 00139 Rome, Italy TE.LEX: 16963 Avenue Val Duchesse, 3 Tel: (06434) 6005 Tel: (06) 81 27290 - 81 27324 Middlesex B-1160 Brussels TELEX: 484426 TELEX: 63051 PORTUGAL Tel: (01) 904-9303 Tel: (02) 660 00 12 ,Dltram TELEX: 923429 TELEX: 25441 JAPAN Componentes E Electronlca LOA Jermyn Industries Pan Electron Av. Miguel Bombarda, 133 Vestry Estate No.1 Higashlkata-Machi lisboa 1 Sevenoaks, Kent Mldorl-Ku, Yokohama 226 Tel: 11945313 Tel: (0732) 50144 Tel: (045) 471-8811 TELEX: 95142 TELEX: 781-4773 *Field Application Location inter

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