DOCSLIB.ORG

Introducing the Irmx® Operating Systems

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Introducing the Irmx® Operating Systems Introducing the iRMX® Operating Systems RadiSys Corporation 5445 NE Dawson Creek Drive Hillsboro, OR 97124 (503) 615-1100 FAX: (503) 615-1150 www.radisys.com 07-00634-01 December 1999 EPC, iRMX, INtime, Inside Advantage, and RadiSys are registered trademarks of RadiSys Corporation. Spirit, DAI, DAQ, ASM, Brahma, and SAIB are trademarks of RadiSys Corporation. Microsoft and MS-DOS are registered trademarks of Microsoft. IBM and PC/AT are registered trademarks of International Business Machines Corporation. Microsoft Windows and MS-DOS are registered trademarks of Microsoft Corporation. Intel is a registered trademark of Intel Corporation. All other trademarks, registered trademarks, service marks, and trade names are property of their respective owners. December 1999 Copyright 1999 by RadiSys Corporation All rights reserved. ii Quick Contents Chapter 1. Basic Concepts Chapter 2. Nucleus and Kernel Features Chapter 3. BIOS and EIOS Features Chapter 4. Human Interface Features Chapter 5. Application Loader Features Chapter 6. UDI Features Chapter 7. Networking Features Chapter 8. System Development Chapter 9. Application Debugging Chapter 10. System Configuration Appendix A. Related Publications Glossary Index Introducing the iRMX Operating Systems iii Notational Conventions Most of the references to system calls in the text and graphics use C syntax instead of PL/M (for example, the system call send_message instead of send$message). If you are working in C, you must use the C header files, rmx_c.h, udi_c.h, and rmx_err.h. If you are working in PL/M, you must use dollar signs ($) and use the rmxplm.ext and error.lit header files. This manual uses the following conventions: ✏ Note Notes indicate important information. LL! CAUTION Cautions indicate situations which may damage hardware or data. iv Contents 1 Basic Concepts iRMX Operating System Features................................................................... 2 Real-time Processing................................................................................ 2 Multitasking ...................................................................................... 3 Preemptive, Priority-based Scheduling ............................................. 4 Interrupt Processing........................................................................... 5 Predictable Response Time ............................................................... 6 Multiprogramming ............................................................................ 7 Objects and System Calls ......................................................................... 9 Intertask Coordination and Communication...................................... 10 Memory Pools and Memory Sharing................................................. 13 Virtual Memory Allocation With the Paging Subsystem .................. 14 System Calls...................................................................................... 14 Operating System Layers .................................................................. 15 Example Code and Demonstration Programs........................................... 16 Network Support ...................................................................................... 17 32-Bit Architecture, Addressing, and Protection...................................... 17 Bus Architecture Support ......................................................................... 19 iRMX for PCs Special Features....................................................................... 20 2 Nucleus and Kernel Features Nucleus Objects............................................................................................... 21 Jobs........................................................................................................... 22 Object Directories ............................................................................. 24 Memory Pools ................................................................................... 25 Tasks ........................................................................................................ 26 Memory Segments.................................................................................... 26 Buffer Pools and Heaps............................................................................ 27 Exchange Objects..................................................................................... 28 Mailboxes.......................................................................................... 28 Semaphores ....................................................................................... 28 Regions.............................................................................................. 30 Introducing the iRMX Operating System Contents v Ports .................................................................................................. 30 Extension Objects and Composite Objects............................................... 31 Object Directories, Tokens and Descriptors............................................. 32 Nucleus Task Scheduling ................................................................................ 33 Priority ..................................................................................................... 33 Execution State......................................................................................... 34 Round-robin Scheduling........................................................................... 35 Nucleus Interrupt and Exception Handling...................................................... 35 Interrupt Handlers .................................................................................... 36 Interrupt Handler Alone .................................................................... 36 Interrupt Handler/Task Combination................................................. 36 Exceptional Conditions ............................................................................ 37 Environmental and Programmer Errors............................................. 38 Hardware Exceptions ........................................................................ 38 Nucleus Messaging Service............................................................................. 39 Services............................................................................................. 39 Kernel Features ............................................................................................... 40 Kernel Objects.......................................................................................... 40 Kernel Task Management ........................................................................ 41 Kernel Time Management........................................................................ 41 Kernel Interrupt Handling ........................................................................ 41 When To Use the Kernel.......................................................................... 42 3 BIOS and EIOS Features I/O System Objects, Logical Names and System Calls ................................... 43 User Objects, Users and User Access Control.......................................... 43 Example: Multiuser System and the User Object............................. 44 Connections and File Access Modes ........................................................ 45 File Connections................................................................................ 45 Device Connections........................................................................... 46 I/O Jobs .................................................................................................... 46 Logical Names for Files and Devices (EIOS Only) ................................. 47 BIOS and EIOS System Call Differences ................................................ 47 System Call Names ........................................................................... 47 Synchronous and Asynchronous System Calls (BIOS Only) ............ 48 Files and Directories........................................................................................ 48 Hierarchical File System .......................................................................... 48 File Access Rights.................................................................................... 49 File Types................................................................................................. 50 Named Files ...................................................................................... 50 Remote Files ..................................................................................... 50 DOS Files.......................................................................................... 51 vi Contents CD-ROM Files.................................................................................. 51 Physical Files .................................................................................... 51 Stream Files....................................................................................... 51 Devices and Device Control ............................................................................ 52 Device Independence................................................................................ 52 File Drivers ....................................................................................... 53 Device Drivers .................................................................................. 53 Loading and Configuring Drivers.....................................................
Load more

Recommended publications
  • A Programmable Microkernel for Real-Time Systems∗
    A Programmable Microkernel for Real-Time Systems∗ Christoph M. Kirsch Marco A.A. Sanvido Thomas A. Henzinger University of Salzburg VMWare Inc. EPFL and UC Berkeley [email protected] tah@epfl.ch ABSTRACT Categories and Subject Descriptors We present a new software system architecture for the im- D.4.7 [Operating Systems]: Organization and Design— plementation of hard real-time applications. The core of the Real-time systems and embedded systems system is a microkernel whose reactivity (interrupt handling as in synchronous reactive programs) and proactivity (task General Terms scheduling as in traditional RTOSs) are fully programma- Languages ble. The microkernel, which we implemented on a Strong- ARM processor, consists of two interacting domain-specific Keywords virtual machines, a reactive E (Embedded) machine and a proactive S (Scheduling) machine. The microkernel code (or Real Time, Operating System, Virtual Machine microcode) that runs on the microkernel is partitioned into E and S code. E code manages the interaction of the system 1. INTRODUCTION with the physical environment: the execution of E code is In [9], we advocated the E (Embedded) machine as a triggered by environment interrupts, which signal external portable target for compiling hard real-time code, and in- events such as the arrival of a message or sensor value, and it troduced, in [11], the S (Scheduling) machine as a universal releases application tasks to the S machine. S code manages target for generating schedules according to arbitrary and the interaction of the system with the processor: the exe- possibly non-trivial strategies such as nonpreemptive and cution of S code is triggered by hardware interrupts, which multiprocessor scheduling.
    [Show full text]
  • Interrupt Handling in Linux
    Department Informatik Technical Reports / ISSN 2191-5008 Valentin Rothberg Interrupt Handling in Linux Technical Report CS-2015-07 November 2015 Please cite as: Valentin Rothberg, “Interrupt Handling in Linux,” Friedrich-Alexander-Universitat¨ Erlangen-Nurnberg,¨ Dept. of Computer Science, Technical Reports, CS-2015-07, November 2015. Friedrich-Alexander-Universitat¨ Erlangen-Nurnberg¨ Department Informatik Martensstr. 3 · 91058 Erlangen · Germany www.cs.fau.de Interrupt Handling in Linux Valentin Rothberg Distributed Systems and Operating Systems Dept. of Computer Science, University of Erlangen, Germany [email protected] November 8, 2015 An interrupt is an event that alters the sequence of instructions executed by a processor and requires immediate attention. When the processor receives an interrupt signal, it may temporarily switch control to an inter- rupt service routine (ISR) and the suspended process (i.e., the previously running program) will be resumed as soon as the interrupt is being served. The generic term interrupt is oftentimes used synonymously for two terms, interrupts and exceptions [2]. An exception is a synchronous event that occurs when the processor detects an error condition while executing an instruction. Such an error condition may be a devision by zero, a page fault, a protection violation, etc. An interrupt, on the other hand, is an asynchronous event that occurs at random times during execution of a pro- gram in response to a signal from hardware. A proper and timely handling of interrupts is critical to the performance, but also to the security of a computer system. In general, interrupts can be emitted by hardware as well as by software. Software interrupts (e.g., via the INT n instruction of the x86 instruction set architecture (ISA) [5]) are means to change the execution context of a program to a more privileged interrupt context in order to enter the kernel and, in contrast to hardware interrupts, occur synchronously to the currently running program.
    [Show full text]
  • Polycom Realpresence Collaboration Server (RMX) Deployment Guide for Maximum Security Environments
    [Type the document title] Military Unique Deployment Guide Version 8.3.0.J May 2014 | DOC2714B Polycom® RealPresence® Collaboration Server (RMX) 1500/2000/4000 Deployment Guide for Maximum Security Environments Polycom Document Title 1 Trademark Information POLYCOM® and the names and marks associated with Polycom's products are trademarks and/or service marks of Polycom, Inc., and are registered and/or common law marks in the United States and various other countries. All other trademarks are the property of their respective owners. Patent Information The accompanying product may be protected by one or more U.S. and foreign patents and/or pending patent applications held by Polycom, Inc. This software has achieved UC APL certification. This document provides the latest information for security-conscious users running Version 8.3.0.J software. The information in this document is not intended to imply that DoD or DISA certifies Polycom RMX systems. Support Information For support on your Polycom systems, contact Polycom Global Services at 1-888-248-4143 or go to the Polycom Support Contact page (http://support.polycom.com/PolycomService/support/us/support/ Contact_Us.html). Documentation Feedback Polycom appreciates your help as we work to improve its product documentation. Send your comment to [email protected]. © 2014 Polycom, Inc. All rights reserved. Polycom, Inc. 6001 America Center Drive San Jose CA 95002 USA No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of Polycom, Inc. Under the law, reproducing includes translating into another language or format.
    [Show full text]
  • Emerging Technologies Multi/Parallel Processing
    Emerging Technologies Multi/Parallel Processing Mary C. Kulas New Computing Structures Strategic Relations Group December 1987 For Internal Use Only Copyright @ 1987 by Digital Equipment Corporation. Printed in U.S.A. The information contained herein is confidential and proprietary. It is the property of Digital Equipment Corporation and shall not be reproduced or' copied in whole or in part without written permission. This is an unpublished work protected under the Federal copyright laws. The following are trademarks of Digital Equipment Corporation, Maynard, MA 01754. DECpage LN03 This report was produced by Educational Services with DECpage and the LN03 laser printer. Contents Acknowledgments. 1 Abstract. .. 3 Executive Summary. .. 5 I. Analysis . .. 7 A. The Players . .. 9 1. Number and Status . .. 9 2. Funding. .. 10 3. Strategic Alliances. .. 11 4. Sales. .. 13 a. Revenue/Units Installed . .. 13 h. European Sales. .. 14 B. The Product. .. 15 1. CPUs. .. 15 2. Chip . .. 15 3. Bus. .. 15 4. Vector Processing . .. 16 5. Operating System . .. 16 6. Languages. .. 17 7. Third-Party Applications . .. 18 8. Pricing. .. 18 C. ~BM and Other Major Computer Companies. .. 19 D. Why Success? Why Failure? . .. 21 E. Future Directions. .. 25 II. Company/Product Profiles. .. 27 A. Multi/Parallel Processors . .. 29 1. Alliant . .. 31 2. Astronautics. .. 35 3. Concurrent . .. 37 4. Cydrome. .. 41 5. Eastman Kodak. .. 45 6. Elxsi . .. 47 Contents iii 7. Encore ............... 51 8. Flexible . ... 55 9. Floating Point Systems - M64line ................... 59 10. International Parallel ........................... 61 11. Loral .................................... 63 12. Masscomp ................................. 65 13. Meiko .................................... 67 14. Multiflow. ~ ................................ 69 15. Sequent................................... 71 B. Massively Parallel . 75 1. Ametek.................................... 77 2. Bolt Beranek & Newman Advanced Computers ...........
    [Show full text]
  • Publication Title 1-1962
    publication_title print_identifier online_identifier publisher_name date_monograph_published_print 1-1962 - AIEE General Principles Upon Which Temperature 978-1-5044-0149-4 IEEE 1962 Limits Are Based in the rating of Electric Equipment 1-1969 - IEEE General Priniciples for Temperature Limits in the 978-1-5044-0150-0 IEEE 1968 Rating of Electric Equipment 1-1986 - IEEE Standard General Principles for Temperature Limits in the Rating of Electric Equipment and for the 978-0-7381-2985-3 IEEE 1986 Evaluation of Electrical Insulation 1-2000 - IEEE Recommended Practice - General Principles for Temperature Limits in the Rating of Electrical Equipment and 978-0-7381-2717-0 IEEE 2001 for the Evaluation of Electrical Insulation 100-2000 - The Authoritative Dictionary of IEEE Standards 978-0-7381-2601-2 IEEE 2000 Terms, Seventh Edition 1000-1987 - An American National Standard IEEE Standard for 0-7381-4593-9 IEEE 1988 Mechanical Core Specifications for Microcomputers 1000-1987 - IEEE Standard for an 8-Bit Backplane Interface: 978-0-7381-2756-9 IEEE 1988 STEbus 1001-1988 - IEEE Guide for Interfacing Dispersed Storage and 0-7381-4134-8 IEEE 1989 Generation Facilities With Electric Utility Systems 1002-1987 - IEEE Standard Taxonomy for Software Engineering 0-7381-0399-3 IEEE 1987 Standards 1003.0-1995 - Guide to the POSIX(R) Open System 978-0-7381-3138-2 IEEE 1994 Environment (OSE) 1003.1, 2004 Edition - IEEE Standard for Information Technology - Portable Operating System Interface (POSIX(R)) - 978-0-7381-4040-7 IEEE 2004 Base Definitions 1003.1, 2013
    [Show full text]
  • Additional Functions in HW-RTOS Offering the Low Interrupt Latency
    HW-RTOS Real Time OS in Hardware Additional Functions in HW-RTOS Offering the Low Interrupt Latency In this white paper, we introduce two HW-RTOS functions that offer the lowest interrupt latency available and help create a more software-friendly environment. One of these is ISR implemented in hardware, which improves responsiveness when activating a task from an interrupt and eliminates the need for developing a handler in software. The other is a function allowing the use of non-OS managed interrupt handlers in a multitasking environment. This makes it easier to migrate from a non-RTOS environment to a multitasking one. R70WP0003EJ0100 September, 2018 2 / 8 Multitasking Environment with Lowest Interrupt Latency Offered by HW-RTOS 1. Executive Summary In this white paper, we introduce two functions special to HW-RTOS that improve interrupt performance. The first is the HW ISR function. Renesas stylized the ISR (Interrupt Service Routine) process and implemented it in hardware to create their HW ISR. With this function, the task corresponding to the interrupt signal can be activated directly and in real time. And, since the ISR is implemented in the hardware, application software engineers are relieved of the burden of developing a handler. The second is called Direct Interrupt Service. This function is equivalent to allowing a non-OS managed interrupt handler to invoke an API. This function %" "$# $""%!$ $ $""%!$!" enables synchronization and communication "$ "$ between the non-OS managed interrupt handler and $($ $($ '$ '$ tasks, a benefit not available in conventional $ $ software. In other words, it allows the use of non-OS # $ % " "$) ) managed interrupt handlers in a multitasking $($ '$ environment.
    [Show full text]
  • N94-13338 1.1.1 3Rd NASA Symposium on VLSI Design 1991
    N94-13338 1.1.1 3rd NASA Symposium on VLSI Design 1991 Experience with Custom Processors in Space Flight Applications M. E. Fraeman, J. R. Hayes, D. A. Lohr, B. W. Ballard, R. L. Williams, and R. M. Henshaw Johns Hopkins University Applied Physics Laboratory Laurel, Maryland 20723 Abstract- APL has developed a magnetometer instrument for a Swedish satel- lite named Freja with launch scheduled for August 1992 on a Chinese Long March rocket. The magnetometer controller utilized a custom microprocessor designed at APL with the Genesil silicon compiler. The processor evolved from our experience with an older bit-slice design and two prior single chip efforts. The architecture of our microprocessor greatly lowered software development costs because it was optimized to provide an interactive and extensible pro- gramming environment hosted by the target hardware. Radiation tolerance of the microprocessor was also tested and was adequate for Freja's mission-- 20 kRad(Si) total dose and very infrequent latch-up and single event upset events. 1 Introduction The Johns Hopkins University Applied Physics Laboratory (APL) has developed a micro- processor that is well suited to one-of-a-kind embedded applications especially in satellite instrument control. The chip has been qualified for use in a magnetometer instrument for the Swedish Freja satellite. The processor's language directed architecture reduced Freja software costs because the flight hardware served as its own development system. Thus, unlike traditional interpreted programming languages like Basic, Lisp, or Smalltalk, our Forth language development system was fully supported on the embedded flight proces- sor. Performance was also equivalent or better than that obtained by other microprocessors programmed in languages like C with traditional cross-compilers and development systems.
    [Show full text]
  • Space Station Freedom Data Management System Growth and Evolution Report
    NASA Technical Memorandum 103869 Space Station Freedom Data Management System Growth and Evolution Report R. Bartlett, G. Davis, T. L. Grant, J. Gibson, R. Hedges, M. J. Johnson, Y. K. Liu, A. Patterson-Hine, N. Sliwa, H. Sowizral, and J. Yan N93-15k77 (NASA-TM- I03869) SPACE STATION FREEDOM DATA MANAGEMENT SYSTEM GROWTH ANO EVOLU TIr}N REPORT (NASA) Uncl as September 1992 66 P G3/17 0178407 National Aeronautics and Space Administration Z NASA Technical Memorandum 103869 Space Station Freedom Data Management System Growth and Evolution Report T. L. Grant and J. Yan, Ames Research Center, Moffett Field, California September 1992 RIASA National Aeronauticsand Space Administration Ames Research Center MoffettField, CaJifomia94035-1000 The Study Team The Data Management System (DMS) analysis team Digital Equipment Corporation, Moffett Field, CA consists of civil servants and contractors at NASA Ames Roger Bartlett Research Center, Information Sciences Division. Prof. Joanne Bechta Dugan provided the reliability Intelligent Systems Technology Branch, Ames analysis of the DMS network reported in appendix B; she Research Center, Moffett Field, CA used the HARP code and the work was sponsored by Gloria Davis Langley Research Center (LaRC). Members of the Failure Terry Grant Tolerance/Redundancy Management Working Group Bob Hedges provided network failure information and preliminary Y. K. Liu models that aided our study of the failure tolerance of the Dr. Ann Patterson-Hine DMS network. Nancy Sliwa We also acknowledge the following individuals for Sterling Federal Systems, Inc., Palo Alto, CA reviewing early versions of the manuscripts: Dr. Jerry Yah Gregg Swietek (NASA Headquarters), Mike Pasciuto (NASA), Donald Woods (McDonnell Douglas Space Research Institute for Advanced Computational Systems Company (MDSSC)) and George Ganoe Science, Moffett Field, CA (NASA LaRC).
    [Show full text]
  • Polycom RMX™ 2000/4000 Administrator's Guide
    Polycom RMX™ 2000/4000 Administrator’s Guide Version 5.0 | December 2009 | DOC2518B Trademark Information Polycom®, the Polycom “Triangles” logo, and the names and marks associated with Polycom’s products are trademarks and/or service marks of Polycom, Inc., and are registered and/or common-law marks in the United States and various other countries. All other trademarks are the property of their respective owners. Patent Information The accompanying product is protected by one or more U.S. and foreign patents and/or pending patent applications held by Polycom, Inc. Portions, aspects and/or features of this product are protected under United States Patent Law in accordance with the claims of United States Patent No: US 6,300,973; US 6,492,216; US 6,496,216; US 6,757,005; US 6,760,750; US 7,054,620; US 7,085,243; US 7,113,200; US 7,269,252; US 7,310,320. PATENT PENDING © 2009 Polycom, Inc. All rights reserved. Polycom, Inc. 4750 Willow Road Pleasanton, CA 94588-2708 USA No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of Polycom, Inc. Under the law, reproducing includes translating into another language or format. As between the parties, Polycom, Inc., retains title to and ownership of all proprietary rights with respect to the software contained within its products. The software is protected by United States copyright laws and international treaty provision. Therefore, you must treat the software like any other copyrighted material (e.g., a book or sound recording).
    [Show full text]
  • Irmx Installation and Startup
    iRMX® Installation and Startup RadiSys Corporation 5445 NE Dawson Creek Drive Hillsboro, OR 97124 (503) 615-1100 FAX: (503) 615-1150 www.radisys.com 07-0683-01 December 1999 EPC, iRMX, INtime, Inside Advantage, and RadiSys are registered trademarks of RadiSys Corporation. Spirit, DAI, DAQ, ASM, Brahma, and SAIB are trademarks of RadiSys Corporation. Microsoft and MS-DOS are registered trademarks of Microsoft Corporation and Windows 95 is a trademark of Microsoft Corporation. IBM and PC/AT are registered trademarks of International Business Machines Corporation. Microsoft Windows and MS-DOS are registered trademarks of Microsoft Corporation. Intel is a registered trademark of Intel Corporation. All other trademarks, registered trademarks, service marks, and trade names are property of their respective owners. December 1999 Copyright 1999 by RadiSys Corporation All rights reserved. ii Quick Contents Section I. Choosing Your Installation Chapter 1. Introduction Section II. iRMX Installation Procedures Chapter 2. Installing on iRMX development/target systems that are PC-compatible Platforms with no DOS Chapter 3. Installing on iRMX development/target systems that are PC-compatible Platforms with DOS Chapter 4. Installing on iRMX Development/Target Systems that are Multibus II Platforms Chapter 5. Installing the iRMX III OS on Multibus I Systems Chapter 6. Installing on Windows NT systems used as iRMX development systems Section III. iRMX Getting Started Chapters Chapter 7. DOSRMX Specifics Chapter 8. iRMX for PCs Specifics Chapter 9. Getting Acquainted with the Operating System Chapter 10. Where To Go From Here Section IV. Appendices Appendix A. Installed Directories Appendix B. Limitations Appendix C. Configuration Requirements for PC Platforms Appendix D.
    [Show full text]
  • Interrupt Handling
    ,ch10.10847 Page 258 Friday, January 21, 2005 10:54 AM CHAPTER 10 Chapter 10 Interrupt Handling Although some devices can be controlled using nothing but their I/O regions, most real devices are a bit more complicated than that. Devices have to deal with the external world, which often includes things such as spinning disks, moving tape, wires to distant places, and so on. Much has to be done in a time frame that is differ- ent from, and far slower than, that of the processor. Since it is almost always undesir- able to have the processor wait on external events, there must be a way for a device to let the processor know when something has happened. That way, of course, is interrupts. An interrupt is simply a signal that the hardware can send when it wants the processor’s attention. Linux handles interrupts in much the same way that it handles signals in user space. For the most part, a driver need only register a handler for its device’s interrupts, and handle them properly when they arrive. Of course, underneath that simple picture there is some complexity; in particular, interrupt handlers are somewhat limited in the actions they can perform as a result of how they are run. It is difficult to demonstrate the use of interrupts without a real hardware device to generate them. Thus, the sample code used in this chapter works with the parallel port. Such ports are starting to become scarce on modern hardware, but, with luck, most people are still able to get their hands on a system with an available port.
    [Show full text]
  • Internet Address Space: Economic Considerations in the Management of Ipv4”, OECD Digital Economy Papers, No
    Please cite this paper as: OECD (2008-06-18), “Internet Address Space: Economic Considerations in the Management of IPv4”, OECD Digital Economy Papers, No. 145, OECD Publishing, Paris. http://dx.doi.org/10.1787/230461618475 OECD Digital Economy Papers No. 145 Internet Address Space ECONOMIC CONSIDERATIONS IN THE MANAGEMENT OF IPV4 OECD DSTI/ICCP(2007)20/FINAL FOREWORD The report provides an analysis of economic considerations associated with the transition from IPv4 to IPv6. It provides background analysis supporting the forthcoming ICCP-organised Ministerial-level meeting on ―The Future of the Internet Economy‖, to take place in Seoul, Korea on 17-18 June 2008. This report was prepared by Ms. Karine Perset of the OECD‘s Directorate for Science Technology and Industry. It was declassified by the ICCP Committee at its 54th Session on 5-7 March 2008. It is published under the responsibility of the Secretary-General of the OECD. This paper has greatly benefited from the expert input of Geoff Huston from APNIC, David Conrad from the IANA, Patrick Grossetête from CISCO Systems, Bill Woodcock from Packet Clearing House, Marcelo Bagnulo Braun from the University of Madrid, Alain Durand from Comcast, and Vincent Bataille from Mulot Déclic, although interpretations, unless otherwise stated, are those of the author. 2 DSTI/ICCP(2007)20/FINAL TABLE OF CONTENTS FOREWORD ................................................................................................................................................... 2 MAIN POINTS ..............................................................................................................................................
    [Show full text]