1 INTRODUCTION TO ASIC OUTLOOK 1998

ASSPs AND ASICs

The term ASIC (Application Specific IC) has been a misnomer from the very beginning. ASICs, as now known in the IC industry, are really customer specific ICs. In other words, the gate array or standard cell device is specifically made for one customer. ASIC, if taken literally, would mean the device is created for one particular type of system (e.g., a disk-drive), even if this device is sold to numerous customers and/or is put in the IC manufacturerÕs catalog.

Currently, a device type that is sold to more than one user, even if it is produced using ASIC tech- nology, is considered a standard IC. Thus, we are left with the following nomenclature guidelines (Figure 1-1).

ASIC: A device produced for only one customer. PLDs are included as ASICs because the customer “programs” that device for its needs only.

CSIC: What ASICs should have been called from the beginning. Some companies differentiate an ASIC from a CSIC by who completes or is responsible for the majority of the IC design effort. If it is the IC producer, the part is labeled a CSIC, if it is the end-user, the device is called an ASIC. This term is not currently used very often in the IC industry.

ASSP: Application Specific Standard Product is a relatively new term for ICs targeting specific types of systems. In many cases the IC will be manufactured using ASIC technology (e.g., gate or linear array or standard cell techniques) but will ultimately be sold as a standard device type to numerous users (i.e., put into a product catolog). If the end-user helped the IC producer design the ASSP, that user is typically given a market leadtime (i.e., window of opportunity) to use the device before it is made available to its competitors.

CSP: Customizable Standard Products are 70 to 90 percent standard with 10 to 30 percent of the chip available for user-specified logic, memory, or peripheral functions. A CSP can be an ASIC device if it is sold to only one customer.

Source: ICE 19181C

Figure 1-1. ASIC Industry Terminology

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One problem many IC producers have run into while producing ASSPs (Application Specific Standard Products) is that in order to provide the optimum part, the IC producer must understand the system application at least as well as the end-user. Because this system-level expertise is not easy to acquire, most ASSP vendors have formed close relationships or partnerships with end- users. In this way, the IC vendor and end-user work closely together early in the system design cycle in order to properly define the ASSP device.

In general, as standard ICs take aim at ever finer segments of the marketplace, they ultimately evolve into ASSPs. In other words, at some point in time there could be very few standard ICs; most devices produced would be aimed at specific system needs. An example would be certain DRAMs architecturally optimized for a hand-held telecom system, laptop PC, or HDTV set. This is precisely the direction the IC industry is heading.

As IC producers customize their devices for specific system needs, the list of ICs labeled as ASSPs continues to expand. In 1997, Alcatel-Mietec introduced an ARM core-based ISDN chip-set (Figure 1-2). The chip-set is produced using a 3V, 0.5µ CMOS mixed-signal process. It doesnÕt take too much imagination to visualize a one-chip ASSP solution sometime in the near future. Twenty years from now there may be few ÒstandardÓ ICs produced.

AGND Analog Proprietary (DSP) JTAG Support Filter Engine TAP

Interface ROM

D/A Logic RAM ARM7TDMI Core A/D Serial

Port

Pulse Shaper S-Interface GCI Logic Logic Detector

Source: Alcatel-Mietec/EET 22707

Figure 1-2. Network-Termination Device Borrows ARM CPU

A couple of years ago, Motorola introduced the concept of the CSP (Figure 1-3). As was shown in Figure 1-1, the CSP product allows a small portion of user-specific logic to be introduced into a standard product design. The customized logic can be CFBÕs (complex function blocks; e.g., an ATM cell processor) or other circuitry from MotorolaÕs standard cell or gate array libraries.

Basically, an ASSPÕs circuitry is entirely designed by the IC producer. A CSP device always con- tains some of the end usersÕ unique circuit design or circuit interconnection.

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ASSP Application MC92xxx Specific Standard CFB Product CSP Customizable Platform Diffused Memory Customizable Architectures Standard Standard Product User-Specific Logic

CFB-Library CFBs- CSP Elements Application Customizable Driven Standard USL Product

Source: Integrated System Design/Motorola 21034

Figure 1-3. MotorolaÕs CSP Design Flow

A CSP is usually classified as an ASIC device because it is sold only to the customer that defined the unique circuitry portion of the chip. Moreover, like an ASIC device, MotorolaÕs CSP program has NREÕs (starting at $100K) and design cycle times that are typically about 90 days.

Although the 1996 ASIC market was about $17.6 billion, the ASSP-type products (which are part of the special purpose MOS Logic category) are taking away some of its momentum (Figure 1-4). Overall, the ASIC market is forecast to follow total IC industry growth rates fairly closely.

8 7.39

7 Ð13% 24% 6.41 Ð6% 5.98 6.15 6 26%

5 4.74

26% 4 3.75

3 Billions of Dollars

2

1

0 1992 1993 1994 1995 1996 1997 (FCST) Year

Source: ICE 20204D

Figure 1-4. Special Purpose MOS Logic Market (1992-1997)

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Does the proliferation of ASSPs and more customer-specific standard products mean an end to the ASIC market? No. This is because most of the pros and cons of ASICs versus ASSPs or standard products still exist.

The primary advantage of ASSPs or standard products is the ability to immediately (most of the time) purchase the ICs and get the system to market quickly. However, ASIC devices allow the system producer to differentiate its product from the competition. The result is that many times the system producer is able to gain marketshare and/or better profit margins.

In some cases standard products and ASICs are merging in an attempt to offer the benefits of both approaches. In 1993, TI announced that it was merging an enhanced version of its standard fixed- point TMS320C25 DSP chip and 15,000 usable and customizable 0.8-micron CMOS gate-array gates on one device. Thus, the user is able to take advantage of well characterized high-perfor- mance DSP circuitry while at the same time adding unique features to give its system a differen- tial advantage over its competitors. About 35 percent of TIÕs total DSP IC sales in 1996 were in a customizable version. This percentage is expected to rise to over 50 percent in 2001.

Another gray area is where Cirrus Logic takes one of its ASSP ICs and customizes a portion of it for one of its customers. Typically only about 5-10 percent of the new design is customized for the end-user. This ÒtweakedÓ device is still normally classified as an ASSP since the majority of the circuitry is still ASSP-based.

There is no question that the IC industry will continue to evolve toward devices that are specifi- cally suited for the customersÕ needs. ICE believes that various versions of ASICs (e.g., CSPs) and ASSPs will co-exist to help serve those needs in the most economical and efficient manner possible.

ASIC DEFINITIONS

Some basic definitions and classifications are shown below in order to define what ICE means when using the various terms used to describe todayÕs ASIC devices. ASIC stands for Application Specific Integrated Circuit and according to ICEÕs definition includes gate arrays, standard cells (sometimes called cell-based), full custom, and programmable logic devices (PLDs). These devices are classified as either semicustom, custom, or PLDs. Formal definitions are given in Figure 1-5 and diagrammed in Figure 1-6.

ICE does not include ASSPs in its ASIC market figures. An example of an ASSP part that is not classified as an ASIC by ICE is HitachiÕs H8/300H Series of microcontrollers. Although the H8/300H user is able to customize this MCU using an extensive Hitachi cell library, the finished devices are almost always allowed to be sold to other Hitachi customers after a certain period of time (Motorola has a similar program using its 68HC05 MCUs).

1-4 INTEGRATED CIRCUIT ENGINEERING CORPORATION Introduction to ASIC Outlook 1998

I. ASIC Semicustom IC - A monolithic circuit that has one or more customized mask layers, but does not have all mask layers customized, and is sold to only one customer.

Gate Array - A monolithic IC usually composed of columns and rows of transistors (organized in blocks of gates). One or more layers of metal interconnect are used to customize the chip. Sometimes called an uncommitted logic array (ULA).

Linear Array - An array of transistors and resistors that performs the functions of several linear ICs and discrete devices.

II. ASIC Custom IC - A monolithic circuit that is customized on all mask layers and is sold to only one customer. "System-on-a-chip" devices are typically custom ICs.

Standard Cell IC - A monolithic IC that is customized on all mask levels using a cell library that embodies pre-characterized circuit structures. ICs that are designed with a silicon compiler are included in this category. Most "embedded" arrays are included in this category because all mask layers are customized.

Full Custom IC - A monolithic IC that is at least partially "handcrafted". Handcrafting refers to custom layout and connection work that is accomplished without the aid of a silicon compiler or standard cells.

III. ASIC Programmable Logic Device (PLD) - A monolithic circuit with fuse, antifuse, or memory cell-based circuitry that may be programmed (customized), and in some cases, reprogrammed by the user (in-system or prototype form).

Simple PLD (SPLD) - Usually a PAL or PLA, typically contains less than 750 logic gates.

Complex PLD (CPLD) - A hierarchical arrangement of multiple PAL-like blocks.

Field Programmable Gate Array (FPGA) - A PLD that offers fully flexible interconnects, fully flexible logic arrays, and requires functional placement and routing.

Electrically Programmable Analog Circuit (EPAC) - A PLD that allows the user to program and reprogram basic analog functions.

IV. ASSP - A relatively new term for ICs targeting specific types of systems. In many cases the IC will be manufactured using ASIC technology (e.g., gate or linear array or standard cell techniques) but will ultimately be sold as a standard type to numerous users (i.e., put into a product catalog). If the end-user helped the IC producer design the ASSP, that user is typically given a market leadtime (i.e., window of opportunity) to use the device before it is made available to its competitors.

Source: ICE 13660H

Figure 1-5. ASIC/ASSP Definitions

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Final masks or e-beam definition Channeled

Semicustom Laser deposited (Gate arrays and interconnections linear arrays)

Channelless Laser etched interconnections

Embedded Standard arrays* cell

ASIC Custom CSP**

Full custom

Fuse Writable Antifuse***

OTP EPROM

EPROM

EEPROM Writable/ PLD FPGA erasable Flash memory

Ferroelectric * Classification depends upon number of mask layers customized EPAC ** Typically uses hand-crafted or cell-based technology for the customizable portion of the device

*** Includes amorphous silicon Volatile SRAM

Source: ICE 15247G

Figure 1-6. ASIC Technology Tree

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Motorola also has its ÒFlexCoreÓ program that allows the end-user to use its 32-bit MPUs as cores in cell-based designs. This program is significantly different from its, and HitachiÕs, MCU ASSP offerings in that the finished devices will most likely stay proprietary to the original customer. Thus, these devices are considered to be standard cell ASICs.

The FlexCore- and CSP-type ASIC programs* are prime examples of why ASSPs will not eliminate the market for ASICs. As was mentioned earlier, ASSPs will still hold an advantage in time-to- market, but they will never be able to compete with the product differentiation capability of robust ASIC offerings such as FlexCore and CSP.

Another ASIC segment that needs additional clarification and discussion is the PLD category. ICE includes under the generic term PLD the simple bipolar fuse-programmable PAL devices (e.g., the 22V10) produced by AMD and TI, the complex programmable (CPLD) devices (that typically have configurable macrocells, multiple feedback paths, etc.) that are usually MOS memory cell-based, and that are called field programmable gate arrays (FPGAs).

The FPGAs are produced using MOS memory cell (and thus are usually reprogrammable) or anti- fuse technology. The physical (e.g., line lengths) and electrical characteristics of the interconnects are unknown before programming, just like a gate array.

As was shown, the PLD classification now encompasses a broad range of products and most people in the IC industry are aware that the term PLD is no longer synonymous with the obsolete bipolar fuse-programmable PAL.

Another definitional clarification that should be mentioned is in the standard cell category. Many of the standard cell designs produced in the ASIC industry use a combination of pre-characterized and ÒhandcraftedÓ circuit structures. ICE categorizes an ASIC that has 50 percent or more of its circuitry composed of cells as a standard cell IC. If less than 50 percent of the circuitry is from pre- characterized cells (with the majority of the design being handcrafted), the IC is considered a full custom ASIC.

Another device that deserves some further discussion is the embedded array ASIC. When design- ing with this device, the customer first identifies any megacell functions that will be needed. The ASIC producer optimizes the layout of the cell-based design and then begins producing base wafers. While the base wafers are being fabricated, the customer is finishing design work for the uncom- mitted random logic area (gate array portion) that was set aside in the initial design. After the base wafer is finished being processed, the gate array area of the ICs on the base wafer is metallized.

* Zilog has a similar program for its Z80 MCU devices.

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The ultimate goal of the parallel random logic design and cell-based wafer fabrication efforts of the embedded array program is to shorten the turnaround time encountered with standard cell devices. Many embedded array producers are achieving turnaround times very close to those of gate arrays.

Although both standard cell and gate array design and fabrication techniques are used on the embedded array, because all of the mask layers of the device are customized for the user, ICE will classify the embedded array ASICs (e.g., VLSI TechnologyÕs Flex-Arrays) as standard cells.

Throughout ÒASIC Outlook 1998Ó AVAILABLE, TOTAL OR RAW GATES The number of unconnected gates on a device. ICE uses terms such as available, USABLE OR WIREABLE GATES total, raw, and usable when refer- The number of gates that can typically be interconnected implementing an "average" design. Usable gate count will ring to gate densities. Figure 1-7 always be less than the number of available, total, or raw shows the definitions followed by gates. ICE in regard to gate count. Typical Source: ICE 16779A usable gate counts for various Figure 1-7. Gate Count Definitions ASICs are shown in Figure 1-8.

ASIC Type Usable Gate Percentage

Double-Level Metal MOS PLD 30 - 50

Triple-Level Metal MOS PLD 60 - 70

Double-Level Metal Channelled Gate Array 85 - 95

Double-Level Metal Channelless Gate Array 40 - 50

Triple-Level Metal Channelless Gate Array 60 - 70

Four-Layer Metal Channelless Gate Array 40 - 60*

Five-Layer Metal Channelless Gate Array 60 - 70*

Standard Cell 85 - 95

Full Custom 100

*For devices with more than one million total gates

Source: ICE 16780C

Figure 1-8. Sampling of Usable Gate Counts

As total gate densities have increased, the IC manufacturer has had to go to a greater number of interconnect levels (i.e., metal layers) to keep die size and usable gate count percentages reason- able (Figure 1-9). This has been especially evident with the new triple-level metal PLDs. The new PLD technologies are helping reduce PLD die size dramatically, and in turn, significantly reduce manufacturing costs.

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6

5

4

3 Metal Layers

2

1

0 Usable Gates ≤10K >10K - ≤50K >50K - ≤1M >1M - ≤5M >5M Year Introduced 1974 1980 1986 1994 - 1996 1997 - 1999 *Gate Array and Standard Cell Source: ICE 18530D

Figure 1-9. ASIC* Metal Layer Trends

Of course the move to a greater number of metal layers comes with cost and complexity problems. With an increasing number of ASIC designs being pad limited (i.e., the die size is dictated by the number of I/O pads rather than the logic gate area) the move to more layers of metal has pro- ceeded very slowly in the ASIC user base.

ASIC PRODUCT LIFECYCLE

Figure 1-10 shows the 1997 location of each of the major ASIC families on the product lifecycle curve. It is interesting to note that most of the classifications still reside on the growth side of the curve. As the ASIC market matures, the majority of the ASIC product types will be in or approaching the maturity stage of their lifecycles in the late 1990Õs.

Low density (i.e., less than 10,000 gates) gate arrays are considered to be in the saturation/decline stage. Currently, many gate array vendors are shying away from accepting designs for low gate count arrays. As veteran IC buyers know, once products enter the latter stages of the lifecycle, price becomes a secondary concern to availability. Likewise, bipolar TTL PALs are quickly losing marketshare and are now entirely in the decline stage. As shown, replacement products for the bipolar TTL PAL and low-density gate array, such as MOS PLDs, are currently in the introduction or growth/maturity stage.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 1-9 Introduction to ASIC Outlook 1998 s e l a S

Introduction Growth Maturity Saturation Decline and Obsolescence

PLD W/Memory Bipolar PLDs EPLD EPAC EEPLD Flash-PLD SRAM-PLD Antifuse PLD Full CMOS Gate Array CMOS Gate Array Custom (≥500,000 Gates) (≥100,000 and <500,000 Gates) CMOS Gate Array (≥20,000 and <100,000 Embedded-DRAM Gates) Mixed CMOS Gate Array Standard Cell Analog/Digital (<20,000 Gates) Standard Cell Digital Standard Cell

Embedded Arrays ECL Gate Arrays

GaAs Gate Array BiCMOS Analog Gate Array Arrays GaAs Standard Cell

Source: ICE 11642U

Figure 1-10. 1997 ASIC Products Lifecycle

CONCLUSIONS

Overall, ASICs are still considered ÒtechnologyÓ drivers (Figure 1-11) for many aspects of the IC industry. While DRAMs, SRAMs, and flash memory will be the IC process drivers for the fore- seeable future, ASICs will drive most of the IC industryÕs advances in flexible IC manufacturing, CAD tools and software, packaging technology, testing methodologies, as well as customer design support/service. With so many critical technologies being driven by ASIC needs, it is obvious that future standard IC advancements will heavily depend upon ASIC technology.

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DRAM PROCESS DRIVERS EPROM SRAM

MATERIALS GAS AND FEATURE (e.g., WAFERS CHEMICAL HIGH-VOLUME FABRICATION SIZE AND METALS) PURITY MANUFACTURING EQUIPMENT

TECHNOLOGY DRIVERS ASICs

CUSTOMER CAD DESIGN IC FLEXIBLE TESTING SUPPORT/ TOOLS SOFTWARE PACKAGING MANUFACTURING SERVICE

Source: ICE 15308A

Figure 1-11. ÒDriversÓ in the Industry

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