Test Mode Matrix Circuit for an Embedded Microprocessor Core

Europaisches Patentamt (19) European Patent Office Office europeeneen des brevets £P 0 758 1 1 3 A1

(12) EUROPEAN PATENT APPLICATION

(43) Date of publication: (51) Intel e G06F 11/267 12.02.1997 Bulletin 1997/07

(21) Application number: 96305207.1

(22) Date of filing: 16.07.1996

(84) Designated Contracting States: • Colyer, Peter Stewart DE FR GB Essex Junction, VT 05453 (US) • Stauffer, David Robert (30) Priority: 07.08.1995 US 511943 Milton, VT 05468 (US)

(71) Applicant: International Business Machines (74) Representative: Bailey, Geoffrey Alan Corporation IBM United Kingdom Limited Armonk, N.Y. 10504 (US) Intellectual Property Department Hursley Park (72) Inventors: Winchester Hampshire S021 2JN (GB) • Cherichetti, Cory Ansel Burlington, VT 05401 (US)

(54) Test mode matrix circuit for an embedded microprocessor core

(57) A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the circuit to be tested integrated fully functionally \ using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in- circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit in number of operates a mutually ex- D-tO—'o I clusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices TEST MODE MATRIX may also be implemented on the same integrated circuit. -J-4-- U « .4

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Description connection points which are coupled to the connections points of the microprocessor, and which emulates mi- BACKGROUND OF THE INVENTION croprocessor operation while providing advanced debugging capabilities. A stand-alone microprocessor 1. TECHNICAL FIELD 5 may thus be removed in an embedded system and re- placed with an ICE during the debugging of the system This invention generally relates to integrated cir- hardware and software. However, when a microproces- cuits, and more specifically relates to application-spe- sor is implemented within an ASIC, the connection cific integrated circuits (ASICs) which have one or more points to the microprocessor are buried within the ASIC embedded microprocessor cores, which allow for test- 10 logic. One way to use an ICE with a microprocessor em- ing the microprocessor core with standard test vectors, bedded within an ASIC is to bring all the microprocessor and which allow for using an in-circuit emulator (ICE) in I/O to external I/O pins on the ASIC device. However, debugging the software for each microprocessor core. for most applications, the majority of microprocessor I/ O signals are not needed at the external I/O pins during 2. BACKGROUND ART is normal operation. Adding all the microprocessor I/O signals as I/O pins on the ASIC device, which are used only Modern electronic systems often incorporate em- during development of the ASIC, would greatly increase bedded microprocessors or microcontrollers. With the the packaging size for the ASIC, thereby substantially push for higher levels of integration and performance, increasing its cost. This method of providing external I/ the trend has been to embed a microprocessor or mi- 20 o pins on an ASIC for using an ICE with an embedded crocontroller (referred to hereinafter generically as mi- microprocessor generally is not a cost-effective solu- croprocessor) within an application specific integrated tion. In addition, for applications that require two or more circuit (ASIC). The resulting ASIC contains the micro- embedded microprocessor cores within an ASIC, pro- processor "core" plus application-specific logic pack- viding all the appropriate microprocessor I/O signals on aged on a single chip. 25 external I/O pins would result in an unworkable number Since the microprocessor core within an ASIC typ- of I/O pins. ically interfaces only to logic within the ASIC, it is typi- Various architectures are known for embedding a cally not necessary during normal operation to connect microprocessor core within an ASIC. For example, U.S. input/output (I/O) signals from the microprocessor core Pat. No. 5,254,940 Testable Embedded Microprocessor to the primary I/O (Le., off -chip) drivers/receivers of the 30 and Method of Testing Same (issued 10/19/93 to Oke ASIC. However, when microprocessor I/O is not acces- etal. and assigned to LSI Logic Corp.) discloses a meth- sible outside of the ASIC chip, the microprocessor core od of embedding a microprocessor core such that mi- within the ASIC becomes much more difficult to test. croprocessor I/O are driven off -chip only when the ASIC Typically, stand-alone microprocessors are tested by is configured into a special test mode. FIG. 1 herein is applying a set of test vectors to the inputs, and monitor- 35 a reproduction of FIG. 2 in the Oke et al. patent. During ing the outputs for expected responses. These sets of normal operation, chip output pads 214 are used for sig- test vectors are often referred to as Architectural Verifi- nals to/from the application-specific logic. This circuit cation Patterns (AVPs). When the microprocessor is 200 permits the embedded microprocessor 204 to be embedded within ASIC logic, it is no longer possible to tested using the standard AVPs developed for the stand- use the AVPs developed for the stand-alone microproc- 40 alone microprocessor. The Oke et al. circuit is limited, essor. New AVPs, which account for the behaviour of however, in that an ICE cannot be substituted for the the embedded microprocessor plus the application-spe- embedded microprocessor. In addition, the Oke et al. cific logic, could be developed. However, this would re- circuit is limited to unidirectional signals, and does not quire new and unique AVPs for each ASIC. The devel- provide a solution for bidirectional I/O lines. opment of AVPs for a semiconductor device is a very 45 Another design for embedding a microprocessor expensive and time-consuming process, and generat- within an ASIC is described in U.S. Pat. No. 5,304,860 ing new AVPs for each ASIC device would thus substan- "Method for Powering Down a Microprocessor Embed- tially increase the development costs for each device. It ded within a Gate Array" (issued 4/1 9/94 to Ashby et al. is therefore desirable to provide a way to test a micro- and assigned to Motorola, Inc.). FIG. 2 herein is a re- processor core implemented within an ASIC using the so production of FIG. 7 of the Ashby et al. patent. The Ash- standard AVPs developed for the stand-alone micro- by et al. patent describes a method of embedding the processor. microprocessor core such that the embedded micro- Another complication that results from embedding processor core and the application-specific logic can be a microprocessor core in an ASIC relates to the testing isolated from each other. The circuit of Ashby et al. per- of the software that runs on the embedded microproc- 55 mits the embedded microprocessor core to be tested us- essor core. Typically, software for microprocessors is ing standard AVPs, and permits the connection of an tested and integrated with the hardware using a test tool ICE to emulate the embedded microprocessor. The cir- called an in-circuit emulator (ICE). An ICE typically has cuit is limited, however, in making all microprocessor I/

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O signals coupled to the application-specific logic ac- operational signals directly to the logic circuit, for routing cessible to I/O pins during all modes of operation. The microprocessor test signals to the microprocessor, and increased I/O pin requirement typically increases the for routing logic test signals to the logic circuit; routing size of the chip, the size of the package, and hence the the microprocessor test signals from an external tester; cost of the ASIC. The problem of excessive pinout be- 5 and applying test vectors to the microprocessor through comes even more significant for ASICs that have more the signal routing means. than one embedded microprocessor core. Another sig- Thus a test mode matrix circuit for an integrated cir- nificant disadvantage is that all connections between cuit such as an ASIC is provided which controls the rout- the embedded microprocessor and the application-spe- ing of signals on the integrated circuit device. The func- cific logic is always via an off-chip driver 54 and match- 10 tion of the test mode matrix circuit is determined by the ing receiver 58. The propagation delay of an off-chip state of control inputs. When the control inputs are con- driver and receiver is much greater than the propagation figured for normal operation, the application-specific delay of on-chip signals. Thus, making all connections logic is coupled directly to the microprocessor core with- between the microprocessor core and the application- out passing through off-chip I/O drivers/receivers. In ad- specific logic through off-chip drivers and receivers im- 15 dition, in normal mode, various signals from the appli- poses a significant performance limitation due to in- cation-specific logic are coupled to the I/O drivers/re- creased propagation delays. ceivers. When the control inputs are configured for AVP Another relevant architecture for an integrated cir- operation, the microprocessor core I/O signals are cou- cuit that includes an embedded microprocessor is dis- pled directly to the I/O drivers/receivers to allow an ex- closed in U.S. Pat. No. 5,331,571 "Testing and Emula- 20 ternal tester to apply standard AVPs developed for a tion of Integrated Circuits" (issued 7/19/94 to Aronoff et stand-alone microprocessor to the embedded micro- al. and assigned to NEC Electronics, Inc.). The three processor core. When the control inputs are configured patents listed above are incorporated herein by refer- for ICE operation, the application-specific logic signals ence. The Aronoff et al. circuit allows for testing an em- which are coupled to the microprocessor core during bedded microprocessor, but requires internal three- 25 normal operation are coupled instead to the I/O drivers/ state busses (i.e., three-state busses which connect log- receivers, allowing an external ICE to emulate the func- ic entirely inside the chip). Internal three-state busses tions of the embedded microprocessor core during de- do not allow for complete testability of the integrated cir- bugging of the application-specific logic and the micro- cuit. For example, if a three-state driver is turned off processor core software. The control inputs may also when it should be turned on, its output may still float to 30 define other modes of operation, such as allowing scan a logic state that is indicative of a functioning circuit, testing of the integrated circuit during manufacturing. In thereby masking defects in the integrated circuit. addition, the test mode matrix contains no three-state Therefore, there existed a need to provide an inte- devices, allowing for complete testability of the integrat- grated circuit, such as an ASIC, with an embedded mi- ed circuit. croprocessor core that allows for the microprocessor 35 core to be tested using standard AVPs developed for BRIEF DESCRIPTION OF DRAWINGS the stand-alone microprocessor, that allows for an ICE to be used to emulate the embedded microprocessor The preferred exemplary embodiment of the core, that couples the microprocessor core directly to present invention will hereinafter be described in con- the application-specific logic without passing through 40 junction with the appended drawings, where like desig- off-chip drivers and receivers, and that contains no nations denote like elements, and: three-state devices to assure complete testability. FIG. 1 is a block diagram of a prior art circuit for DISCLOSURE OF INVENTION selectively coupling signals from a microprocessor 45 core and signals from application-specific logic to According to the present invention an integrated cir- chip output pads 214 of an ASIC; cuit comprises: at least one microprocessor; a logic circuit; and signal routing means coupled between the mi- FIG. 2 is a prior art circuit for selectively coupling croprocessor and the logic circuit, for routing microproc- signals from a microprocessor core and signals essor operational signals directly to the logic circuit, for so from application-specific logic to I/O pads 56 of an routing microprocessor test signals to the microproces- ASIC, and for coupling signals from the microproc- sor, and for routing logic test signals to the logic circuit. essor core through I/O drivers 54 and receivers 58 According to the present invention a method for to the application-specific logic; testing an integrated circuit comprises the steps of: providing a microprocessor on the integrated circuit; pro- 55 FIG. 3 is a block diagram of an ASIC implementing viding a logic circuit on the integrated circuit; providing the test mode matrix in accordance with a first em- signal routing means coupled between the microproc- bodiment of the present invention; essor and the logic circuit, for routing microprocessor

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FIG. 4 is a block diagram of an ASIC implementing as "AVP mode", which allows microprocessor core 310 two test mode matrices in accordance with a sec- to be tested by applying standard test vectors to I/O cir- ond embodiment of the present invention; cuits 330. In a third mode of operation, AVP is de-asserted while ICE is asserted, causing ASIC 300 to enter FIG. 5 is a block diagram of a non-dedicated cell 5 another special test mode referred to herein as "ICE used within the test mode matrices of FIGs. 3 and 4; mode", which allows application-specific logic 320 and code for microprocessor core 310 to be debugged by FIG. 6 is a block diagram of a dedicated cell used connecting an in-circuit emulator (ICE) to I/O circuits within the test mode matrices of FIGs. 3 and 4; and 330. In a fourth mode of operation, AVP and ICE are 10 both asserted, causing ASIC 300 to enter another mode FIG. 7 is a block diagram of a portion of the core corresponding to a mode selected by the user. One ex- selection matrix of FIG. 4. ample of an appropriate fourth mode allows scan testing of ASIC 300 during manufacturing. BEST MODE FOR CARRYING OUT THE INVENTION The state of control signals 382 is reflected on in- 15 puts 390 of test mode matrix 340, causing test mode Referring to FIG. 3, an integrated circuit, such as matrix 340 to make the appropriate connections for the ASIC 300, in accordance with a first embodiment of the selected mode. Test mode matrix 340 is bidirectional, present invention comprises a microprocessor core and can therefore switch inputs, outputs, and bidirec- 310, application-specific logic 320, I/O circuits 330, and tional signals. In normal mode (e.g., when AVP and ICE a test mode matrix 340. Test mode matrix 340 intercon- 20 are both de-asserted), test mode matrix 340 couples mi- nects microprocessor core 31 0, application-specific log- croprocessor I/O signals on bus 350 to a first set of ap- ic 320, and I/O circuits 330 in a manner that allows test- plication-specific logic I/O signals on bus 360, and cou- ing microprocessor core 310 using standard test vectors ples a second set of application-specific logic I/O signals by coupling an external tester to I/O circuits 330; that on bus 370 to bus 380, which are in turn coupled to I/O allows system testing and debugging of the application- 25 circuits 330. Note that the signals available off-chip (i. specific logic 320 and code for the microprocessor core e., on bus 380 coupled to I/O circuits 330) are signals 310 by connecting an in-circuit emulator (ICE) to I/O cir- 370 from application-specific logic 320. The microproc- cuits 330; and that further allows for normal circuit op- essor I/O signals 350 will not necessarily be available eration. Test mode matrix 340 makes the required con- off-chip, unless application-specific logic 320 internally nections without routing any of the signals between mi- 30 routes some of the microprocessor I/O from bus 360 to croprocessor core 310 and application-specific logic bus 370. Thus, in normal mode, microprocessor core 320 through off-chip driver/receivers located within I/O 31 0 may not be readily accessible for testing. However, circuits 330, and without routing any of these signals microprocessor core 310 may always be tested using through three-state devices, allowing for a high level of AVP mode. performance while maintaining complete testability of 35 In AVP mode (e.g., when AVP is asserted and ICE the ASIC. is de-asserted), test mode matrix 340 couples the mi- Microprocessor core 310 executes code and con- croprocessor I/O signals on bus 350 to bus 380, causing trols application-specific logic 320 to cause ASIC 300 to all the microprocessor I/O signals to be accessible off- perform its desired function. Microprocessor core 310 is chip. AVP mode thus allows an external tester coupled any suitable microprocessor core which may be imple- 40 to I/O circuits 330 to apply standard test vectors devel- mented within the ASIC. Application-specific logic 320 oped for a stand-alone microprocessor to test micro- is an array of logic designed and configured to interact processor core 310 within ASIC 300. with microprocessor core 310. I/O circuits 330 provide In ICE mode (e.g., when AVP is de-asserted and all the off-chip drivers and receivers to interface ASIC ICE is asserted), test mode matrix 340 couples the I/O 300 to external devices. The operation of ASIC 300 de- 45 signals on bus 360 to bus 380. In normal mode, bus 360 pends on the state of control signals 382, shown for il- provides microprocessor I/O to application-specific logic lustrative purposes in FIG. 3 as AVP and ICE. These 320. In ICE mode, an external in-circuit emulator (ICE) control signals 382 pass through I/O circuits 330 and may be coupled to I/O circuits 330 to emulate microproc- signals 390 to test mode matrix 340, which varies its essor core 31 0. Coupling bus 380 to bus 360 necessar- function according to the specific mode selected via 50 ily implies that signals on bus 370 which are normally control signals 382. connected off-chip via bus 380 in normal mode are not For the specific implementation shown in FIG. 3, the available off-chip in ICE mode, since all off-chip I/O on two binary control signals 382 (AVP, ICE) provide for bus 380 is coupled to application-specific logic 320 via four different modes of operation. In a first mode of op- bus 360. The impact of signals on bus 370 being una- eration, AVP and ICE are both de-asserted, causing nor- 55 vailable in ICE mode may be minimized by judicious se- mal operation of ASIC 300. In a second mode of oper- lection of which signals within application-specific logic ation, AVP is asserted while ICE is de-asserted, causing 320 are coupled to bus 370. ASIC 300 to enter a special test mode referred to herein Referring nowto FIG. 4, an ASIC 400 in accordance

4 7 EP0 758 113 A1 8 with a second embodiment of the present invention suit- CORE_SELECT is in a first state corresponding to core ably includes a microprocessor core 310, application- 31 0), test mode matrix 340 couples the microprocessor specific logic 320, and a test mode matrix 340 (similar I/O signals on bus 350 to bus 380. Core selection matrix to the implementation of the first embodiment), and in 454 then couples bus 380 to bus 452 in response to in- addition includes a second microprocessor core 410, a 5 put 492 being in the first state (corresponding to core second test mode matrix 440, a core selection matrix 310), causing all the microprocessor I/O signals for mi- 454, and I/O circuits 430. ASIC 400 in accordance with croprocessor core 310 (Le., on bus 350) to be accessi- the second embodiment of the invention is used when ble off-chip. In this manner, an external tester coupled multiple microprocessors are embedded in a single to I/O circuits 430 may apply standard test vectors de- ASIC device. For illustrative purposes, the number of 10 veloped for a stand-alone microprocessor to test micro- microprocessor cores in FIG. 4 is shown as two, but the processor core 310 within ASIC 300. Microprocessor present invention extends to any appropriate number of core 410 may be tested in similar fashion in AVP mode microprocessor cores embedded within an integrated by asserting AVP, de-asserting ICE, and placing core circuit, such as an ASIC. select in a second state corresponding to core 410. In Core selection matrix 454 switches the signals on is this mode, test mode matrix 440 couples microproces- bus 380 to bus 452 when input 492 is in a first state, and sor I/O signals on bus 450 to bus 480. Core selection switches the signals on bus 480 to bus 452 when input matrix 454 then couples bus 480 to bus 452 in response 492 is in a second state. The two states of input 492 to input 492 being in the second state corresponding to correspond to the two states of the CORE_SELECT in- core 410, making all the microprocessor I/O signals for put, and core selection matrix 452 thus selects which 20 microprocessor core 41 0 (Le., on bus 450) available off- bus (380 or 480) is coupled to I/O circuits 430. chip, thereby allowing for testing microprocessor core Control signals 482 to I/O circuits 430 determine the 410 with standard test vectors. Thus, in AVP mode, mi- mode of operation for ASIC 400, and suitably comprise croprocessor cores 310 and 410 may be tested by se- an AVP signal and an ICE signal (as for the first embod- lecting the appropriate core with the CORE_SELECT iment shown in FIG. 3), and one or more 25 control signal, and by applying appropriate test vectors CORE_SELECT signals. The state of control signals (e.g., AVPs) to I/O circuits 430. 482 is reflected on inputs 390 of test mode matrix 340, In ICE mode, an external in-circuit emulator (ICE) on inputs 490 of test mode matrix 440, and on inputs may be coupled to I/O circuits 430 to emulate one of the 492 of core selection matrix 454, which collectively embedded microprocessor cores 310 and 410. In ICE cause the appropriate test mode matrix (340 or 440) and 30 mode with microprocessor core 310 selected (e.g., core selection matrix 454 to make the appropriate con- when AVP is de-asserted, ICE is asserted, and nections for the selected mode. Control signals 482 to CORE_SELECT is in the first state, corresponding to ASIC 400 define similar modes as ASIC 300 (FIG. 3), microprocessor core 310), test mode matrix 340 cou- namely, normal mode, AVP mode, ICE mode, and other ples the I/O signals on bus 360 to bus 380. Core selec- modes (as required). However, control signals 482 must ts tion matrix then couples bus 380 to bus 452 in response also provide AVP mode and ICE mode (and possibly one to input 492 being in the first state (corresponding to mi- or more other modes) for both microprocessor cores croprocessor core 310). In normal mode, bus 360 pro- 310 and 410. The AVP and ICE control signals function vides microprocessor I/O from microprocessor core 31 0 the same as for ASIC 300, while CORE_SELECT de- on bus 350 to application-specific logic 320. Coupling fines which microprocessor core (310 or 410) is select- 40 bus 380 to bus 360 necessarily implies that signals on ed. bus 370 which are normally connected off-chip via bus In normal mode (e.g., when AVP and ICE are both 380 in normal mode are not available off-chip in ICE de-asserted), test mode matrix 340 couples microproc- mode. As described above, the impact of signals on bus essor I/O signals on bus 350 to a first set of application- 370 being unavailable in ICE mode may be minimized specific logic I/O signals on bus 360, and couples a sec- 45 by judicious selection of which signals within applica- ond set of application-specific logic I/O signals on bus tion-specific logic 320 are coupled to bus 370. An ICE 370 to bus 380. Core selection matrix 454, in response may also be used to emulate the function of microproc- to control signal 492 being driven to an appropriate state essor core 410 by de-asserting AVP, asserting ICE, and in normal mode by I/O circuits 430, couples the signals placing CORE_SELECT in the second state (corre- on bus 380 to bus 452, which is coupled to I/O circuits 50 sponding to microprocessor core 410). In this mode, test 430. Note that the signals available off-chip (Le., cou- mode matrix 440 couples bus 470 to bus 480. Core se- pled to I/O circuits 430) are signals 370 from application- lection matrix 454 then couples bus 480 to bus 452 in specific logic 320. In addition, in normal mode, test response to input 492 being in the second state (corre- mode matrix 440 routes microprocessor I/O signals from sponding to microprocessor core 410), allowing an ex- bus 450 to bus 470. Bus 480 is inactive in normal mode, 55 ternal ICE coupled to I/O circuits 430 to emulate the and is only used in test modes. functions of microprocessor core 41 0 on bus 470. Thus, In AVP mode with microprocessor core 310 select- in ICE mode, an external ICE may replace one of the ed (e.g., when AVP is asserted, ICE is de-asserted, and embedded microprocessor cores 310 and 410 by se-

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lecting the appropriate core via the CORE_SELECT select lines S are 10, and routing input 11 to the output control signal. when select lines S are 11. The test mode matrix (e.g., 340 and 440) in accord- The function of cell 500 may best be understood by ance with the present invention may be implemented us- analyzing the signals and effects during each mode of ing a variety of different internal circuit configurations. 5 operation (i.e., normal mode, AVP mode, ICE mode, and Referring to FIG. 5, one suitable circuit is a non-dedi- other modes). In normal mode, AVP and ICE are both cated cell 500 which provides the microprocessor I/O de-asserted, i.e., AVP and ICE are both low for cell 500 signals to the I/O circuits (e.g., pad 570) only during a of FIG. 5. With both AVP and ICE low, MUX 510 is en- test mode (e.g., AVP, ICE, or other test modes). Non- abled by the AVP low signal, and input 0 is selected by dedicated cells 500 are suitably used for each I/O signal 10 the ICE low signal. As a result, MUX 510 routes that is accessed externally (e.g., at pad 570) only during DO_OUTfrom microprocessor core 310 to DOJN of ap- a test mode. Referring to FIG. 6, another suitable circuit plication-specific logic 320. MUX 520 is also enabled is a dedicated cell 600 which provides the microproces- (ICE low), and input 0 is selected (AVP low) , causing sor I/O signals to the I/O circuits (e.g., pad 570) in nor- MUX 520 to route DO_OUT from application-specific mal mode as well as in the test modes. Dedicated cell is logic 320 to DOJN of microprocessor core 310. In ad- 600 is used for each I/O signal that must be externally dition, with both AVP and ICE low, MUX 530 routes accessible (e.g., at pad 570) in the normal mode of op- OTHER_OUT from application-specific logic 320 to eration as well as in the test modes. Cell 600 is "dedi- CIO_OUT, which is coupled to data output 572 of pad cated" in that the connection to and from microprocessor 570. MUX 540 routes OTHER JEN from application-spe- I/O to pad 570 is maintained in normal mode rather than 20 cific logic 320 to CIOJEN, which is coupled to output just in test modes, as is the case for the non-dedicated enable 574 of pad 570. In addition, with AVP and ICE cell of FIG. 5, making the output pad "dedicated" to the both low, the output AUXJN of gate 560 is low, while microprocessor I/O signal. gate 550 passes through data input 576 from pad 570 Referring to FIG. 5, non-dedicated cell 500 is a por- to the OTHERJN input to application-specific logic 320. tion of test mode matrix 340 (FIGs. 3 and 4) interposed 25 Thus, normal mode results in the following connections: between microprocessor core 310 and application-specific logic 320, and is coupled to a pad 570 that has a 1) D0_OUT of core 310 to DOJN of logic 320 data output 572, an output enable 574, and a data input 2) D0_OUT of logic 320 to DOJN of core 310 576. Pad 570 corresponds to one specific I/O circuit 3) OTHER_OUT of logic 320 to data output 572 of within I/O circuits 330 or 430. Cell 500 implements the 30 pad 570 connections required for a single bidirectional signal to/ 4) OTHERJEN of logic 320 to output enable 574 of from microprocessor core 310 from/to application-spe- pad 570 cific logic 320 when the signal is needed at pad 570 only 5) data input 576 of pad 570 to OTHERJN of logic during test modes (le., AVP, ICE, and possibly other 320 modes). For illustrative purposes, the bidirectional sig- 35 nal shown in FIG. 5 is the DO (data bit 0) signal of mi- Normal mode thus results in the direct coupling of data croprocessor core 31 0 of FIGs. 3 and 4, which compris- lines between core 310 and logic 320, without passing es a D0_OUT signal (DO output), a DOJN signal (DO through any off -chip driver/receivers, and without pass- input), and a D0_EN signal (DO enable). D0_EN of core ing through any three-state devices. In addition, normal 310 is asserted (i.e., driven high) by core 310 to indicate 40 mode couples pad 570 to/from other I/O in logic 320. that core 31 0 is driving valid data on its D0_OUT output. In AVP mode, AVP is asserted (Le., high) and ICE Similarly, D0_EN of logic 320 is driven high by logic 320 is de-asserted (Le., low). With AVP high and ICE low, when it has valid data on its D0_OUT output. MUX 51 0 is disabled by the AVP high signal, placing the Non-dedicated cell 500 suitably includes multiplex- DOJN input to application-specific logic 320 in a de- ers (MUXs) 510, 520, 530 and 540, and gates 550 and 45 asserted state (e.g., low). MUX 520 is enabled (with ICE 560. MUXs 510 and 520 are suitable 2-to-1 MUXs with low), and input 1 is selected (with AVP high), causing an output that is de-asserted (e.g., driven low) when an MUX 520 to route the data input 576 from pad 570 to enable (G) input is de-asserted (e.g., high). MUXs 510 DOJN of microprocessor core 310. In addition, with and 520 route the signal on the 0 input to the output AVP high and ICE low, MUX 530 routes DO_OUT from when the select S is low and the enable G is asserted so microprocessor core 31 0 CIO_OUT, which is coupled to (e.g., low). MUXs 510 and 520 route the signal on the 1 data output 572 of pad 570. MUX 540 routes DO JEN input to the output when the select S is high and the from microprocessor core 310 to CIOJEN, which is cou- enable G is asserted. MUXs 510 and 520 have their out- pled to output enable 574 of pad 570. In addition, with puts in a de-asserted state (e.g., driven low) when ena- AVP high and ICE low, the outputs of gates 550 and 560 ble G is high. In addition, MUXs 530 and 540 are suitable 55 are both driven low. Thus, AVP mode results in the fol- 4-to-1 MUXs, routing input 00 to the output when select lowing connections: lines S are 00, routing input 01 to the output when select lines S are 01 , routing input 1 0 to the output when the 1) data input 576 of pad 570 to DOJN of core 310

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2) D0_OUT of core 31 0 to data output 572 of pad tion of test mode matrix 340 interposed between micro- 570 processor core 310 and application-specific logic 320, 3) D0_EN of core 310 to output enable 574 of pad and is also coupled to pad 570. Cell 600 implements the 570 connections required for a single bidirectional signal to/ 5 from microprocessor core 310 from/to application-spe- AVP mode therefore results in directly coupling the mi- cific logic 320 when the microprocessor I/O signal is croprocessor I/O signals to pad 570, allowing an exter- needed at pad 570 during both normal mode and test nal tester to apply test vectors to core 310. modes. For illustrative purposes, the bidirectional signal In ICE mode, AVP is de-asserted (i.e., low) and ICE shown in FIG. 6 is the same DO (data bit 0) signal of is asserted (i.e., high). With AVP low and ICE high, MUX 10 microprocessor core 310 shown in FIG. 5. Dedicated 510 is enabled (with AVP low) and input 1 is selected cell 600 suitably includes multiplexers (MUXs) 610, 620, (with ICE high), causing MUX 510 to route data input 630 and 640, and gates 660, 680, 682, 684 and 686. 576 of pad 570 to the DOJN input to application-specific The function of dedicated cell 600 is identical to the func- logic 320. MUX 520 is disabled by the ICE high signal, tion of non-dedicated cell 500 in AVP, ICE and other placing the DOJN input to microprocessor core 310 in is modes, but is different in normal mode. The difference a de-asserted state (e.g., low). In addition, with AVP low between non-dedicated cell 500 and dedicated cell 600 and ICE high, MUX 530 routes DO_OUT from applica- may best be understood by analyzing the signals and tion-specific logic 320 to CIO_OUT, which is coupled to effects of cell 600 during normal mode. data output 572 of pad 570. MUX 540 routes DO JEN In normal mode, AVP and ICE are both de-asserted, from application-specific logic 320 to CIOJEN, which is 20 i.e., low. With both AVP and ICE low, MUX 610 is ena- coupled to output enable 574 of pad 570. In addition, bled by the AVP low signal. The select input to MUX 61 0 with AVP low and ICE high, the outputs of gates 550 and is coupled to the output of gate 680. Thus, with ICE low, 560 are both driven low. Thus, ICE mode results in the when the DOJEN output of microprocessor core 310 is following connections: high, the output of gate 680 is low, causing MUX 610 to 25 route the DO_OUT signal from microprocessor core 310 1 ) data input 576 of pad 570 to DOJN of logic 320 to the input DOJN input of application-specific logic 2) D0_OUT of logic 320 to data output 572 of pad 320. When the DOJEN output of core 310 goes low, 570 however, the output of gate 680 is high, causing MUX 3) DO JEN of logic 320 to output enable 574 of pad 610 to route the CIOJN signal from pad 570 to the 570 30 DOJN input of application-specific logic 320. With ICE low in normal mode, MUX 620 is also en- ICE mode therefore results in directly coupling I/O sig- abled. The output of gate 682 drives the select line of nals from logic 320 to pad 570, allowing an external ICE MUX 620. With AVP low, when the DOJEN output of to emulate core 310. application-specific logic 320 is high, the output of gate In afourth mode, with both AVP and ICE high, MUXs 35 682 is low, causing MUX 620 to route the DO_OUT sig- 510 and 520 are both disabled, causing the DOJN input nal from application-specific logic 320 to the DOJN in- of application-specific logic 320 and the DOJN input to put of microprocessor core 310. When the DOJEN out- microprocessor core 31 0 to be in a de-asserted state (e. put goes low, however, the output of gate 682 goes high, low). MUX 530 routes signal AUX_OUT to CIO_OUT, causing MUX 620 to route the CIOJN signal from data which is coupled to data output 572 of pad 570. MUX 40 input 576 of pad 570 to the DOJN input of microproc- 540 routes signal AUXJEN to CIOJEN, which is coupled essor core 310. to output enable 574 of pad 570. In addition, with AVP With AVP and ICE both low in normal mode, MUXs and ICE both high, the output of gate 550 is driven low, 630 and 640 both route their 00 inputs to their respective and the output of gate 560 (AUXJN) is the same logic outputs. The 00 input of MUX 630 is the output of OR state as CIOJN from data input 576 of pad 570. This 45 gate 684. The inputs to OR gate 684 are DO_OUT from fourth mode thus allows other signals (e.g., AUX) within microprocessor core 310 and DO_OUT from applica- the ASIC to be available at pad 570. One example of tion-specific logic 320. It is assumed that DO_OUT of such afourth mode would allow scan testing of the ASIC either core 310 or logic 320 is held low when the corre- during manufacturing by coupling a scan data input sig- sponding DOJEN is inactive. Thus, when DO_OUTfrom nal to AUXJN and by coupling AUXJEN to a pull-down, so either of core 310 or logic 320 goes high, the output of or by coupling a scan data output signal to AUX_OUT MUX 630 (CIO_OUT) goes high, driving data output 572 and by coupling AUXJEN to a pull-up. of pad 570 high. In similar fashion, when either of the Note that subsets of cell 500 may be used for uni- DOJEN signals from core 310 or logic 320 is high, the directional input or output signals. Cell 500 may be re- output of MUX 640 (CIOJEN) also goes high, driving peated as required, and various cells 500 may share in- 55 output enable 574 of pad 570 high. In addition, with AVP ternal physical structures to minimize the chip area re- and ICE both low, the output of gate 660 is driven low, quired for test mode matrix 340. resulting in a low signal on AUXJN. Thus, normal mode Referring nowto FIG. 6, dedicated cell 600 is a por- results in the following connections:

7 13 EP0 758 113 A1 14

1 ) data input 576 of pad 570 to DOJN of logic 320 for cell 700 to switch between any number of embedded when DOJEN of core 310 is low microprocessor cores by simply increasing the number of select lines that comprise the CORE_SELECT signal 2) D0_OUT of core 31 0 to DOJ N of logic 320 when (and corresponding inputs 492), and increasing the DOJEN of core 310 is high 5 number of inputs to MUXs 710 and 720, and decoder 730, to accommodate the signals from each microproc- 3) data input 576 of pad 570 to DOJN of core 31 0 essor core that are routed through each corresponding when DOJEN of logic 320 is low test mode matrix. By eliminating all three-state devices in the integrat- 4) D0_OUT of logic 320 to DOJN of core 310 when 10 ed circuit (i.e., 300 and 400) in accordance with the DOJEN of logic 320 is high present invention, several benefits accrue when compared to integrated circuits that have three-state devic- 5) high on data output 572 of pad 570 when either es. For example, a three-state bus in high-impedance D0_OUT of core 31 0 or D0_OUT of logic 320 is high state can float across the switching threshold of circuits is driven by the bus, causing these circuits to toggle rap- 6) high on output enable 574 of pad 570 when either idly, thereby consuming more power. Having no three- DOJEN of core 310 or DOJEN of logic 320 is high state busses thus reduces the power consumption of the integrated circuit. In addition, tools for generating test As stated above, the connections for AVP mode, patterns do not typically support three-state devices, ICE mode, and other modes are identical to the connec- 20 since only one driver on the three-state bus can be en- tions for non-dedicated cell 500 in FIG. 5. abled at any given time. To prevent bus contention on a Referring again to FIG. 4, test mode matrix 340 suit- three-state bus during testing, test patterns must be ably comprises a combination of non-dedicated cells generated by hand, significantly increasing the expense 500 and dedicated cells 600, while test mode matrix 440 of testing an integrated circuit with three-state devices suitably comprises only dedicated cells 600. Note that 25 when compared to a comparable integrated circuit with- cells 500 and 600 described herein and illustrated in the out three-state devices. The most important benefit, figures assume a bidirectional signal consisting of an in- however, of eliminating all three-state devices within the put, an output, and an enable signal. Cells 500 and 600 integrated circuit of the present invention is that the re- may also be used, however, for unidirectional input or sulting integrated circuit is 100% testable. All functions output signals, either by driving unused inputs in the ba- 30 of the integrated circuit may be fully functionally tested, sic cells 500 and 600 to a low logic level, or by optimizing without fear that one or more three-state devices are a portion of cell 500 or 600 by removing unneeded cir- masking defects during testing. cuitry. An ASIC in accordance with the present invention Referring to FIG. 7, the internal circuitry of core se- containing one or more test mode matrices as disclosed lection matrix 454 (FIG. 4) includes a plurality of cells 35 herein provides for complete testability by virtue of al- 700. Each cell 700 includes a data input CIO IN, a data lowing each embedded microprocessor core to be fully output CIO_OUT, and an enable input CIOJEN from a functionally tested using standard test vectors, by allow- first test mode matrix (e.g., 340), the same three signals ing an ICE to emulate the function of any one of the em- from a second test mode matrix (e.g., 440), and corre- bedded microprocessor cores for debugging purposes, sponding outputs to pad 570. Cell 700 includes MUXs 40 and by providing other test modes as needed, such as 710 and 720, and decoder 730. MUXs 710 and 720 cou- scan testing of the ASIC during manufacturing. The per- ple input 0 to their outputs when CORE_SELECT is low, formance of the ASIC is also enhanced by directly rout- and couples input 1 to their outputs when ing all signals between the microprocessor core and the CORE_SELECT is high. Decoder 730 couples its input application-specific logic directly through the test mode signal to its output 0 when CORE_SELECT is low, and 45 matrix or matrices, without passing through off-chip driv- couples its input to its output 1 when CORE_SELECT ers and receivers, and without passing through any is high. MUX 71 0 is a data output multiplexer, MUX 720 three-state devices. is an output enable multiplexer, and MUX 730 is a data input decoder. MUXs 710 and 720, and decoder 730, selectively couple the signals from test mode matrix 340 50 Claims to pad 570 when CORE_SELECT is in the first state (e. q. , low, corresponding to microprocessor core 31 0), and 1. An integrated circuit comprising: selectively couple the signal from test mode matrix 440 to pad 570 when core select is in a second state (e.g., at least one microprocessor; high, corresponding to microprocessor core 410). 55 a logic circuit; and While cell 700 is shown for illustrative purposes with signal routing means coupled between the mi- circuitry to switch between two test mode matrices 340 croprocessor and the logic circuit, for routing and 440, it is within the scope of the present invention microprocessor operational signals directly to

8 15 EP0 758 113 A1 16

the logic circuit, for routing microprocessor test pling an in-circuit emulator to the plurality of I/O signals to the microprocessor, and for routing pads. logic test signals to the logic circuit. 8. The integrated circuit of either claim 6 or 7 wherein 2. The integrated circuit of claim 1 wherein the signal 5 the signal routing means routes the microprocessor routing means routes the microprocessor opera- operational signals to the logic circuit without pass- tional signals to the logic circuit without passing ing through any of the plurality of I/O circuits. through any I/O drivers that are coupled to I/O pads on the integrated circuit and without passing 9. The integrated circuit of any of claims 6 to 8 wherein through any I/O receivers that are coupled to the I/ 10 the signal routing means comprises at least one test O pads. mode matrix, each test mode matrix comprising a plurality of cells, each cell coupled to at least one of 3. The integrated circuit of claim 1 or 2 wherein the the plurality of I/O circuits, each cell further compris- signal routing means contains no three-state devic- ing: es. 15 means for coupling at least one signal between 4. The integrated circuit of any previous claim wherein the microprocessor and the logic circuit in the the signal routing means operates in one of a plu- first state; rality of mutually-exclusive states, and wherein the signal routing means routes the microprocessor op- 20 means for coupling at least one signal between erational signals to the logic circuit in a first of the at least one of the plurality of I/O circuits and plurality of states, routes the microprocessor test the microprocessor in the second state; and signals to the microprocessor in a second of the plurality of states, and routes the logic test signals to means for coupling at least one signal between the logic circuit in a third of the plurality of states. 25 at least one of the plurality of I/O circuits and the logic circuit in the third state. 5. The integrated circuit of claim further comprising means for selecting one of the plurality of states. 10. The integrated circuit of any of claims 6 to 9 wherein the signal routing means routes auxiliary test sig- 6. The integrated circuit of claim further comprising a 30 nals from the integrated circuit to the plurality of I/O plurality of I/O circuits coupled to a plurality of I/O circuits when the signal routing means is in a fourth pads, wherein the signal routing means operates in state. one of a plurality of mutually-exclusive states, and wherein: 11. The integrated circuit of any of claims 6 to 10 where- 35 in the signal routing means comprises a test mode the signal routing means routes the microproc- matrix having a first bus coupled to the microprocessor operational signals directly to the logic essor, having a second bus coupled to the logic cir- circuit when the signal routing means is in a first cuit, and having a third bus coupled to the plurality of the plurality of states; of I/O circuits, and wherein: the signal routing means routes the microproc- 40 essor test signals from the plurality of I/O cir- the test mode matrix couples the first bus to the cuits to the microprocessor when the signal second bus in the first state; routing means is in a second of the plurality of the test mode matrix couples the first bus to the states; and third bus in the second state; and the signal routing means routes the logic test 45 the test mode matrix couples the second bus to signals from the plurality of I/O circuits to the the third bus in the third state. logic circuit when the signal routing means is in a third of the plurality of states. 12. The integrated circuit of claim wherein the test mode matrix further comprises a fourth bus coupled 7. The integrated circuit of claim wherein the first state so to the logic circuit, and wherein the test mode matrix of the signal routing means corresponds to a state couples the third bus to the fourth bus in the first for normally operating the integrated circuit, where- state. in the second state of the signal routing means corresponds to a state for testing the microprocessor 13. The integrated circuit of any previous claim com- by applying standard test vectors for the microproc- 55 prising a plurality of microprocessors, and further essor to the plurality of I/O pads, and wherein the comprising switching means for selecting one of the third state of the signal routing means corresponds plurality of microprocessors. to a state for testing the integrated circuit by cou-

9 17 EP0 758 113 A1 18

14. The integrated circuit of any one of claims 1 to 12 on the integrated circuit; comprising a plurality of microprocessors, and providing signal routing means coupled be- wherein the signal routing means comprises: tween the microprocessor and the logic circuit, for routing microprocessor operational signals a plurality of test mode matrices, at least one 5 directly to the logic circuit without passing test mode matrix for each of the microproces- through any of the plurality of I/O circuits in a sors; and first state, for routing microprocessor test sig- switching means for coupling the test mode ma- nals to the microprocessor in a second state, trices corresponding to a selected one of the and for routing logic test signals to the logic cir- plurality of microprocessors to the plurality of I/ 10 cuit in a third state; O circuits. coupling an external tester to the plurality of I/ O pads; 15. The integrated circuit of claim wherein each test selecting the second state, resulting in the sig- mode matrix has a first bus coupled to the corre- nal routing means routing the microprocessor sponding microprocessor, a second bus coupled to is test signals from the plurality of I/O circuits to the logic circuit, and a third bus coupled to the the microprocessor under test; switching means, and wherein: applying a plurality of test vectors to the plurality of I/O pads with the external tester; the test mode matrix couples the first bus to the monitoring signals from of the microprocessor second bus in the first state; 20 under test on the I/O pads that result from ap- the test mode matrix couples the first bus to the plying the plurality of test vectors; and third bus in the second state; and indicating from the monitored signals whether the test mode matrix couples the second bus to the microprocessor under test is functional. the third bus in the third state. 25 19. The method of claim 18 further comprising the steps 16. A method for testing an integrated circuit compris- of: ing the steps of: coupling an in-circuit emulator to the plurality of providing a microprocessor on the integrated I/O pads; circuit; 30 selecting the third state, resulting in the signal providing a logic circuit on the integrated circuit; routing means routing the logic test signals providing signal routing means coupled be- from the plurality of I/O circuits to the logic cir- tween the microprocessor and the logic circuit, cuit; and for routing microprocessor operational signals applying signals to the plurality of I/O pads from directly to the logic circuit, for routing micro- 35 the in-circuit emulator to emulate the function processor test signals to the microprocessor, of the microprocessor. and for routing logic test signals to the logic circuit; 20. The method of claim 19 further including the steps routing the microprocessor test signals from an of: external tester; and 40 applying test vectors to the microprocessor providing a plurality of microprocessors on the through the signal routing means. integrated circuit; providing a plurality of test mode matrices on 17. The method of claim further comprising the steps the integrated circuit, at least one test mode of: routing the logic test signals from an external in- 45 matrix for each of the plurality of microproces- circuit emulator; and sors; emulating the function of the microprocessor providing switching means for coupling the test for debugging the logic circuit and for debugging mode matrices corresponding to a selected one code for the microprocessor. of the plurality of microprocessors to the plural- so ity of I/O circuits; 18. A method for testing an integrated circuit compris- coupling the corresponding test mode matrix to ing the steps of: the plurality of I/O circuits through the switching means; providing at least one microprocessor on the in- routing the logic test signals from the plurality tegrated circuit; 55 of I/O circuits through the switching means; and providing a logic circuit on the integrated circuit; routing the logic test signals from the switching providing a plurality of I/O circuits on the inte- means through the corresponding test mode grated circuit coupled to a plurality of I/O pads matrix to the logic circuit.

10 EP0 758 113 A1

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Patent European EUROPEAN SEARCH REPORT ^ Office EP 96 30 5207

DOCUMENTS CONSIDERED TO BE RELEVANT Patronrv Citation of document with indication, where appropriate, Relevant CLASSIFICATION OF THE l-aregory of re|evan, phages to c|ajm APPLICATION (Int.CI.6) D,X US-A-5 331 571 (ARONOFF ALAN P ET AL) 19 1,2,4-8, G06F11/267 July 1994 13,14, 16-20 Y 12 A 9,11,15 * abstract * * column 4, line 8 - column 5, line 22 * * column 5, line 55 - column 6, line 58 * * column 10, line 61 - column 12, line 4 * * column 13, line 4 - line 52 * * figures 4,6,22,24 *

D,X EP-A-0 567 790 (MOTOROLA INC) 3 November 1,2,4,5, 1993 7,8,16, 17 A 9,11,18, 19 * abstract * * page 2, line 43 - page 3, line 52 * * fiqure 1 * D & US-A-5 304 860 technical fields SEARCHED (Int.CI.6) D,Y US-A-5 254 940 (OKE TIMOTHY P ET AL) 19 12 G06F October 1993 A 1,2,4-9, 11,16,18 * the whole document *

X EP-A-0 594 478 (SAGEM) 27 April 1994 1,4-7,9, 16,17 A 11,18,19 * column 5, line 43 - column 8, line 5 * * figure *

-/--

The present search report has been drawn up for all claims Place of search Date of completion of the search Exaniaer BERLIN 24 October 1996 Masche, C CATEGORY OF CITED DOCUMENTS T : theory or principle underlying the invention E : earlier patent document, but published on, or X : particularly relevant if taken alone after the filing date Y : particularly relevant if combined with another D : document cited in the application document of the same category L : document cited for other reasons A : technological background O : non-written disclosure & : member of the same patent family, corresponding P : intermediate document document

17 EP0 758 113 A1

Patent European EUROPEAN SEARCH REPORT Application Number Office EP 96 30 5207

DOCUMENTS CONSIDERED TO BE RELEVANT Citation of document with indication, where appropriate, Relevant CLASSIFICATION OF THE Category of relevant passages to claim APPLICATION (Int.CI.6-) EP-A-0 419 105 (TEXAS INSTRUMENTS INC) 27 1-3,5, March 1991 16,18 4,6,8-11 * abstract * * column 6, line 16 - column 7, line 1 * * figure 1 *

TECHNICAL FIELDS SEARCHED (Int.CI.6)

The present search report has been drawn up for all claims Place of search Date of completioa of the search Exatniaer BERLIN 24 October 1996 Masche, C CATEGORY OF CITED DOCUMENTS T : theory or principle underlying the invention E : earlier patent document, but published on, or X : particularly relevant if taken alone after the filing date Y : particularly relevant if combined with another D : document cited in the application document of the same category L : document cited for other reasons A : technological background O : non-written disclosure & : member of the same patent family, corresponding P : intermediate document document