High Performance Silicon Carbide Power Packaging—Past Trends, Present Practices, and Future Directions

energies

Review High Performance Silicon Carbide Power Packaging—Past Trends, Present Practices, and Future Directions

Sayan Seal * and Homer Alan Mantooth

Department of Electrical Engineering, University of Arkansas, Fayetteville, AR 72701, USA; [email protected] * Correspondence: [email protected]; Tel.: +1-479-301-7928

Academic Editor: Alberto Castellazzi Received: 15 December 2016; Accepted: 22 February 2017; Published: 10 March 2017

Abstract: This paper presents a vision for the future of 3D packaging and integration of silicon carbide (SiC) power modules. Several major achievements and novel architectures in SiC modules from the past and present have been highlighted. Having considered these advancements, the major technology barriers preventing SiC power devices from performing to their fullest ability were identiﬁed. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were described, and the concept for a novel SiC power module was discussed.

Keywords: wide bandgap; power electronics; high power density; 3D packaging; wire bondless

1. Introduction Wide band gap (WBG) power devices are dictating the pace of development of power electronics today. There has been considerable advancement in the field of WBG semiconductor power devices. These have the benefits of enabling a high power density at high junction temperatures, coupled with faster switching speeds as compared with their silicon (Si) counterparts [1–6]. Thus far, silicon carbide (SiC) [1–3] and gallium nitride (GaN) [4–6] have been the materials of choice for most WBG modules. While GaN is the preferred choice in applications requiring <500 V, SiC excels in applications exceeding 900 V. SiC devices rated 900 V and above are available in chip sizes spanning just tens of square millimeters. In addition, the switching losses associated with SiC are much lower than the values reported for silicon power devices. SiC devices can be switched at higher frequencies resulting in filtering circuits that occupy less package real estate than their silicon counterparts. Contributing further to the cause of power density is the fact that WBG devices may operate at high junction temperatures, thus introducing the possibility of employing more volumetrically efficient thermal management schemes. This combination can have a great impact on system miniaturization to help realize system architectures that do not even exist at the present time [7]. Although the properties of WBG materials seem almost too good to be true at first glance, the realized performance of these power devices are only as good as the package design. Even as the die sizes of the WBG power devices are continually shrinking and the performance is improving, packaging technology is not keeping pace with these developments. In a modern power electronics module, the size of the passive components and thermal management dictate the overall size. The power stage typically occupies a small fraction of the total volume. This, coupled with weak interconnections using wire bonds, introduces a spate of opportunities for improvement. In fact, eliminating wire bonds and designing shorter interconnects with lower parasitics itself could lead directly to a reduction in the size of passive circuit elements.

Energies 2017, 10, 341; doi:10.3390/en10030341 www.mdpi.com/journal/energies Energies 2017, 10, 341 2 of 30

3D packaging has always been an attractive buzzword in the world of electronics packaging [8–11]. Most of the efforts in this area have been largely focused toward microelectronics, but the benefits translate to higher power modules as well [12]. However, it is necessary to take a step back and critically evaluate the need for a 3D approach and weigh it carefully against any foreseen disadvantages. It has been mentioned before that even in current state-of-the-art multi-chip modules (MCMs), coefficient of thermal expansion (CTE) mismatch of a single interface is a cause of concern—3D electronics packaging takes this problem and literally multiplies it by the number of tiers in the design. This poses the threat that 3D electronics packaging may open a plethora of design challenges. The immediate benefits of using a 3D topology are clearly apparent—a reduction in parasitics, use of efficient distributed cooling schemes, a reduction in footprint and consequent increase in power density. However, caution should be exercised regarding the implementation of such a scheme and the ramifications it may have on the overall system performance. The question being asked here is: are we solving a problem, or trading one problem for a host of others? Research in electronics packaging over the past two decades bears testimony to the desire to move away from wire bonding as an interconnection method [13–16]. There have been several attempts to propose alternative methods, and many of these will be investigated in this paper in due course. Most of the methods reported a decrease in the parasitic inductance in the critical switching loops and projected a relative increase in reliability as compared with modules having wire bonded interconnections. The packaging of SiC power devices are deeply rooted in the wire bonding approach used for silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). Wire bonding has been the standard approach used in MCMs because of ease-of-use and low production costs. As far as performance of an interconnect goes, parasitic inductance, reliability, and cost/manufacturability are the major parameters. Wire bonds offer a significant parasitic inductance; however, it does not manifest itself too adversely at switching frequencies ranging up to tens of kHz. Since most commercially available silicon power modules are well within this specification, switching transients resulting from the parasitic inductance of a wire bond are still within tolerable limits. However, the situation is very different with WBG devices which have shown promise at frequencies exceeding 1 MHz. It is for this reason that many GaN manufacturers have adopted a land grid array (LGA) or ball grid array (BGA) approach in favor of wire bonding. On the down side, the reliability concerns of such approaches have prevented a wide-spread adoption of these techniques across the WBG industry. This paper aims at investigating the trends in SiC power packaging over the past decade and highlights some of the high-performance modules. Section2 summarizes the chief requirements of SiC packaging. From a survey of these advanced wire bonded SiC modules in Section3, the major technology bottlenecks for the further advancement of SiC packaging technology are assessed. Section4 makes a case for wire bondless packaging. Investigations into previous work in silicon 3D wire bondless packaging are presented in Section5. Some of the more recent 3D integration efforts in SiC modules are described in Section6, followed by a summary of future efforts and directions in Section7.

2. Requirements of Silicon Carbide Packaging In the case of any power device technology—Si, SiC, or GaN—the goal should be to ensure that the package does not hinder the performance of the device. A common example of this is package parasitics. Through hole and surface mount packages have been standard choices for discrete power devices for an extended period of time. In fact, many high performance power electronics systems still use discrete devices—they are simple to assemble and easy to replace upon failure. Most of these applications used switching frequencies in the range of 1–5 kHz. As packaging materials are added to the package, the electrical path to the terminals increases significantly. Additional parasitic inductance is perhaps the most significant adversity that arises at the result of this. As power MOSFETs were introduced and became popular, the major manufacturers began making power devices available in bare die form. This offered power module designers more flexibility to minimize parasitics and increase power density. Energies 2017, 10, 341 3 of 30

This became especially important as switching frequencies increased. Switching frequencies up to 25 kHz are becoming increasingly common for SiC power modules. This requires a more thoughtful consideration with respect to module layout and interconnect technologies. Some practices, such as including a Kelvin source terminal for the gate driver return path, have become extremely helpful for SiC module design. Some manufacturers like Wolfspeed have also been including an additional Kelvin source terminal with their discrete devices as well. SiC power devices have the potential to impact power density at all levels in the package—a reduction in the size and number of power devices, a reduction in the size and number of passives for filtering circuits, and a reduction in the volume of thermal management [1]. The advent of high voltage SiC power devices will eliminate the need to parallel a large number of power die. This will reduce system complexity and improve system reliability. However, a careful examination is required to be able to assess the requirements of SiC packaging. Although measures are being taken to reduce the critical switching loop parasitics in SiC power modules, it must be acknowledged that wire bonds are one of the major causes of parasitics. Even a short wire bond has an inherent parasitic inductance that often dominates the total parasitic inductance of the entire loop [2]. These stray inductances do not affect the circuit if the switching frequencies are low enough. Considering that the switching losses of Si power devices increased significantly with switching frequency, rudimentary parasitic minimization strategies provided satisfactory electrical performance. However, despite having relatively lower switching frequencies the overshoot arising from the power loop parasitic inductance ensured that selected power devices had to be over-rated to able to accommodate this. Meade conducted a detailed study on the parasitic problem in 2008 [3]. A simple DC-DC converter topology was chosen to demonstrate the effect of parasitic loop inductances on electrical performance. The turn-off losses dominated, especially as the switching frequency approached 2 MHz. A drastic reduction of the turn-off losses was demonstrated for a wire bond-less packaging method at 3 MHz switching frequency. The losses were much worse for discrete devices. Traditional wire bonded techniques resulted in nearly twice the turn-off losses as compared with the wire bond-less technique. Another interesting fact was that paralleling wire bonds does not alleviate he parasitic problem. The mutual inductance between adjacent wires starts dominating, and there is a limit to which increasing the number of wire bonds can help—a fact presented in a 2016 publication by Yang [17]. Wire bond-less packaging must be pursued as a thrust area for SiC packaging if high voltages and currents are desired to be switched at several MHz. However, faster switching would directly translate to a risk of producing greater electromagnetic interference (EMI), and caution must be exercised to prevent this. EMI suppression is another cardinal aspect of package design that has assumed importance owing to rising dv/dt rates in power electronic circuits. One of the common design philosophies which we will encounter in due course is to integrate the gate driver circuit closer to the power device to form low-area switching loops to reduce parasitics. Although this is the correct approach in principle, high slew rates introduce injected current spikes through the parasitic capacitances in the circuit. Future SiC modules must take this into account. As gate drivers and decoupling capacitors are included in the module itself, care should be taken to decouple spurious current spikes from influencing false turn-on events and leading to premature module failure. From the viewpoint of thermal design, there are two principal thrust areas: (1) thermo-mechanical design strategies for low stress and high reliability; and/or (2) double-sided cooling methodologies. While the first area is advantageous regardless of package type, the latter depends on the critical performance criteria for a given module. There has been a substantial amount of work in identifying and developing materials having a close CTE match with SiC. Many of the approaches are discussed in this paper in due course. Die attach failure and interconnect failure are among the chief ways in which CTE mismatch manifests itself. This may be attributed to the CTE of a wire bond or bond pad being significantly different as compared with SiC. Another common location at which delamination occurs is the interface between Energies 2017, 10, 341 4 of 30 the substrate and heat spreader (or heat sink). Some of the solutions that have been proposed to address these issues are using compliant mechanical materials like sintered silver as the die attach material. The “sponge-like” nature of this material makes it adept at cushioning CTE mismatch stresses. Other methods include the development of alloys and metal-matrix composite materials like MoCu or AlSiC. The CTE of these materials are very well matched to SiC and can be tailored by altering the composition of the compounds. These materials are easy to plate and bond to both the devices and heat sinks (or baseplates). Double sided cooling is another option in order to reduce thermo-mechanical stresses. If the junction temperature is controlled to a low enough value, CTE mismatch stresses will not adversely impact module reliability. However, a double-side cooled module necessitates a wire bond-less packaging approach. Double-sided cooling is also advantageous in modules employing a large number of chips. This may be a very good proposition for vehicle under hood applications, where the ambient temperature is already at elevated levels. A single-sided cooling solution may simply not be enough to handle the thermal load. While we are on the issue of thermal performance, there is an important factor to consider. Contemporary Si devices are rated to operate at a junction temperature of 175 ◦C. Most commercially available SiC devices are also rated for a similar temperature range, although researchers have been able to demonstrate a decent performance at higher temperatures as well. The theoretical limit of SiC as a semiconductor material is well beyond 500 ◦C. Yet the ratings of commercially available devices do not reflect this advantage. One issue could be the reliability of the chip metallization at elevated temperatures—an extremely valid concern. However, there are other factors at play here. These concerns have been echoed in a 2009 publication by Wrzecionko [18]. They demonstrated that although the theoretical limit for the operation of SiC power devices can be as high as 700 ◦C, in reality the optimum temperature was less than 300 ◦C. The authors were of the opinion that if a device is operated below the optimum temperature, it was not possible to take complete advantage of the junction gate field-effect transistor (JFET). A higher than optimum temperature of operation, on the other hand, ran the risk of thermal runaway. The paper also demonstrated that the power density could be improved greatly by either using a chip with a larger area and/or using double-sided cooling. Both the suggested methods were prescribed with the intention of reducing the thermal resistance. This particular study involved SiC JFETTs, but the same concerns are applicable to MOSFETs as well. A cooler junction temperature also has a positive influence on module reliability. One of the other concerns of SiC packaging is the metallization of the bare die power devices. The surface finish for all SiC power devices is aluminum for the top side bond pads. This is understandable, since aluminum wire bonding is one of the most widely used means of interconnection. The bottom side finish is usually silver to aid wetting during the soldering process. The silver finish also facilitates advanced die attachment processes like silver sintering. To be able to implement wire bond-less procedures, a reliable and solderable top surface finish is required. One way to circumvent this issue is the use of pressure contacts on the top pads. However, there may be contact resistance issues using these methods that may need to be addressed. A metallurgical bond will require the top side finish to be a solderable metal. This may be done during device fabrication, or re-engineered during the assembly process by incorporating a plating, evaporation, or sputtering test. Electroless Ni/Ag has been a standard plating process for rendering IC chips solderable in the past, and it could work for power devices as well. However, there is no evidence to address the long term reliability of these approaches, especially in high temperature environments. There is no clear answer for an optimized metallization stack up that can attain the same thermal performance standards that SiC devices have been reported to have. Material concerns should not be limited to metallization alone. Interconnects and encapsulation materials should also withstand comparable thermal stresses. Perhaps the most exhaustive subject of thermo-mechanical stress analysis has been die attach materials. This is perhaps because the die attach interface is both electrically and thermally critical, and extremely prone to cracking under Energies 2017, 10, 341 5 of 30 thermal stress. There are analytical models of die attach materials and long-term reliability prediction algorithms based on these models. However, as the operating temperature rises, all parts of the package will assume importance and have to be thoroughly studied before it can be incorporated into a commercial product.

3. Trends in Wire Bonded Silicon Carbide Packaging SiC power devices have been predicted to have tremendous potential to be the next generation material in the semiconductor industry [1–3,19–21]. These devices have been shown to operate in extremely high ambient temperatures with very low degradation in performance [22]. The packaging methods employed for SiC power modules, however, have not witnessed much change from the traditional silicon die attach and wire bond process flow. This was not considered to be a huge obstacle until recently, since the SiC material system itself was found to be much superior to silicon. SiC devices performed much better than their Si counterparts, even while using standard packaging approaches. However, as engineers around the world are gaining a better understanding of SiC devices, the limits of the Si-based packaging schemes are becoming more evident. Most of these packaging approaches bear fundamental performance limits imposed by the physical limits of Si device physics. For example, wire bonding has sufficed as an interconnect technology in modules that switched at the safe operating limits of SiC power devices. Similarly, CTE mismatch stresses were tolerable in Si power modules, most of which were rated at much lower maximum operating temperatures as compared with SiC. As SiC power devices are demonstrated to operate in ambient temperatures pushing the 500 ◦C mark, most Si power module material choices will be rendered unusable. Nevertheless, even without employing unconventional and “out-of-the-box” packaging methods, SiC packaging efforts over the years have successfully demonstrated some noteworthy feats. A 2007 study from Arkansas Power Electronics International (APEI) Inc. (now Wolfspeed, Fayetteville, AR, USA) documented the test results of a 4 kW three-phase power inverter operating at a junction temperature of 250 ◦C[23]. The design and choice of packaging materials used was a combination of known-good approaches for MCMs using Si IGBTs. The power devices in the module were SiC JFETs. Extending the results to a 10 kW inverter based on an identical approach, the authors predicted a 75% overall decrease in the volume as compared with a comparable Si inverter. One major reason for this was the high temperature operability of the SiC devices, which reduced the requirement of volume-intensive thermal management methods. Most packages developed around this time did not push the envelope in terms of incorporating novel packaging materials, but there was a growing consensus among industry and academia for the need to think unconventionally to extract maximum benefits. This issue was addressed in a 2008 paper from General Electric, in which design choices were explored to ensure operation at 250 ◦C[24]. Substrates, die, attach materials, interconnects, and encapsulation materials were explored individually. Direct bonded copper (DBC) substrates were observed to fail within the first 20-30 cycles of testing, clearly exposing the need for new substrate technologies at higher temperatures. Sintered thick film silver metallization on alumina performed the best showing no failures up to 1000 thermal cycles. Direct bonded aluminum (DBA) on aluminum nitride also performed comparably and may be a high temperature alternative as well. As far as die attach materials were concerned, it was reported that 95Pb5Sn high temperature solder was good at absorbing CTE mismatch stresses. A novel miniature top-loading laminated bus structure was designed for this module. This enabled a low-inductance path to the power devices, and in-turn allowed them to switch at a faster frequency. Interconnect inductances were further reduced by using vertical spring-loaded pins instead of wire bonds. The spring-loaded pins were also reported to be more compliant under thermo-mechanical stress. Common epoxy mold compounds did not hold up to partial discharge testing under high temperatures. Nusil and Sylgard were the only compounds that yielded satisfactory performance up EnergiesEnergies 20172017,, 10,, 341 341 66 of of 30 30 satisfactory performance up to at least 400 hours of testing. The temperature for module testing howeverto at least was 400 limited h of testing. to 100 The °C, and temperature there was for no module documented testing data however for the was system/module limited to 100 reliability◦C, and withthere respect was no to documented time or temperature. data for the system/module reliability with respect to time or temperature. AA more more recent recent study study published published in in 2011 2011 documented documented the the design design benefits benefits of of SiC SiC power power converters converters overover silicon silicon based based converters converters [25]. [25]. In In this this stud study,y, a a 1.5 1.5 MW wind turbine frequency converter was was designed.designed. The The first first step step in in this this study study was was a a characterization characterization of of the the switching switching characteristics characteristics of of the the SiC SiC powerpower device device as as a a function of temperature. It It was was reported reported that that the the switching switching loss loss of of the the SiC device were almost unaffectedunaffected by by temperature, temperature, but but that that for for silicon silicon devices devices the lossesthe losses increased increased by 56.3% by 56.3% when whenthe case the temperature case temperature increased increased to 125 to◦C 125 from °C 25from◦C. 25 °C. TheThe systemsystem waswas also also analyzed analyzed at switchingat switching frequencies frequencies of 3 kHz of and3 kHz 50 kHz. and At50 both kHz. frequencies, At both frequencies,the losses associated the losses with associated the silicon with converter the silicon far converter exceeded far the exceeded SiC converter. the SiC The converter. loss in efficiency The loss infor efficiency a Si IGBT for beyond a Si IGBT 20 kHz beyond made 20 it unusable,kHz made while it unusable, the efficiency while ofthe the efficiency SiC converter of the evenSiC converter at 50 kHz evenexceeded at 50 85%.kHz This,exceeded of course, 85%. This, introduced of course, possibilities introduced for apossibilities significant reductionfor a significant in the sizereduction and cost in theof the size passive and circuitcost of elements the passive for the circuit filtering elemen circuitry.ts for The the power filtering losses circuitry. associated The with power the filtering losses associatedpassives were with also the reportedfiltering topassive decrease.s were also reported to decrease. AnotherAnother interesting interesting part part of ofthis this study study was was high high temperature temperature operation operation of the ofconverters. the converters. At an operatingAt an operating temperaturetemperature of 150 of°C 150the ◦volumeC the volume of the SiC of thebased SiC converter based converter was substantially was substantially smaller thansmaller the thanSi converter. the Si converter. Moreover, Moreover, the SiC converter the SiC converter did not didneed not liquid need cooling, liquid cooling, and the andoverall the overallcost of thecost heatsink of the heatsink was also was much also lower much lowerthan the than Si theconv Sierter. converter. At a junction At a junction temperature temperature of 300 of °C, 300 the◦C, situationthe situation improved improved further further for forthe the SiC SiC converter converter offe offeringring a 49.5% a 49.5% additional additional reduction reduction in in volume volume as as comparedcompared with thethe 150150◦ °CC converter. converter. Silicon Silicon power powe modulesr modules cannot cannot operate operate at theseat these temperatures, temperatures, and andSiC modulesSiC modules can go can even go highereven higher with the with appropriate the appropriate packaging packagin choices.g Unfortunately,choices. Unfortunately, no hardware no hardwarewas tested was over tested time toover validate time to the validate reliability the ofreliability operation of inoperation a 300 ◦C in ambient. a 300 °C ambient. AnAn effort effort from APEI Inc. in in conjunction conjunction with with the the University University of of Arkansas Arkansas in in 2008 2008 showcased a a leapleap in in next next generation packaging packaging for for SiC SiC modules [26]. [26]. The The highly highly integrated integrated half half bridge bridge module module (Figure(Figure 11)) waswas capablecapable ofof operatingoperating atat 250250 °C◦C and also won the R&D100 award in 2009.

FigureFigure 1. 1. TheThe high high temperature temperature half-bridge half-bridge SiC SiC modu modulele [26]. [26]. DBA: DBA: direct direct bonded bonded aluminum. aluminum.

The gate driver board was made of low temperature co-fired ceramic (LTCC) material capable The gate driver board was made of low temperature co-ﬁred ceramic (LTCC) material capable of withstanding high temperatures. The magnetics used were fabricated in-house in order to meet of withstanding high temperatures. The magnetics used were fabricated in-house in order to meet the temperature requirements, and the size of the passives were reduced considerably by driving the the temperature requirements, and the size of the passives were reduced considerably by driving the half-bridge at 150 kHz switching frequency. To enable an increased switching frequency, the gate half-bridge at 150 kHz switching frequency. To enable an increased switching frequency, the gate driver board was mounted directly atop the power stage to offer a low inductance vertical path for driver board was mounted directly atop the power stage to offer a low inductance vertical path for the the gate signal. The stacked approach also reduced the footprint of the module, enabling high gate signal. The stacked approach also reduced the footprint of the module, enabling high density density integration even at elevated temperatures. As a proposition for future work for reducing the integration even at elevated temperatures. As a proposition for future work for reducing the size and size and enhancing performance, it was discussed that the gate driver would be placed on the power stage to further reduce parasitics.

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Energiesenhancing 2017, performance,10, 341 it was discussed that the gate driver would be placed on the power stage7 of 30 to further reduce parasitics. For most applications involving high voltage slew rates at high temperatures, the choice of gate driver becomes a limitation. In In many many investigations, investigations, the the SiC SiC module module itself itself was was tested inside a high temperaturetemperature oven, oven, while while the the gate gate driver driver and and contro controlsls were were placed placed in in a a lower lower ambient ambient temperature. temperature. This problem was addressed in a 2015 publication by Wang Wang et al. [27], [27], in which a a silicon-on-insulator silicon-on-insulator (SOI) gate driverdriver waswas integratedintegrated with with a a SiC SiC power power module. module. The The integrated integrated module module shown shown in in Figure Figure2a 2awas was operated operated at aat temperature a temperature of 200 of ◦200C and °C and a switching a switching frequency frequency of 100 of kHz 100 (FigurekHz (Figure2b). This 2b). study This studybrings brings to light to the light importance the importance and necessity and necessity of gate of drivers gate drivers which matchwhich thematch performance the performance of the SiC of thepower SiC devices.power devices. A denser A integrationdenser integration of the gate of the driver gate and driver the and power the devices power woulddevices mean would that mean the thatdriver the chip driver also chip experiences also experiences similar temperaturessimilar temperatures as the power as the die. power die. From all the above studies, it was clear that the the performance performance of of a a module module is is package package limited. limited. Not one of the studies investigated revealed revealed that that SiC SiC had had failed failed as as a a material material at at high high temperatures. temperatures. All the expressed concernsconcerns dealtdealt withwith the the dearth dearth of of adequate adequate packaging packaging materials materials and and technologies technologies at atthese these temperatures. temperatures.

(a) (b)

Figure 2. (a) A photograph showing the module developed by Wang et al. [27]; and (b) waveforms Figure 2. (a) A photograph showing the module developed by Wang et al. [27]; and (b) waveforms showing the operation of the power converter. SOI: silicon-on-insulator; and MOSFET: showing the operation of the power converter. SOI: silicon-on-insulator; and MOSFET: metal-oxide- metal-oxide-semiconductor field-effect transistor. Reprint with permission [4062710688514]; semiconductor ﬁeld-effect transistor. Reprint with permission [4062710688514]; Copyright 2014, IEEE. Copyright 2014, IEEE.

The story of the high frequency applications of SiC bear a striking resemblance to the high temperaturetemperature applications. The The material material itself itself can can switch switch well well into into the the MHz MHz range. range. At At these these frequency frequency levels,levels, the the passives passives employed employed may may be be a fraction a fraction of the of thesize size compared compared with with what what is used is usedtoday. today. The overallThe overall system system cost, cost, volume, volume, weight, weight, and and losse lossess will will also also decrease. decrease. However, However, the the system implementationimplementation isis the the bottleneck. bottleneck. A highA high switching switch frequencying frequency implies implies a high a slew high rate slew for therate switching for the switchingcurrents and currents voltages. and Thisvoltages. induces This undesirable induces undesirable current spikes current through spikes the through parasitic the capacitances parasitic capacitancespresent within present thesystem, within the leading system, to leading a potential to a potential system failure system due failure to adue false to a switching false switching event. event.This phenomenon This phenomenon discourages discourages applications applicatio involvingns frequenciesinvolving frequencies in excess of in several excess hundred of several kHz. hundredNonetheless, kHz. switching Nonetheless, reliably switching and efﬁciently reliably at 50and kHz efficiently is in itself aat huge 50 kHz improvement is in itself over a siliconhuge improvement over silicon MOSFETs and IGBTs. This section explores notable efforts in pushing toward higher switching frequencies, and aims to identify the barriers that prevented a further increase in frequency.

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MOSFETs and IGBTs. This section explores notable efforts in pushing toward higher switching frequencies, and aims to identify the barriers that prevented a further increase in frequency. EnergiesA 2017 2003, 10 study, 341 by Elasser et al. [28] contrasted the performance of the then novel SiC diode against8 of 30 commercially available silicon diodes. Switching losses during reverse recovery at high di/dt were one of theA parameters2003 study ofby comparison, Elasser et al. and [28] the contrasted performance the was performance compared of at the room then temperature novel SiC as diode well againstas at 150 commercially◦C. The circuit available was tested silicon in adiodes. boost converterSwitching topology losses during switched reverse at 100 recovery kHz, with at high a silicon di/dt wereIGBT. one It is of important the parameters to note of that comparison, this was a and low th powere performance application was with compared a 500 W at full room load, temperature but it was assufﬁcient well as toat illustrate150 °C. The the circuit beneﬁts was of tested SiC technology in a boost andconverter the concerns topology with switched inferior at packaging 100 kHz, with of SiC a silicondevices. IGBT. Table It1 islists important the results to note of the that analysis. this was The a resultslow power showed application an order with of magnitude a 500 W full decrease load, but in itthe was switching sufficient losses to illustrate associated the with benefits the SiC of devices.SiC technology Furthermore, and the the concerns reduction with seemed inferior impervious packaging to ofan SiC increase devices. in junction Table 1 temperature, lists the results where of thethe lossesanalysis. for theThe silicon results based showed counterparts an order nearly of magnitude doubled decreasewith an identical in the switching temperature losses increase. associated with the SiC devices. Furthermore, the reduction seemed impervious to an increase in junction temperature, where the losses for the silicon based counterpartsTable 1. Performance nearly doubled comparison with an of identical Si vs SiC diodes temperature at 25 ◦C andincrease. 150 ◦C at 480 A/µs [28]. DUT: device under test. Reprint with permission [4062720248056]; Copyright 2003, IEEE. Table 1. Performance comparison of Si vs SiC diodes at 25 °C and 150 °C at 480 A/μs [28]. DUT: ◦ ◦ device under test. Reprint withDUT permissionTj = 25 [4062720248056];C Copyright DUT T2003,j = 150 IEEE.C

Fast SiDUT Ultra-FastTj = 25 °CSiC Fast Si Ultra-Fast DUT Tj = 150SiC °C Diode Si Diode Diode Diode Si Diode Diode Fast Si Ultra-Fast Si SiC Fast Si Ultra-Fast Si SiC DiodeDiode Diode Diode Diode Diode Diode 344 µJ 86 µJ 8 µJ 704 µJ 268 µJ 26 µJ Diode Losses Losses344 μJ 86 μJ 8 μJ 704 μJ 268 μJ 26 μJ IGBT IGBT Losses 320 μJ 320 µJ88 μ 88J µJ 5656µ μJJ 912912µJ μJ 172 µJ172 μ 56J µJ 56 μJ Losses Total 664 μJ 174 μJ 64 μJ 1616 μJ 440 μJ 92 μJ Total 664 µJ 174 µJ 64 µJ 1616 µJ 440 µJ 92 µJ

Several studies have been published since, which have supplemented the favorable recovery characteristicsSeveral studies of SiC haveSBDs. been It is hardly published surprising since, whichthat they have are supplemented ubiquitous in most the favorable high performance recovery powercharacteristics modules of that SiC are SBDs. produced It is hardly today. surprising In 2011, thatAdamowicz they are ubiquitouset al. [29] conducted in most high a similar performance study, withpower a cardinal modules difference. that are produced They fully today. appreciated In 2011, the Adamowicz benefits of eta near-zero al. [29] conducted reverse recovery a similar offered study, bywith SiC a cardinaldiodes, difference.but with caution They fully toward appreciated the implic the beneﬁtsations from of a near-zerothe standpoint reverse of recovery EMI. A offered 100 kHz by converterSiC diodes, was but constructed with caution using toward SiC the JFETs implications and SiC fromfreewheeling the standpoint diodes of (FWDs). EMI. A 100The kHz performance converter was also constructed contrasted using by using SiC JFETs a Si FWD and SiCin conjunction freewheeling with diodes the SiC (FWDs). JFETs. The performance was also contrastedFigure by3a using shows a Si the FWD turn-off in conjunction waveform with for the the SiC silicon JFETs. fast diode. The performance was unacceptableFigure3a at shows 100 kHz the with turn-off the reverse waveform recovery for the current silicon exceeding fast diode. 24 A Thewhile performance carrying just was2 A. Voltageunacceptable perturbations at 100 kHz were with also the reported reverse recoveryin the te currentst circuit exceeding as a result 24 Aof whileEMI with carrying magnitudes just 2 A. exceedingVoltage perturbations 1.5 kV. This were could also reportedpotentially in thekill test power circuit supplies, as a result gate of EMI drivers, with magnitudesand even the exceeding power devices1.5 kV. This themselves. could potentially kill power supplies, gate drivers, and even the power devices themselves.

(a) (b)

Figure 3. ComparisonComparison of of reverse reverse re recoverycovery transients transients using using ( (aa)) Si Si fast fast recovery recovery diode; diode; and and ( (b)) SiC diode [29]. [29]. Reprint Reprint with permissi permissionon [4062730593351]; Copyright 2011, IEEE.

Energies 2017, 10, 341 9 of 30

Figure3b shows the result for one of the SiC diodes under investigation. Oscillations could still be observed in the turn-off waveforms, but were tolerable. An interesting observation was that two diodes with similar characteristics showed slightly different damping on the gate-source signal. It was deduced that the source lead parasitic inductance contributed the gate-source ringing. This is another instance where it was proved yet again that the performance of the SiC device was packaging limited. The estimated lead inductances in the discrete components used for this study were reported to be around 20 nH. Since this time, most integration efforts have been focused on tighter integration to reduce interconnect inductances and mitigate the EMI arising as a consequence. This is a compelling reason for most major SiC manufacturers providing an additional Kelvin sense terminal in their discrete component packages [30]. A significant step forward in high frequency operation and its impact on system size and performance was presented in a 2013 publication from APEI Inc. and Toyota, in conjunction with the University of Arkansas [31]. The illustrated high power density plug in HEV battery charger also won an R&D 100 award in 2014. The designed converter was switched at a frequency of 500 kHz and yielded an efficiency of 93.4%. The efficiency increased to 96.5% as a result of decreasing the switching frequency to 200 kHz, which is still an impressive frequency as compared with the competition. The increase in switching frequency allowed the designers to reduce the size and weight of magnetics and relax the demands required by the heat sink. The result was a volumetric power density of 12 kW/L, and a gravimetric power density of 9.1 kW/kg. The weight was especially important since this module was designed to operate in a mobile system. The researchers reported that customized package design was a key enabler in being able to push the performance of SiC technology closer to what it is capable of. Design improvements included a customized low inductance power module. The gate driver board with the associated circuitry was mounted in close proximity with the power module. The power module was mounted on a MMC baseplate to reduce the CTE mismatch and weight, and facilitated high temperature operation. Even with these commendable efforts to leverage high frequency operation, the authors reported that the thermal management and the inductors used in the module comprised 73% of the weight, and 66% of the volume respectively. It was discussed that pushing the operating frequency beyond 500 kHz would help further volumetric gains, but it was not clearly stated what prevented the authors from doing so in this revision itself. In a separate publication in the same year, APEI reported that they had operated the X5 module at frequencies in excess of 1 MHz while maintaining an efficiency greater than 93% up to nearly 4 kW output power [32]. It was reiterated in the paper that the design philosophy for switching at these unprecedented frequencies relied heavily on tighter integration between the power devices, drive circuitry, and decoupling capacitors. The need for a high temperature and high frequency module was also the underlying motivation for a 1.2 kV, 120 A phase leg module using SiC devices by Chen et al. [33] in 2016. By optimizing the layout of the module, a 40% reduction in the switching loop inductance was possible, even while using wire bonded interconnections. The module was also demonstrated to operate at 200 ◦C junction temperature. The power module is shown in Figure4a. The substrate used was DBC with AlN as the ceramic—a common material if choice for SiC power modules. However, DBC substrates have gained a negative reputation for delamination during high temperature swings. To remedy this, a step-edge approach was used in which the edges of the copper traces on the DBC were etched so that they formed a tapered step on the edge. This makes the copper less prone to peeling under thermal stress [34]. A photograph showing the patterned substrate with a step-edge is shown in Figure4b. The parasitic ringing and overshoot for this module were reported to be 20% lower as compared with a commercial module even without embedding decoupling capacitors within the module. VDS slew rates as high as 13.9 V/ns were achieved with using a 0 Ω external gate resistor due to the favorable switching transient behavior. The overshoots and switching energy comparison is shown in Figure4c. No EMI related issues were reported despite the unprecedentedly high voltage slew rates. Energies 2017, 10, 341 10 of 30 Energies 2017, 10, 341 10 of 30

(a) (b)

(c)

Figure 4. (a) Photograph showing the power module; (b) step edge technology for improved Figure 4. (a) Photograph showing the power module; (b) step edge technology for improved reliability reliability at high temperatures; and (c) a comparison of switching performance between the (Center at high temperatures; and (c) a comparison of switching performance between the (Center for Power for Power Electronics Systems (CPES) module and a comparable commercial product. Electronics Systems (CPES) module and a comparable commercial product. Another noteworthy accomplishment in the recent past came from researchers at the Future RenewableAnother noteworthyElectric Energy accomplishment Delivery and inManage the recentment (FREEDM) past came center from researchers(North Carolina at the State Future RenewableUniversity, Electric Raleigh, Energy NC, USA). Delivery The andauthors Management in their abstract (FREEDM) mentioned center with (North respect Carolina to power State University,modules Raleigh, that “The NC, era USA). for Thehigh authors voltage-megahertz in their abstract switching mentioned has witharrived respect [35].” to A power 1.5 MHz modules synchronous boost converter and a 3.68 MHz half bridge inverter were demonstrated. Figure 5a that “The era for high voltage-megahertz switching has arrived [35].” A 1.5 MHz synchronous boost shows a photograph of the top view of the power module. It can be noticed that the gate drivers for converter and a 3.68 MHz half bridge inverter were demonstrated. Figure5a shows a photograph of the respective switches were mounted as close as possible to the power die on the power module the top view of the power module. It can be noticed that the gate drivers for the respective switches itself. This resulted in a significant reduction in the gate loop parasitic inductance and prevented werefalse mounted turn on aseffects close due as to possible the EMI to generated the power at the die high on thedv/d powert levels modulegenerated itself. in the This circuit. resulted Figure in a significant5b shows reduction a photograph in the gateof the loop module parasitic with inductance the heatsink, and and prevented Figure 5c false shows turn the on effectsswitching due to the EMIwaveforms. generated at the high dv/dt levels generated in the circuit. Figure5b shows a photograph of the moduleThe withefforts the presented heatsink, in and this Figuresection5 csummarize shows the admirable switching research waveforms. to place SiC technology a cutThe above efforts conventional presented silicon in this power section modules summarize in terms admirable of performance. research All to the place above SiC approaches technology a cut aboveused existing conventional packaging silicon technologies power modulesand material ins terms in novel of performance.ways, and employed All the good above engineering approaches usedpractices existing to packaging develop next technologies generation and power materials electronics in novel modules. ways, However, and employed the achievements good engineering still practicesgrossly to underutilized develop next the generation full gamut powerof performance electronics benefits modules. that SiC However, devices have the achievementsto offer. One of still grosslythe key underutilized enablers in thepushing fullgamut performance of performance would be the benefits interconnect that SiC technology. devices have to offer. One of the Some issues are common for the packaging and integration of any class of semiconductor key enablers in pushing performance would be the interconnect technology. technology. Heat sinks and passive devices are two examples of such issues. Be it silicon, SiC, or Some issues are common for the packaging and integration of any class of semiconductor GaN—these components occupy maximum space and weight in the package. Using WBG technology.technology Heat to help sinks relax and thepassive demands devices of a big areandtwo heavy examples heat sink ofmay such alleviate issues. the Beissue it from silicon, the SiC, or GaN—thesestandpoint ofcomponents thermal management. occupy maximumIt will also spaceencourage and innovations weight in thein heat package. sink technology. Using WBG technologyHowever, to efficiency help relax is thereally demands a more dominant of a big andconcern heavy in power heat sink converters. may alleviate Producing the efficient issue from the standpointtopologies and of thermalpackaging management. solutions may It not will even also cr encourageeate substantial innovations waste heat in to heat begin sink with. technology. This However,coupled efficiency with the high is really temperature a more operability dominant of concernSiC devices in have power the converters. potential of greatly Producing impacting efficient topologiesthe volume and occupied packaging by solutionsthe thermal may management not even createin a power substantial module. waste A far as heat passive to begin devices with. are This coupledconcerned, with the significant high temperature reductions operabilityin size and ofweight SiC devicesare possible have when the potential switching of frequencies greatly impacting are the volumeincreased, occupied as have been by the documented thermal management by several of the in aforementioned a power module. research A far efforts. as passive devices are concerned, significant reductions in size and weight are possible when switching frequencies are increased, as have been documented by several of the aforementioned research efforts. Energies 2017, 10, 341 11 of 30 Energies 2017, 10, 341 11 of 30

(a) (b)

(c)

FigureFigure 5. 5.A A3.68 3.68 MHz MHz SiC SiC power power module module from from the FREEDM centercenter atat NorthNorth Carolina Carolina State State UniversityUniversity [35]. [35 ].EN: EN: enable; enable; IN: IN: input; input; VDD: VDD: drain voltage; andand GND:GND: ground. ground. ( a()a A) A photograph photograph showingshowing the the top top view view of of the the module; module; ( (bb)) a a photograph photograph showing thethe whole whole module module assembly assembly with with the the heatheat sink; sink; and and (c ()c test) test waveforms waveforms showing showing the the switching characteristicscharacteristics of of the the module. module. Reprint Reprint with with permissionpermission [4062731030342]; [4062731030342]; Copyright Copyright 2015, 2015, IEEE.

4. Wire4. Wire Bondless Bondless Packaging—The Packaging—The Road Road Forward? Forward? TheThe quality quality and and reliability reliability ofof powerpower modules modules has has a direct a direct influence influence on resource on resource utilization, utilization, the cost the costof of production, production, and and energy energy efficiency efficiency in in the the industry. industry. We We are are at at the the peak peak of of global global electrification, electrification, andand the the trends trends predict predict a asteady steady increase increase in thethe foreseeableforeseeable future.future. TheThesphere sphere of of applications applications of of electronicelectronic modules modules is isever-increasing—and ever-increasing—and it it is is perhaps perhaps time toto movemove pastpast thethe “one “one size size fits fits all” all” packagingpackaging solutions solutions thatthat havehave been been strongly strongly adhered adhered to up toto now.up to Conventional now. Conventional packaging materialspackaging materialsand methods and methods have been have known been toknown perform to perform poorly under poorly both under thermal both andthermal electrical and electrical stress. Hence, stress. Hence,applications applications involving involving harsh environmentsharsh environments have typically have beentypically most been accepting most of accepting novel packaging of novel packagingtechnologies. technologies. In fact, most In fact, innovations most innovations pertaining pertaining to the field to of the electronics field of packaging electronics have packaging been havetargeted been towardtargeted applications toward applications with harsh with temperatures, harsh temperatures, harsh environments, harsh environments, high power levels, high largepower levels,voltage large swings—or voltage swings—or any combinations any combinations thereof. thereof. In their 2011 paper summarizing the challenges in power packaging, Liu and Kinzer [36] from In their 2011 paper summarizing the challenges in power packaging, Liu and Kinzer [36] from Fairchild Semiconductor hailed SiC as a foreseeable future replacement for silicon power devices. Fairchild Semiconductor hailed SiC as a foreseeable future replacement for silicon power devices. However, they agreed that the interconnection scheme had to improve. They discussed alternatives to However, they agreed that the interconnection scheme had to improve. They discussed alternatives conventional wire bonding—such as copper ball bonding, wedge bonding, clip connections, copper to conventional wire bonding—such as copper ball bonding, wedge bonding, clip connections, stud bumps, flip-chip bonding, etc. Many of these approaches will be discussed in due course. They copper stud bumps, flip-chip bonding, etc. Many of these approaches will be discussed in due also discussed that as SiC chip sizes shrink, there needs to be effective mechanisms for increased course.heat transfer.They also Double-sided discussed that cooling as SiCcan chip be sizes explored shrink, as there an example, needs to by be adoptingeffective wiremechanisms bondless for increasedsandwich-type heat transfer. modules. Double-sided cooling can be explored as an example, by adopting wire bondless sandwich-type modules. In 2007, Bower et al. [37] documented some of the common issues that were being reported in relation to the failure of SiC modules. Unsurprisingly, wire bond fatigue topped their list, in itself accounting for the most failures associated with a single component (Figure 6a). Figure 6b,c shows the dominant failure mechanisms in wire bonds.

Energies 2017, 10, 341 12 of 30

In 2007, Bower et al. [37] documented some of the common issues that were being reported in Energiesrelation 2017, 10 to, 341 the failure of SiC modules. Unsurprisingly, wire bond fatigue topped their list, in itself12 of 30 accounting for the most failures associated with a single component (Figure6a). Figure6b,c shows the dominantWire bond failure lift mechanismsoff occurs indue wire to bonds. the same reason that solder interfaces fail—due to CTE mismatchWire stresses bond liftbetween off occurs the due bond to the pad same and reason bonding that soldermaterial. interfaces However, fail—due the to CTE CTE of mismatch the metals usedstresses for wire between bonding the differ bond padby a and large bonding margin material. from the However, substrate the CTEmaterials of the metalsas shown used in for Figure wire 7a. Hence,bonding they are differ prone by a largeto fail margin much fromsooner the under substrate repeated materials thermal as shown stress in Figure or high7a. Hence,temperature they are than a solderprone joint to would. fail much In sooner fact, CTE under is repeatednot all that thermal materials stress orfor high a thermo-mechani temperature thancal a solder stress. joint Even would. eutectic solderIn fact,and CTEsintered is not silver all that have materials a high for aCTE, thermo-mechanical but they are stress.better Even at absorbing eutectic solder thermo-mechanical and sintered stressessilver due have to atheir high low CTE, Young’s but they modulus. are better atFigure absorbing 7b shows thermo-mechanical a comparison stresses of the due Young’s to their modulus low of wireYoung’s bonding modulus. metals Figure and7 bcommon shows a comparisondie attach materials. of the Young’s modulus of wire bonding metals and common die attach materials. To improve the mechanical strength of wire bonds, some measures have also been taken to To improve the mechanical strength of wire bonds, some measures have also been taken to utilize utilize thick Cu/Al-Bi ribbon bonding instead of aluminum [38]. However, like with most copper thick Cu/Al-Bi ribbon bonding instead of aluminum [38]. However, like with most copper wire wire bondingbonding approaches, approaches, this hasthis the has risk ofthe damaging risk of the damaging die due to excessivethe die bondingdue to force/energyexcessive bonding [36]. force/energyRibbon bonding [36]. Ribbon does not, bonding however, does solve not, the howeve problemr, ofsolve connecting the problem the gate of padconnecting of a SiC MOSFET.the gate pad of a SiCWith MOSFET. the shrinking With die the sizes shrinking of SiC devices, die sizes justifying of SiC devices, the use of justifying ribbon bonding the use is of going ribbon to become bonding is goingincreasingly to become more increasingly difﬁcult. Also,more any difficult. type of Also, wire bondingany type technology of wire bonding eliminates technology the possibility eliminates of the possibilitydouble-sided of coolingdouble-sided or 3D integration, cooling or which 3D in bringstegration, us to which our next brings topic. us to our next topic.

(a) (b)

(c)

FigureFigure 6. ( 6.a) (aA) Apie-chart pie-chart depictingdepicting the the failure failure modes modes in SiC in power SiC modules;power modules; (b) a photograph (b) a showingphotograph showingwire bondwire liftbond off; lift and off; (c) aand photograph (c) a photograph showing wire showing bond heelwire fracture bond heel [37]. Reprintfracture with [37]. permission Reprint with permission[4062731448789]; [4062731448789]; Copyright Copyright 2008, IEEE. 2008, IEEE.

Energies 2017, 10, 341 13 of 30 Energies 2017, 10, 341 13 of 30

Sintered Silver

Eutectic solder

Gold

Copper

Aluminum

0 20406080100120

Young's Modulus (GPa) (a) (b)

Figure 7. A bar graph comparing the (a) coefficient of thermal expansion (CTE) and (b) Young’s Figure 7. A bar graph comparing the (a) coefficient of thermal expansion (CTE) and (b) Young’s modulus of materials used in a state-of-the-art SiC power module. modulus of materials used in a state-of-the-art SiC power module. 5. 3D Integration Efforts 5. 3D Integration Efforts There have been several attempts to provide better alternatives to wire bonding through 3D wireThere bondless have beentechnology. several Although attempts tothe provide industry better has adopted alternatives a handful to wire of bondingthese propositions, through 3D most wire bondlessof the technology.proposed solutions Although exist the only industry as proof-of-con has adoptedcept. a handfulThe main of explanation these propositions, for this is most that ofthe the proposedreliability solutions and performance exist only asbenefits proof-of-concept. offered by a la Therge mainmajority explanation of these solutions for this iscan that seldom the reliability justify andthe performance cost of a complete benefits retooling offered of by a amanufacturing large majority facility. of these If a solutions simple solder canseldom and wire justify bond thebased cost of amodule complete of retoolingsufficient ofengineering a manufacturing quality facility. meets Ifthe a simpletarget soldermodule and lifetime wire bond with based satisfactory module of sufficientperformance, engineering there is hardly quality a need meets to think the target about module 3D solutions. lifetime However, with satisfactory this situation performance, is rapidly therechanging is hardly with a needelevated to think demands about on 3D the solutions. performance However, and operating this situation conditions is rapidly that power changing modules with elevatedare expected demands to meet. on the There performance are numerous and operatingother adva conditionsntages to be that realized power in modules a well-engineered are expected and to meet.non-conventional There are numerous packaging other advantagesscheme—decreased to be realized material in a well-engineeredcosts, faster performance, and non-conventional reduced packagingelectromagnetic scheme—decreased interference, material and improved costs, faster thermal performance, management reduced to electromagneticname a few. Among interference, the andinnovative improved schemes thermal managementproposed in the to namelast 5–10 a few. years, Among only the a few innovative have managed schemes to proposed successfully in the lasttransition 5–10 years, into only a commercial a few have module managed from to a successfullyproof-of-concept. transition into a commercial module from Power electronics packaging has always borrowed liberally from microelectronics packaging a proof-of-concept. advances in the past. Most of the chip-on-board, flip-chip, and 3D through silicon via (TSV) research Power electronics packaging has always borrowed liberally from microelectronics packaging that exists in the literature is targeted toward low power microelectronics or sensor applications advances in the past. Most of the chip-on-board, flip-chip, and 3D through silicon via (TSV) [39–44]. Low power RF circuits have also adopted wire bondless BGA-based packaging methods as research that exists in the literature is targeted toward low power microelectronics or sensor state-of-the-art due to the parasitic reduction offered by such 3D integration schemes, reduced cost, applicationsand reliability[39– 44benefits]. Low [45–48]. power There RF circuits is also have a wealth also of adopted literature wire in support bondless of BGA-basedthe favorable packaging aspects methodsof BGAs. as In state-of-the-art fact, an application due to note the from parasitic Fairchild reduction Semiconductor offered bya silicon such 3DBGA integration package has schemes, been reduceddescribed cost, as and a step reliability in the benefitsdirection [45 of– 48realizin]. Thereg the is also“perfect a wealth MOSFET” of literature [49]. However, in support in ofthis the favorableinvestigation aspects we of only BGAs. intend In fact,to include an application the advances note in from 3D/wire Fairchild bondless Semiconductor power module a siliconpackaging BGA packagein detail. has been described as a step in the direction of realizing the “perfect MOSFET” [49]. However, in this investigationMost of the 3D we packaging only intend solutions to include proposed the advances to date utilize in 3D/wire Si devices. bondless These power propositions module packagingcame at ina detail.time when Si technology was hitting a limit in terms of performance. Wire bondless integrationMost of the offered 3D packaging hope from solutions the standpoint proposed of be totter date signal utilize integrity Si devices. and reliability. These propositions The inherent came at aproperties time when of SiWBG technology were found was to hitting be so amuch limit more in terms superior of performance. to their existing Wire Si bondless counterparts, integration that offeredeven hopestandard from Si the MOSFET standpoint and IGBT of better packaging signal integritytechniques and used reliability. for packag Theing inherent SiC devices properties reapedof WBGhuge were benefits. found toThis be sosituation much moremust superiorchange towith their the existing realization Si counterparts, that the Si-based that even packaging standard Si MOSFETapproaches and were IGBT tailored packaging to the performance techniques used limits for of packagingSi semiconductor SiC devices technology. reaped It is huge instructive benefits. Thisto situation take a close must look change at what with benefits the realization 3D packaging that techniques the Si-based had packaging for Si packaging, approaches and reflect were tailored upon to thewhether performance this is the limits path ofto Sifollow semiconductor for highly integrated technology. SiC It modules. is instructive to take a close look at what The power overlay technology proposed by General Electric in 1995 [50] was also presented as a benefits 3D packaging techniques had for Si packaging, and reflect upon whether this is the path to viable approach for wire bondless interconnections (Figure 8). In this technology, the flexible follow for highly integrated SiC modules. interposer is 2 mil thick Kapton polyimide film. Vias are formed on top of the power device The power overlay technology proposed by General Electric in 1995 [50] was also presented as a viable approach for wire bondless interconnections (Figure8). In this technology, the flexible interposer Energies 2017, 10, 341 14 of 30 EnergiesEnergies 2017 2017, 10, 10, 341, 341 14 of14 30 of 30 isconnections 2connections mil thick by Kapton by laser laser polyimideablation, ablation, andand film. areare Vias metallized are formed byby sputtering onsputtering top of theor or plating power plating deviceto to form form connections interconnections. interconnections. by laser ablation,SurfaceSurface mount and mount are devices metallizeddevices couldcould by sputtering bebe directlydirectly or platingmounted tod on formon toptop interconnections. ofof thethe power power devices, Surfacedevices, mountand and vertical devicesvertical couldinterconnectionsinterconnections be directly mounted ensuredensured on thatthat top the ofthe the parasiticparasitic power devices,circcircuituit elements andelements vertical werewere interconnections reduced reduced significantly. significantly. ensured thatThis This the parasitictechnologytechnology circuit was waselements capable capable of wereof handlinghandling reduced highhigh significantly. operating voltages Thisvoltages technology of of up up to to was2400 2400 capableV Vand and a of devicea handlingdevice power power high operatingdissipationdissipation voltages of of up up to to of 200 200 up W. toW. 2400 V and a device power dissipation of up to 200 W.

Figure 8. A schematic showing the cross section of the General Electric (GE) power overlay technique Figure 8. A schematic showing the cross section of the General Electric (GE) power overlay Figure[48]. Reprint8. A schematic with permission showing [4062740331943]; the cross section Copyright of the General 1995, ElectricIEEE. (GE) power overlay technique technique[48]. Reprint [48 ].with Reprint permission with permission [4062740331943]; [4062740331943]; Copyright Copyright 1995, IEEE. 1995, IEEE. The skin interconnect technology introduced by Semikron in 2011 (Figure 9) was a major step towardsTheThe skinskin both interconnectinterconnect wire bond-less technologytechnology interconnections, introduced as well by as Semikron 3D integration in 2011 [51]. (Figure Metal9 9) )traces waswas a printeda major major on step step towardstowardsa flexible bothboth foil wirewire serve bond-less bond-less as interconnections. interconnections, interconnections, This as foilas well wellhas as aspatterns 3D 3D integration integration that mate [51 [51]. directly]. Metal Metal on traces traces top printedof printed power on on a flexiblea flexibledevices foil andfoil serve connectserve as interconnections.as to interconnections. them by silver This sintering This foil hasfoil technology. patterns has patterns that A 400 mate that A, 600 directlymate V dual directly on IGBT top ofon modulepower top of using devices power anddevicesSKiN connect interconnectionsand connect to them to by them silverwas fabricated.by sintering silver sintering The technology. thermal technology. solution A 400 A, A used 600400 for VA, dual 600this V IGBTmodule dual module IGBT is a pinmodule using fin heat SKiNusing interconnectionsSKiNsink interconnectionswhich is wasalso fabricated.sintered was fabricated. to The the thermal substrate, The thermal solution and is usedsolution fluid for cooled. thisused module for This this isensures module a pin fin high is heat a reliabilitypin sink fin which heat issink alsoperformance which sintered is for toalso thethe sintered substrate,module [52]to and theas compared is substrate, fluid cooled. to anconventionald This is fluid ensures soldercooled. high techno reliabilityThislogy. ensures The performance wire high bond-less reliability for the moduleperformanceSKiN [module52] as for compared showed the module an to average conventional [52] as reductioncompared solder of to technology.9.68 conventional% in parasitics The solder wire over bond-lesstechno a comparablelogy. SKiN The module wirewire bonded bond-less showed anSKiNmodule. average module It reduction was showed apparent of an 9.68% averagefrom in the parasitics reduction inspection over of of a9.68 the comparable %failure in parasitics mechanisms wire bondedover thata comparable module. the joint It between was wire apparent bonded the frommodule.flexible the inspectionItfoil was and apparent the of power the from failure device the mechanisms is inspection the weak linkof that the in the powerfailure joint cycling betweenmechanisms tests. the It flexible thatmust the be foil jointmentioned and between the powerthat the deviceflexiblethe SKiN is foil the moduleand weak the link survivedpower in power device more cycling ispower the weak tests.cycles Itlink than must in any power be comparable mentioned cycling tests. thatstate-of-the-art the It must SKiN be module(SOA) mentioned module survived that moretheusing SKiN power wire module cyclesbonds survived thanand bettered any comparablemore them power by state-of-the-artat cycles least anthan order any (SOA) of comparable magnitude. module usingstate-of-the-art wire bonds (SOA) and betteredmodule themusing bywire at leastbonds an and order bettered of magnitude. them by at least an order of magnitude.

Figure 9. Exploded view of the SKiN module from Semikron [51]. Reprint with permission [4062740751911]; Copyright 2011, IEEE. Figure 9. Exploded view of the SKiN module from Semikron [51]. Reprint with permission FigureIn 2012, 9. theExploded planar viewinterconnect of the SKiNtechnology module (SiP fromLIT) Semikronmodule from [51]. Siemens Reprint was with realized, permission which [4062740751911]; Copyright 2011, IEEE. utilized[4062740751911]; copper plating Copyright over a 2011, conformally IEEE. deposited insulation layer to form interconnections [53]. TheIn vias 2012, or theopenings planar in interconnect the insulating technology layer form (SiPed LIT)interconnections module from to Siemens the power was die realized, bond pads, which andIn was 2012, achieved the planar by interconnectthe layer structuring technology process. (SiPLIT) Because module of using from planar Siemens interconnections, was realized, whichthe utilized copper plating over a conformally deposited insulation layer to form interconnections [53]. utilizedstray inductance copper plating in these over power a conformally modules showed deposited a 50% insulation decrease layeras compared to form to interconnections conventional wire [53 ]. The vias or openings in the insulating layer formed interconnections to the power die bond pads, Thebonded vias or modules. openings The in theon state insulating resistance layer showed formed a interconnections30% decrease. to the power die bond pads, and and was achieved by the layer structuring process. Because of using planar interconnections, the was achieved by the layer structuring process. Because of using planar interconnections, the stray stray inductance in these power modules showed a 50% decrease as compared to conventional wire bonded modules. The on state resistance showed a 30% decrease.

Energies 2017, 10, 341 15 of 30 inductance in these power modules showed a 50% decrease as compared to conventional wire bonded modules. The on state resistance showed a 30% decrease. TheEnergies thermal 2017, 10, resistance341 offered by this packaging scheme was also lower than an aluminum15 of 30 wire bonded module; and the least thermal resistance was realized by using liquid cooling. From failure The thermal resistance offered by this packaging scheme was also lower than an aluminum analysis results, it could be ascertained that the failure occurred at the junction between the copper wire bonded module; and the least thermal resistance was realized by using liquid cooling. From interconnect layer and the silicon power device. The onset of failure, however, was much delayed failure analysis results, it could be ascertained that the failure occurred at the junction between the as comparedcopper interconnect with an aluminum layer and the wire silicon bonded power module. device. ThisThe onset was attributedof failure, however, to the fact was that much copper was adelayed relatively as compared better match with toan siliconaluminum with wire regard bonded to themodule. CTE This as compared was attributed to aluminum. to the fact Anotherthat reasoncopper was becausewas a relatively this interconnect better match technology to silicon with had regard a larger to surfacethe CTE area as compared of contact to withaluminum. the power die andAnother thus reason the thermomechanical was because this interconnect stresses were techno distributedlogy had a more larger uniformly. surface area This of contact was one with of the only studiesthe power that die published and thus the a comprehensivethermomechanical reliability stresses were analysis distributed to quantify more uniformly. that this approach This was met industryone standards.of the only studies that published a comprehensive reliability analysis to quantify that this Chip-scaleapproach met packaging industry standards. of integrated power modules was explored by Liu et al. [54] in 2001 as Chip-scale packaging of integrated power modules was explored by Liu et al. [54] in 2001 as a a plausible approach to improve the performance of Si IGBT power modules using 3D packaging plausible approach to improve the performance of Si IGBT power modules using 3D packaging techniques. Figure 10a shows a photograph of the solder ball bumped devices flip-chipped onto the techniques. Figure 10a shows a photograph of the solder ball bumped devices flip-chipped onto the substrate.substrate. An 8.6%An 8.6% percent percent voltage voltage overshoot overshoot waswas observed for for the the flip-chip flip-chip module module as compared as compared withwith 14% 14% overshoot overshoot of aof commercially a commercially available available wirewire bonded module module (Figure (Figure 10b). 10 b).The Thereliability reliability ◦ ◦ reportsreports suggested suggested that that under under thermal thermal cycling cycling formform 0 °CC to to 100 100 °C Cthe the resistance resistance of the of thesolder solder ball ball interconnectsinterconnects did notdid degradenot degrade after afte atr least at least 2800 2800 cycles, cycles, and and that that all all specimens specimens were were functionally functionally intact after 4000intact cycles.after 4000 cycles. In 2004,In 2004, another another integrated integrated flip-chip flip-chip module module incorporatingincorporating a aflex-circuit flex-circuit was was demonstrated demonstrated to to havehave 40% 40% lower lower voltage voltage overshoot overshoot and and 24% 24% lowerlower losses as as a a result result of of implementing implementing wire wire bondless bondless techniques [55]. Figure 11 shows the schematic of the module and the electrical benefits of the techniques [55]. Figure 11 shows the schematic of the module and the electrical benefits of the flip-chip flip-chip bonding method over commercially available discrete devices. Although this is a low bonding method over commercially available discrete devices. Although this is a low power module power module using Si devices, the benefits directly transfer to modules in the higher power usingrange—especially Si devices, the benefits since the directly voltage transfer and current to modules slew rates in encountered the higher power will be range—especially more severe as thesince the voltagepower levels and current rise. slew rates encountered will be more severe as the power levels rise.

(a)

(b)

Figure 10. Flip-chip integrated power module showing: (a) a photograph of the flip-chipped devices; Figure 10. Flip-chip integrated power module showing: (a) a photograph of the flip-chipped devices; and (b) the switching waveforms for a module using commercially packaged wire bonded devices and ((bleft) the) and switching the flip-chip waveforms on flex (FCOF) for a module module (right using) [54]. commercially Reprint with packaged permission wire [40627500 bonded66013]; devices (left)Copyright and the flip-chip 2001, IEEE. on flex (FCOF) module (right)[54]. Reprint with permission [4062750066013]; Copyright 2001, IEEE.

Energies 2017, 10, 341 16 of 30 Energies 2017, 10, 341 16 of 30

Energies 2017, 10, 341 16 of 30

(a)

(b) (c)

Figure 11. Flip-chip on flex package showing (a) a schematic of the package cross-section; (b) the Figureexperimental 11. Flip-chip waveforms on flex showing package a reduct showingion in the (a )turn-off a schematic transients; of and the (c) package the reduction cross-section; in (b) (c) (b) the experimentalswitching energy waveforms losses as a showingresult of wire a reduction bondless packaging in the turn-off methods. transients; Reprint with and permission (c) the reduction in switchingFigure[4062750364316]; 11. energy Flip-chip losses Copyright on flex as a package result2004, IEEE. of showing wire bondless (a) a schematic packaging of the methods. package Reprintcross-section; with ( permissionb) the [4062750364316];experimental Copyrightwaveforms 2004,showing IEEE. a reduction in the turn-off transients; and (c) the reduction in switchingIn 2011, energy Fuji Electric losses as[56] a resultproposed of wire the bondleuse ofss copper packaging pins methods.to connect Reprint to the withdevice permission bond pads instead[4062750364316]; of wire bonds(Figure Copyright 2004, 12). The IEEE. copper pins fit into the through-hole connections on the power Incircuit 2011, Fujiboard. Electric The copper [56] pins proposed were attached the use to of the copper bond pad pins of to the connect power device to the using device solder. bond pads insteadConnections ofIn wire2011, bonds(FigureFuji to theElectric bottom [56] side12 prop). of Theosedthe die copperthe were use maof pins decopper using fit intopins copper theto copins through-holennect as well. to the There device connections were bond several pads on the powerinstead circuitadvantages of wire board. of bonds(Figure this The design copper apart 12). The pinsfrom copper werethe obvious pins attached fit reduction into to the the through-holein bondparasitic pad circuit connections of theelements: power on thethe device DBCpower using solder.circuit Connectionssurface board. did Thenot to copperneed the bottompatterning pins we side reand attached of hence the die theto were thethermal bond made resistancepad using of the offered copper power bypins device this as scheme using well. Theresolder.was were significantly lower than conventional methods in which the DBC must be patterned, thus severalConnections advantages to the of bottom this design side of apartthe die from were themade obvious using copper reduction pins as in well. parasitic There were circuit several elements: eliminating conductive copper from the DBC surface and compromising thermal conductivity. The advantages of this design apart from the obvious reduction in parasitic circuit elements: the DBC the DBCmodule surface used did a notrigid need epoxy patterning molding compound and hence instead the thermalof soft silicone resistance encapsulants offered normally by this schemeused was surface did not need patterning and hence the thermal resistance offered by this scheme was significantlyin wire lower bonded than modules. conventional It was shown methods in thisin study which thatthe rigid DBC epoxy must induced be patterned, 35% less strain thus on eliminating the significantly lower than conventional methods in which the DBC must be patterned, thus conductivesolder copper connections from theas compared DBC surface to using and silicones. compromising Another thermalinteresting conductivity. feature that was The revealed module used a eliminating conductive copper from the DBC surface and compromising thermal conductivity. The rigid epoxythrough molding reliability compound testing was instead that theof chief soft failure silicone mode encapsulants in this topology normally was the usedinterfacial in wire joint bonded modulematerial, used namely a rigid the epoxy solder. molding A fin heat compound sink was insteadused for ofheat soft removal. silicone encapsulants normally used modules.in wire It bonded was shown modules. in this It studywas shown that rigidin this epoxy study inducedthat rigid 35% epoxy less induced strain on35% the less solder strainconnections on the as comparedsolder connections to using silicones. as compared Another to using interesting silicones. feature Another that interesting was revealed feature through that was reliability revealed testing was thatthrough the reliability chief failure testing mode was in that this the topology chief failure was mode the interfacial in this topology joint material, was the interfacial namely thejoint solder. A finmaterial, heat sink namely was used the solder. for heat A fin removal. heat sink was used for heat removal.

(a) (b)

Figure 12. Cont. Energies 2017, 10, 341 17 of 30 Energies 2017, 10, 341 17 of 30

(c)

Figure 12. Copper pin interconnected epoxy molded design from Fuji Electric Co., Ltd. Showing: (a) Figure 12. Copper pin interconnected epoxy molded design from Fuji Electric Co., Ltd. Showing: a schematic of the cross-section of the package; (b) loss comparison between the developed structure a b ( ) a schematicand wire bonded of the cross-sectionSiC and Si variants; of the package; and (c) reliability ( ) loss comparison curves agains betweent junction the temperature developed structureand and wireinterconnect bonded type SiC [56]. and Reprint Si variants; with permission and (c) reliability[4062741117252]; curves Co againstpyright 2012, junction IEEE. temperature and interconnect type [56]. Reprint with permission [4062741117252]; Copyright 2012, IEEE. The metal post interconnected parallel plate structure (MPIPPS) module design was part of the Thepower metal electronic post interconnectedbuilding block (PEBB) parallel initiative plate structure at Virginia (MPIPPS) Tech [57,58]. module A 15 design kW inverter was part was of the constructed that was capable of switching at 20 kHz, at least twice as fast as the switching speed power electronic building block (PEBB) initiative at Virginia Tech [57,58]. A 15 kW inverter was achieved using a comparable wire bonded device. constructed that was capable of switching at 20 kHz, at least twice as fast as the switching speed Vertical copper posts were used to connect a driver DBC to an underlying DBC populated with achievedpower using devices. a comparable The copper wire “posts” bonded in this device. approach were separate from copper “pins” (from Fuji VerticalElectric) in copper that they posts contacted were used a larger to connect area of the a driver bond DBCpad. This, to an the underlying authors claimed DBC populatedprovided a with powerlarger devices. contact The area copper for thermally “posts” induced in this approachstress distribution were separate in the copper from copperpost. It “pins”also reduced (from Fuji Electric)current in thatcrowding they contactedat the junction a larger between area the of inte therconnection bond pad. post This, and the the authorspower device claimed bond provided pad. a larger contactThis study area for also thermally included induceda detailed stress survey distribution of materials inthat the were copper as closely post. Itmatched also reduced in CTE currentas crowdingphysically at the possible junction in betweenorder to thereduce interconnection thermal stress post at the and various the power material device interfaces. bond pad.This was Thiscrucial study and alsohad a included direct impact a detailed on module survey lifeti ofme. materials Inter-layers that werelike thermal as closely interface matched materials in CTE as (TIMs) have also been considered. A poorly engineered interface layer drastically increases the physically possible in order to reduce thermal stress at the various material interfaces. This was crucial thermal resistance of the module. Minimizing the number of interfaces from the chip to the heat sink and had a direct impact on module lifetime. Inter-layers like thermal interface materials (TIMs) have had been proposed as a crucial aspect of the PEBB design philosophy. also beenOne considered. encouraging A poorly fact was engineered revealed from interface the MP layerIPPS module—even drastically increases a silicon theMOSFET thermal could resistance be of theswitched module. at Minimizing a frequency theof 20 number kHz by ofadopting interfaces a wire from bondless the chip packaging to the heat scheme. sink This had beenwas easily proposed as a crucialdouble aspectthe frequency of the PEBBof any designcomparable philosophy. wire bonded silicon power module of the time. Using the Onecopper encouraging posts reduced fact the was parasitic revealed inductance from the of MPIPPSthe interconnects module—even to less than a silicon 2 nH, MOSFETthus enabling could be switchedsilicon at technology a frequency to be of pushed 20 kHz to by its adoptingtheoretical a limits. wire bondless packaging scheme. This was easily double theIn frequencyaddition to ofthe any above comparable power modules wire it bonded is important silicon to mention powermodule a few commercial of the time. MOSFET Using the coppermodules posts reducedbased on thewire parasitic bondless inductance technology. of Although the interconnects they were tooriginally less than designed 2 nH, thus for enablinglow voltage silicon power MOSFETs, the design principle may serve as a base for the architecture of wire silicon technology to be pushed to its theoretical limits. bondless SiC power modules of the future. The BGA MOSFET from Fairchild Semiconductor [59,60], In addition to the above power modules it is important to mention a few commercial MOSFET the FlipFET, CopperStrap, and DirectFET [61] from International Rectifier are good examples. Most modulesof these based approaches on wire bondlesswere developed technology. to address Although the theyhigh wereparasitic originally source designedinductance for and low high voltage siliconpackage power thermal MOSFETs, resistance the design associated principle with maythe st serveandard as wire a base bonded for the SO-8 architecture MOSFET ofpackage. wire bondless Of SiC powerthese, modulesthe most ofbenefits the future. were Theobserved BGA for MOSFET the completely from Fairchild wire bondless Semiconductor and double-side [59,60], thecooled FlipFET, CopperStrap,DirectFET, andwhich DirectFET was reported [61 ]to from improve International these parameters Rectifier by more are than good 10×. examples. Most of these approachesAnother were developedinteresting low to address power silicon the high module parasitic was sourcethe DrMOS inductance from Infineon. and high In this package module, thermal resistancethe gate associated drive circuit with was the integrated standard within wire the bonded power module SO-8 MOSFET itself. This package. resulted in Of extremely these, thelow most benefitslosses were and observed high efficiencies, for the completely resulting in wire an increa bondlessse in andthe allowable double-side switching cooled frequency. DirectFET, Not which to was mention, all this was possible at a much higher power density as a result of a highly integrated reported to improve these parameters by more than 10×. Another interesting low power silicon module was the DrMOS from Infineon. In this module, the gate drive circuit was integrated within the power module itself. This resulted in extremely low losses and high efficiencies, resulting in an increase in the allowable switching frequency. Not to mention, all this was possible at a much higher power density as a result of a highly integrated Energies 2017, 10, 341 18 of 30 assembly. Perhaps some of the gate-driver-in-module approaches for higher power modules bear testimony to the direct adoption of the DrMOS design philosophy. Press pack modules are among the more popular wire bondless solutions available in the market today. This solution employs mechanical pressure contacts to bond to power devices [62,63]. Although the target application for this is typically in the MW power range, the benefits of using this design translate directly across all power ranges. This class of modules does away with unreliable metallurgical joints like wire bonds and solder, that are prone to breaking under thermo-mechanical stresses. This type of module also has integrated short circuit protection, and is most commonly used for parallel connections between high power devices. It is not, however, an integrated power module and the gate signals must be applied externally. Another keen insight into the packaging design problem is presented in [64]. Material interfaces are the Achilles’ heel in power modules. The CTE mismatch between the various components in a module lead to the cracking of die attach layers and the lifting of wire bonds from the bond pads. Attachment surfaces with comparatively larger surface areas are more prone to failure by delamination. In light of these observations, the article cites various efforts aimed at “un-packaging” where a module is stripped of unnecessary material interfaces and components in a bid to eliminate the failure modes associated with the corresponding constituents. This would directly manifest itself as an increase in reliability and module lifetime. This approach sounds ideal and gives the sense of approaching virtually monolithic electronics modules. Concepts involving embedded systems with power die, passives, and interconnections within a single interposer block follow this approach. It is also possible, if desired, to integrate thermal management within the interposer, to compensate for the comparatively lower thermal conductivities of most existing interposer materials. Is this, however, the answer to all problems? This approach sounds ideal and theoretically solves most issues pertaining to reliability and lifetime. The cost and complexity of building such a module may be prohibitive. Integrating different components together also makes serviceability a challenge. Any kind of rework is difficult to do and may prove to be too expensive to be practical. Therefore, caution must be exercised to maintain a balance between extending the life of a module while keeping an eye on seamless serviceability in case an untimely and unforeseen failure arises. Research in SiC power modules has redefined our conception of the performance limits of a power electronics module. Researchers continue to demonstrate prototypes capable of functioning at switching frequencies in the MHz range. SiC modules targeted toward high temperature, on the other hand, have been demonstrated to operate at temperatures above the physical limits of silicon semiconductor technology. These efforts are truly remarkable and herald in a new paradigm in the design and performance of power electronics. However, before these novel technologies are incorporated as part of systems that have a direct impact on our lives, some questions need to be answered with absolute certainty. Let us consider the case of the high frequency SiC modules first. The information on the reliability analysis of these modules is scarce. The applications benefiting from an increased power density (as a consequence of an increased switching frequency) also require a high degree of reliability. Data centers, solar inverters for the grid, vehicular electronics—a failure to quantify reliability of these systems will have a significant impact on human life and property. It is understood that academic publications and prototypes are targeted toward demonstrating key enabling technologies. However, system reliability must be demonstrated at some level to make a technology transition possible. As devices are switched at higher frequencies, EMI analysis is imperative. Any failures that may have occurred due to uncontrolled EMI emission must also be reported and studied. Best practices from the printed circuit board (PCB) design world may be utilized to design power modules meeting rigorous EMI specifications. System level reliability analysis is also important for modules targeted to operate at high temperatures as well. In many studies focused on high temperature SiC modules, gate driver and Energies 2017, 10, 341 19 of 30 control circuit boards are excluded from the elevated temperature ambient. It is well appreciated that most gate driver ICs and passives that are currently commercially available are rated for maximum operating temperatures around 125 ◦C. This limits researchers from demonstrating system level reliability at elevated temperatures. If the high temperature performance of the associated components around the SiC power devices are not improved, it will be difficult to justify the added costs of choosing SiC over Si IGBTs. Today commercially available Si IGBTs are rated for temperatures up to 175 ◦C. Hence from a strictly “high temperature” viewpoint, there needs to be some fundamental system level technological research to be able to conclusively qualify SiC as superior. Having said that, the power density improvement offered by SiC cannot be ignored. Even if a SiC power module operates at an identical temperature level as that of a Si power module, it may theoretically operate at a much higher switching frequency and induce little or no increase in the associated switching losses. However, whether the performance gains that accompany this power density enhancement can justify the cost of using SiC technology is uncertain. There are also not many studies that relate the variation of switching losses with a variation in the junction temperature of the device. There are a few studies which suggest that it may not be possible to switch MOSFETs as fast as one might think. STMicroelectronics published an application note showing marked increase in the gate resistance with temperature [6]. This will inhibit fast switching and may even result in higher losses in the drive circuits. Some of the above studies included in the review illustrate the advantages of using SiC technology beyond the shadow of a doubt. However, a degree of skepticism must be maintained to ascertain whether a claimed improvement in system performance would be absolutely impossible without SiC power devices. These devices are part of a larger and more complex system. While a piece-wise validation is an important first step, the need for a high level view of reliability encompassing the system as a whole cannot be disregarded.

6. Present Wire Bondless Integration Efforts in Power Electronics The realm of wire bondless SiC power MOSFET packaging, where it is capable of a much greater impact, is fairly uncharted. In 2012, researchers at the University of Arkansas developed a 6.5 kV wire bondless power module [65]. This was followed by a similar demonstration of an LTCC-based high temperature, double-sided cooled power module in 2013 [66]. In the 2012 version, solder was used for bonding both sides of the die to patterned DBC substrates on either side. An underfill material was used for relieving thermo-mechanical stresses. Additionally a benzocyclobutene (BCB) coating was used on the top and bottom layers to aid electrical isolation. However, after 260 thermal cycles between −40 ◦C and 200 ◦C, the solder layer was found to delaminate from the edges (Figure 13a). The 2013 version included a rigid LTCC fixture for mechanical support instead of the underfill material (Figure 13b). Also, sintered silver was used as the die interconnection material instead of solder owing to its superior thermo-mechanical properties. This change enabled the new version to operate at higher ambient temperatures. A double-sided cooled approach helped these novel structures maintain satisfactory operation up to 150 ◦C. Additional LTCC 3D wire bondless power modules are being pursued at the University of Arkansas. One of the main reasons for using LTCC as an interposer material is the excellent CTE match it offers to SiC [67]. The 9K7 material system from Dupont has a near perfect CTE match with SiC. Also, LTCC offers very good electrical isolation and can operate at high temperatures [67]. This is supplemented by the fact that LTCC substrates have been the state-of-the-art for several RF and microwave engineering applications in the past, due to low dielectric losses at high frequencies. They have also been used in actuators and sensors. The LTCC material system has exhibited good reliability in these applications. All these factors work in favor of LTCC as the choice of material for an interposer in 3D SiC modules. Energies 2017, 10, 341 20 of 30

Energies 2017, 10, 341 20 of 30

(a) (b)

Figure 13 Recent wire bondless power module packaging efforts from the University of Arkansas Figure 13. Recentshowing: wire (a) a bondlessscanning acoustic power microscope module (SAM) packaging image of efforts solder fromdelamination the University in the 2012 of Arkansas showing: (a)module, a scanning and (b) acoustic a schematic microscope showing the design (SAM) approach. image of solder delamination in the 2012 module, (a) (b) and (b) a schematic showing the design approach. The 2016 3D stacked module by Dutta and Ang [68] featured two LTCC-based standalone Figureparallel 13 Recent MOSFET wire modules bondless that powerwere interconnected module packaging to form effortsa half bridge. from the Each University standalone of module Arkansas showing: (a) a scanning acoustic microscope (SAM) image of solder delamination in the 2012 The 2016served 3D stackedas a switching module position. by DuttaThe half and bridge Ang connection [68] featured was facilitated two LTCC-basedby using spring standaloneloaded parallel module,metallic and connectors, (b) a schematic housed showing in an LTCC the designfixture. approach.Spring loaded interconnects have been previously MOSFET modulesused in electronics that were for high interconnected speed I/O with some to form success. a halfThe classical bridge. press Each pack standalonefor IGBTs has also module served as a switchingThedemonstrated 2016 position. 3D stacked the The viability halfmodule of bridge pressure by Dutta connection contacts and as aAng highly was [68] reliable facilitated featured interconnect bytwo using approach.LTCC-based spring It will loadedstandalone be metallic connectors,parallel MOSFETinteresting housed inmodulesto observe an LTCC thatthe test were fixture. results interconnected for Spring high speed loaded to and form high interconnects a halfpower bridge. SiC MOSFETs. haveEach standalone been The initial previously module used simulation results of the switching characteristics show promise. in electronicsserved as a for Theswitching high second speed LTCCposition. I/Obased The witheffort half came some bridge from success. Zhuconnection et al. The[69]. was An classical LTCCfacilitated interposer press by pack usingwas used forspring as IGBTs a loaded has also demonstratedmetallic fixtureconnectors, the for viability fuzz housed button of interconnects. pressurein an LTCCcontacts There fixture. have asSpring been a highlyseveral loaded studies reliable interconnect corroborating interconnects have the benefits been approach. previously of It will be interestingused in electronicsusing to fuzz observe button for highthe interconnects testspeed results I/O for with RF for applications some high su speedccess. [70–73]. The and Figure classical high 14a power shows press apack SiC schematic MOSFETs.for IGBTs of the has The also initial demonstratedcross section the viability of the fuzz of button pressure press contacts pack module as a. Anotherhighly reliableinteresting interconnect feature of this approach. module was It will be simulation results of the switching characteristics show promise. interestingthe presenceto observe of an the LTCC test microchannel results for heat high sink. speed This enabled and high the heat power dissipation SiC MOSFETs.of the MOSFETs The initial The secondto be LTCCcontrolled based adequately effort without came fromadding Zhu sign etificant al. [volume69]. An to LTCCthe module. interposer Conductive was traces used as a fixture simulation results of the switching characteristics show promise. for fuzz buttonwere interconnects. printed on the microchannel There have sink been for carrying several current. studies Figure corroborating 14b shows a photograph the benefits of the of using fuzz TheLTCC-based second LTCC heat sink.based The effort fuzz buttonscame fromwere investigZhu etated al. in[69]. software An LTCC to show interposer that the parasitics was used as a buttonfixture interconnects forwere fuzz contained button for to RF interconnects.a minimum. applications Also, There the [70 thermal– 73have]. Figure managementbeen several 14a was shows studies tested a wi schematiccorroboratingth a dummy of heat thethe load, crossbenefits section of of the fuzzusing button fuzzand buttonperformed press packinterconnects to expectation. module. for The Another RF results applications had interesting good [70–73].correlation feature Figure with of the this14a maximum shows module atemperature schematic was the presenceof the of an LTCCcross microchannelsectionpredicted of the by finitefuzz heat element button sink. analysis. press This enabledpack module the. heat Another dissipation interesting of thefeature MOSFETs of this module to be controlled was adequatelythe presence without of an adding LTCC microchannel significant volumeheat sink. to Th theis enabled module. theConductive heat dissipation traces of the were MOSFETs printed on the microchannelto be controlled sink adequately for carrying without current. adding Figure significant 14b shows volume a photographto the module. of Conductive the LTCC-based traces heat sink.were The printed fuzz buttons on the microchannel were investigated sink for in carrying software current. to show Figure that 14b the shows parasitics a photograph were contained of the to LTCC-based heat sink. The fuzz buttons were investigated in software to show that the parasitics a minimum. Also, the thermal management was tested with a dummy heat load, and performed to were contained to a minimum. Also, the thermal management was tested with a dummy heat load, expectation.and performed The results to expectation. had good The correlation results had with (gooda) the correlation maximum with temperature the maximum predicted temperature by finite elementpredicted analysis. by finite element analysis.

(b)

(a)

(b)

Figure 14. 3D stacked power module with a fuzz button embedded interposer by Zhu et al. [69]. (a) A schematic showing the cross section of the module; and (b) photographs showing the top and bottom views of the low temperature co-ﬁred ceramic (LTCC) microchannel heat sink. Energies 2017, 10, 341 21 of 30

3D packaging of SiC modules has been embraced by APEI Inc. In some of their more recent efforts they used a stacked gate driver board atop the power stage for low inductance interconnections. However, the parasitic inductance of the wire bonds is still the limiting factor in switching performance. This fact is touched on in a 2015 publication by APEI Inc., where they demonstrated the concept of a wire bondless power module for the very first time [74]. However, a prototype based on the design has not been released yet. The wire bondless power module used the PowerStep connector in favor of wire bonded interconnections. The connector was made of etched copper with a gold finish. Sintered silver, solder, and electrically conductive adhesives were described as possible attachment methods. The paper presented a detailed finite element analysis of the favorable effects of adopting a wire bondless approach. Aside from the obvious reduction in loop parasitics, it was found that the thermo-mechanical stresses of the PowerStep connector were much lower than a wire bond at a junction temperature of 200 ◦C. This is an important feature considering the fact that one of the major benefits of SiC power devices is their ability to operate efficiently at elevated temperatures. Also, the Joule heating associated with the PowerStep connector was found to be much lower as compared with a wire bond at current loads of 100 A and above. The module was also tailored for a switching frequency of 500 kHz, enabled by the reduction in parasitics. The modules discussed thus far in this section show great promise to offset the drawbacks associated with wire bonding. The approaches like spring pins and fuzz buttons have already been proven to be beneficial in high speed electronic circuits in the past. With careful design considerations, these benefits should translate to high power modules as well. The success of press pack modules bears testimony to the success of this design philosophy. However, it is important to note that the described approaches are power modules. They must still be routed to a gate driver board to operate in the field. This implies that the parasitic gate inductance of the module is not the sole force to reckon with. The connection to and from the gate driver board, and the board parasitics will also play a key role in determining the behavior of the switching transients and associated EMI behavior. This fact has been highlighted in some of the integrated power modules that have been presented in this paper. Implementing the gate driver “on board” or “in module” was the driving factor behind their success.

7. Future Directions The future of SiC power modules could be “the best of both worlds”—by implementing wire bondless technology in an integrated power module. Efforts are underway at the National Science Foundation (NSF) Center for Power Optimization of Electro-Thermal Systems (POETS) Engineering Research Center (ERC) to deliver the SiC power module of the future based on this concept. This section will summarize some of the integrated SiC module design concepts proposed by the POETS ERC this year. In 2016, the concept for an LTCC-based integrated wire bondless power module (IWPM) was put forth [75]. A simple schematic showing the cross section of the proposed module is shown in Figure 15. The interposer was envisioned as a shallow container made of Dupont 9K7 LTCC material. The material of the interposer was chosen for reasons stated earlier. Power devices were mounted on the bottom side of the interposer, such that the gate and source pads of the SiC power devices contacted the interposer surface. The top side contacts of commercially available SiC power devices in bare die form are made of aluminum, and this was proposed to be converted to a Ni/Ag ﬁnish by using an electro-less plating process. The choice of material for the ﬂip-chip die attach material was sintered silver. The bottom side of the power devices were proposed to be connected by an electrically conductive metal foil bonded by sintered silver. The metal foil would, in turn, be bonded to a designated pad on the interposer to complete the current path. Energies 2017, 10, 341 22 of 30

Energies 2017, 10, 341 22 of 30

Figure 15. The LTCC based integrated wire bondless power module by Seal et al. [74]. Figure 15. The LTCC based integrated wire bondless power module by Seal et al. [75]. The top side of the interposer would house the gate drive circuits for the power devices on the bottom tier. The connection from the output of the gate driver chip to the gate pad of the MOSFET The top side of the interposer would house the gate drive circuits for the power devices on the bottomwas tier. achieved The connection by a through from LTCC the outputvia, filled of thecomp gateletely driver with conductive chip to the paste gate and pad cured. of the The MOSFET module showedFigure very 15. low The LTCCthermo-mechanical based integrated strewiresses bondless at a nominalpower module junction by Seal temperature et al. [74]. 80 °C. was achieved by a through LTCC via, ﬁlled completely with conductive paste and cured. The module A follow up study in 2016 by Seal et al. [76] demonstrated a single integrated switch module The top side of the interposer would house the gate drive circuits for the power devices◦ on the showedbased very on low the thermo-mechanical design principle of the stresses integrated at a wire nominal bondless junction power temperaturemodule (IWPM). 80 FigureC. 16a bottom tier. The connection from the output of the gate driver chip to the gate pad of the MOSFET A follow up study in 2016 by Seal et al. [76] demonstrated a single integrated switch module showswas aachieved rendering by aof through the proposed LTCC via,module filled with comp theletely encapsulation with conductive removed, paste andshowing cured. the The gate based ondriver,module the isolator, design showed and principle very passive low thermo-mechanical ofdevices the integrated on the top stre la wiressesyer. atThe bondless a nominal bare die junction powerSiC MOSFET temperature module was (IWPM).on 80 the°C. bottom Figure 16a shows alayer, rendering asA with follow ofthe theup IWPM. study proposed Simulationsin 2016 moduleby Seal of a et double with al. [76] the puls demonstrated encapsulatione test of the a modulesingle removed, integrated at a high showing slewswitch rate module theshowed gate driver, isolator,a anddrasticbased passive reductionon the design devices the levelsprinciple on of the ringingof topthe integrated layer.and overshoot The wire bare bondlessassociated die SiCpower with MOSFET modulethe module (IWPM). was as compared on Figure the bottom16a with layer, a conventionalshows a rendering wire bonded of the moduleproposed (Figure module 16b,c). with the encapsulation removed, showing the gate as with the IWPM. Simulations of a double pulse test of the module at a high slew rate showed a driver, isolator, and passive devices on the top layer. The bare die SiC MOSFET was on the bottom drastic reductionlayer, as with the the levels IWPM. of Simulations ringing and of a overshoot double pulse associated test of the module with theat a high module slew rate as comparedshowed with a conventionala drastic wire reduction bonded the module levels of (Figureringing and 16 overshootb,c). associated with the module as compared with a conventional wire bonded module (Figure 16b,c).

(a) (b)

(c)

Figure 16. Flip-chip bonded integrated switch module, 2016, showing: (a) a rendering of the top side of the power module with the gate drive circuit; (cb)) the “turn-on” waveforms for a comparable wire

Figure 16. Flip-chip bonded integrated switch module, 2016, showing: (a) a rendering of the top side Figure 16.ofFlip-chip the power bondedmodule with integrated the gate drive switch circuit; module, (b) the “turn-on” 2016, showing: waveforms (a for) a a rendering comparable ofwire the top side of the power module with the gate drive circuit; (b) the “turn-on” waveforms for a comparable wire bonded module; and (c) the virtually ripple free waveforms obtained by using a ﬂip-chip wire-bondless approach. Energies 2017, 10, 341 23 of 30

Energies 2017, 10, 341 23 of 30

Underbonded a power module; dissipation and (c) theof virtually 100 W, ripple the proposedfree waveforms module obtained reached by using amaximum a flip-chip junction ◦ ◦ temperaturewire-bondless of 140 approach.C, thus meeting the 150 C maximum rating of the device itself. Under this thermal load, the mechanical stress on the flip-chip contacts were found to be less than half that of a conventionalUnder wire a power bonded dissipation MOSFET assembly.of 100 W, However,the proposed the stressmodule was reached found a tomaximum be concentrated junction at the edgetemperature of the flip chip of 140 contact. °C, thus This meeting would the make 150the °C diemaximum attach layerrating susceptible of the device to itself. cracking Under at thethis edges thermal load, the mechanical stress on the flip-chip contacts were found to be less than half that of a within a few hundred thermal cycles. Moreover, using sintered silver for flip-chip bonding on an LTCC conventional wire bonded MOSFET assembly. However, the stress was found to be concentrated at interposerthe edge may of introducethe flip chip considerable contact. This process would make cost andthe die complexity. attach layer Also, susceptible the electrical to cracking conductivity at the of sinterededges thick within film a conductorsfew hundred on thermal LTCC cycles. is not Moreover as high as, using copper. sintered For high silver current for flip-chip modules, bonding this on was an importantan LTCC issue interposer to consider may because introduce it mayconsiderable introduce process undesirable cost and voltage complexity. drops Also, and the cause electrical unwanted hot spotsconductivity in the interposer. of sintered Tothick address film conductors these concerns, on LTCC the is conceptnot as high of theas copper. flip-chip For MOSFET high current package was developed.modules, this was an important issue to consider because it may introduce undesirable voltage Adrops fourth and 3Dcause SiC unwanted module hot concept spots in was the proposedinterposer. byTo address researchers these atconcerns, the University the concept of of Arkansas the in 2016flip-chip [77]. TheMOSFET first step package in building was developed. the module was to reconfigure a commercially available bare die A fourth 3D SiC module concept was proposed by researchers at the University of Arkansas in MOSFET into a flip-chip capable package. A chip-scale MOSFET was developed, a schematic of the 2016 [77]. The first step in building the module was to reconfigure a commercially available bare die part is shown in Figure 17a. A commercially available bare die MOSFET was attached to a metallic MOSFET into a flip-chip capable package. A chip-scale MOSFET was developed, a schematic of the drainpart connector. is shown The in Figure material 17a. of A thecommercially drain connector available was bare chosen die MOSFET to be copper was attached for cost to considerations, a metallic but adrain composite connector. material The material like CuMo of the or drain AlSiC connector with a was better chosen CTE to match be copper to SiC for may cost considerations, be used for greater reliability.but a composite The assembly material was like solder CuMo masked or AlSiC and with solder a better ball CTE bumped match to to SiC produce may be the used flip-chip for greater capable chipreliability. scale package. The assembly Figure 17 wasb shows solder the masked schematic and ofsolder a power ball modulebumped incorporatingto produce the these flip-chip flip-chip SiC MOSFETs.capable chip Thescale philosophy package. Figure behind 17b shows this approach the schematic was of similar a power to module the IWPM, incorporating but this these method employedflip-chip several SiC MOSFETs. known-good The philosophy design practices behind to this improve approach the was manufacturability, similar to the IWPM, repeatability, but this and serviceabilitymethod employed of the integrated several powerknown-good module. design practices to improve the manufacturability, repeatability, and serviceability of the integrated power module.

(a)

(b)

Figure 17. (a) A schematic showing the proposed chip scale MOSFET; and (b) a schematic showing the module implementation of the chip-scale MOSFET package. Energies 2017, 10, 341 24 of 30 Energies 2017, 10, 341 24 of 30 Figure 17. (a) A schematic showing the proposed chip scale MOSFET; and (b) a schematic showing the module implementation of the chip-scale MOSFET package. The drain connector has the dual purpose of serving as a low thermal resistance path to the heat sink. AnotherThe drain noticeable connector feature has the of dual this purpose approach of was servin theg absenceas a low thermal of a power resistance substrate. path In to a the way, heat this approachsink. Another is similar noticeable in principle feature to of attaching this approach the die was directly the absence on the of baseplate.a power substrate. This has In the a way, benefit this of decreasingapproach both is similar the thermal in principle path to and attaching the number the die of directly interfaces on inthe a baseplate. power module. This has the benefit of decreasingA solder both ball the array thermal was path used and in the the number module of interfaces instead ofin a power flat soldered/sintered module. interface. As mentionedA solder earlier, ball array a flat was bond used line in showed the module an accumulation instead of a of flat thermo-mechanical soldered/sintered stressinterface. along As the edges—thusmentioned making earlier, thea flat bond bond susceptible line showed to premature an accumulation cracking of under thermo-mechanical thermal stress. stress Solder along balls the have beenedges—thus used in BGA making interconnection the bond susceptible over the past to premat severalure decades cracking as under a highly thermal dense stress. and reliable Solder formballs of interconnection.have been used This in BGA packaging interconnection technique over exploited the past the several best characteristics decades as a highly that BGA dense technology and reliable had to offer.form Oneof interconnection. of the concerns This with packaging using a flat techni bondque line exploited was that the the best die maycharacteristics be marginally that skewedBGA technology had to offer. One of the concerns with using a flat bond line was that the die may be after the reflow/sintering process. This slant would facilitate cracking from the narrow edge under marginally skewed after the reflow/sintering process. This slant would facilitate cracking from the repeated thermal stress. Solder balls have a tendency to reflow and self-planarize [78]. They also narrow edge under repeated thermal stress. Solder balls have a tendency to reflow and have the property of self-aligning due to surface tension. Even if the end user does not place the part self-planarize [78]. They also have the property of self-aligning due to surface tension. Even if the perfectly accurately during flip-chip bonding, the surface tension of molten solder has a tendency to end user does not place the part perfectly accurately during flip-chip bonding, the surface tension of “pull”molten the solder part into has the a tendency right location to “pull” [79 ].the part into the right location [79]. BGAsBGAs also also have have known known good good reliability reliability asas discusseddiscussed in an earlier section. section. A A study study by by Lin Lin and and LuoLuo showed showed that that SnAg SnAg flip flip chip chip solder solder bumps bumps survivedsurvived more than 3000 3000 thermal thermal cycles, cycles, even even when when mountedmounted on on inexpensive inexpensive FR4 FR4 substrates substrates [ 80[80].]. SomeSome studies also show showeded a a strong strong correlation correlation between between interconnectinterconnect parasitic parasitic inductance inductance and and EMI EMI emissionsemissions [[81,82].81,82]. BGA BGA technology technology has has been been known known for for havinghaving much much less less parasitic parasitic inductance inductance as compared as compar withed with wire wire bonds, bonds, and isand thus is expected thus expected to produce to lessproduce EMI. This less was EMI. expected This was to expected be a highly to be desirable a highly featuredesirable in feature a power in modulea power intendedmodule intended to operate to at highoperate voltage/current at high voltage/current slew rates. slew rates. FutureFuture work work on on this this module module will will include include the the assembly assembly ofof thethe chip-scalechip-scale packaged MOSFETs on on a PCBa PCB with with an integrated an integrated gate gate driver driver and and passive passive circuitry circuitry (Figure (Figure 18 18).). The The circuitcircuit topologytopology is that of of a halfa half bridge bridge employing employing two two 1200 1200 V V MOSFETs MOSFETs from from ROHM ROHMSemiconductor. Semiconductor. The The top top side side of of the the PCB PCB houseshouses the the gate gate driver driver chip chip and and power power supplies, supplies, alongalong with the other other passives passives necessary necessary for for the the gate gate drivedrive to function.to function.

(a) (b)

Figure 18. The integrated wire bondless half bridge incorporating chip-scale packaged MOSFETs Figure 18. The integrated wire bondless half bridge incorporating chip-scale packaged MOSFETs showing a rendering of (a) the top view of the printed circuit board (PCB) with the gate driver, showing a rendering of (a) the top view of the printed circuit board (PCB) with the gate driver, passives, passives, and power supplies; and (b) the bottom view showing the MOSFETs and decoupling and power supplies; and (b) the bottom view showing the MOSFETs and decoupling capacitors. capacitors.

A few capacitors and inductors for inductively isolating the heat sink are also mounted on the top side. This will help in mitigating EMI by suppressing any injected current spikes that may propagate through the heat sink because of the parasitic capacitance between the drain connector and the heat Energies 2017, 10, 341 25 of 30 sink [83]. The bottom side of the PCB contains the two chip-scale MOSFETs serving as the two switch positions of the half bridge. EMI suppression capacitors are also mounted in the bottom side. Mounting the DC link capacitor close to the MOSFETs in this fashion proved to be the most effective in EMI spike suppression according to some studies using the GaN material system [84].

8. Conclusions SiC devices are fast becoming the semiconductor device of choice in most advanced applications. The demand will only continue to increase as the world becomes more electrified. Having access to power converters that fit within the palm of our hands may give rise to innovations that are yet to be imagined. The enormous potential that SiC offers as a semiconductor material has not been explored completely. We tend to use performance limiting packaging technologies and restrain the full benefits of SiC technology. Researchers had already encountered the glass ceiling of package performance with silicon devices in the past. Many examples in this paper bear testimony to the adoption of unconventional silicon power packaging solutions in a bid to extricate that much more in terms of thermal and electrical performance. SiC packaging research needs to progress along the same line. The bottlenecks in state-of-the-art SiC power modules needs to be identified. Investigations need to be conducted to ascertain the part/parts of the package giving rise to these performance limits. This must be followed by innovative redesign in the appropriate direction to push SiC modules further. Interconnect technology is one of the major limiting factors plaguing SiC modules of the present. Wire bonding offers too much parasitic inductance to be able to run SiC power devices at the frequencies it is capable of. Ringing and overshoots due to parasitic loop inductance are only a part of the problem—EMI emissions are a worse consequence which may lead to a catastrophic failure due to a false switching event. Many power electronics research groups around the globe are realizing this, and a there has been a noticeable push in the direction of low inductance SiC package designs in the recent past. Efforts at the University of Arkansas are focused on providing high-performance alternatives to wire bonding. Approaches involving spring pin interconnects, fixtured fuzz buttons, and solder ball interconnects have proven to be winning choices in high speed, low power electronics applications in the past. The endeavor is to re-engineer these methods to render them applicable to SiC power modules at all power levels. Some of the recent efforts in this direction have been described, and these will help lay the bedrock of a better understanding of these interconnect technologies as it applies to SiC packaging. Evaluating and weighing these approaches against one another will help establish new standards for packaging technologies suited to the needs of a particular application. Wire bondless integration will also introduce possibilities of double-sided cooling and 3D integration, once again depending on what the end application would benefit the most from. Compact integration coupled with faster switching frequencies will enable an unprecedented power density. In a rapidly growing electronics market, less is more. Smaller and lighter power electronics may completely change the way we perceive the world.

Acknowledgments: This work was supported by the National Science Foundation Engineering Research Center for Power Optimization of Electro Thermal Systems (POETS) with cooperative agreement EEC-1449548. Author Contributions: Sayan Seal conducted the review and assimilated and organized data into defined sections in the paper. He served as the primary author of this work. Homer Alan Mantooth defined the content and framework of the publication, He also advised the first author in a comprehensive and iterative editing process. Conflicts of Interest: The authors declare no conflict of interest.

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