FD-SOI Technology
Bich-Yen Nguyen Soitec Agenda
1 FD-SOI technology overview
2 Markets, foundries offers & ecosystems
3 FD-SOI material & roadmap
4 Summary
10/10/20172 SOITEC Confidential FD-SOI technology Challenge of Traditional Planar Bulk Transistor Scaling
Source: IBM, T.C. Chen, ISSCC 2006 • Increased standby power dissipation • Amplified V variability th new transistor architectures and ⇒Impact Yield materials are needed ⇒Limit Vdd scaling
10/10/20173 SOITEC Confidential FD-SOI technology Continue Moore Law with New Materials & Device Architectures 2003 2005 2007 2009 2011 2012
Hartmann, GSA12 90nm 45 nm 22nm
65nm 32nm
Strained Silicon
Introduction of New High-K / Metal Gate Materials
Introduction of New Fully Depleted Device Devices Architecture 10/10/20174 SOITEC Confidential FD-SOI technology Leakage Power is still a Major Issue Despite the Use of Hi-K Dielectric
High-K/Metal Gate Stack
Source: IBS
SiON/Poly Gate Stack
Technology node Leakage power is still tremendously growing after insertion of the High- K/MG gate stack at 28nm node as demands for more performance and functionality
10/10/20175 SOITEC Confidential FD-SOI technology New Device Architecture: Planar FDSOI or Multi-Gate Transistor
Minimum Design Max Disruption scalability G G D SD S Buried OX S G D
Bulk Si Bulk Si Buried oxide
Conventional Planar Planar Single-or double Multiple-Gate, FinFET or Bulk Transistor Gate FDSOI Nanowire Transistor FDSOI : Fully Depleted Silicon-on Insulator
Thin channel (Fully Depleted) with multi gates for better gate or short channel (SCE) control Better gate control ⇒ better transistors scaling
10/10/20176 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER
• Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm ß Gate bias ß Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design UTBB: Ultra-Thin Body and BOX
10/10/20177 SOITEC Confidential FD-SOI technology FDSOI Device Physics
Body factor: n = …1.05… in FDSOI; …1.5… in Bulk FDSOI Vg G Bulk/PDSOI Vg G Coxf S D Cox F S D Csi s1 Oxide F F Silicon Cdepl s Coxb s2
W 1 2 Linear current: I = µ C ()V − V V − n V D ox L G TH D 2 D 1 W 2 Saturation current: I = µ C (()V − V ) Dsat 2n ox L G TH kT Sub-threshold slope: S = n ln(10 ) q µ gm = 2 Cox W L Gain (strong inversion): VA VA ID n ID
10/10/20178 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER
• Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm ß Gate bias ß Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
10/10/20179 SOITEC Confidential FD-SOI technology FD-SOI Transistor Level Benefits
BULK FD-SOI Thin and excellent Gate uniformity SOI defined Gate channel
Source Drain Source Top Si Drain BOX 2nd gate through ultra thin BOX Bulk wafer FD-SOI base wafer
Vth and SCE defined by complex and heavily Vertical transistor layout determined by FD-SOI channel and halo doping techniques engineered substrate and undoped channel Large Vt mismatch due to random dopant Significant improved Vt mismatch due to fluctuation => limit Vdd scaling minimize random dopant fluctuation => enable Vd scaling down to 0.4V or lower Strong sensitivity to short channel effect Excellent SCE Large junction capacitance (Cj), GIDL and Didode leakage Minimum Cj, GIDL & diode leakages Limited well bias capability Extensive back bias capability
10/10/201710 SOITEC Confidential FD-SOI technology FD-SOI superior SER enables high reliability required applications FD-SOI = 20x SER CPU#1 Memory improvement vs. bulk CPU#2 28nm 28nm FD-SOI in FT/Mb in CPU#1
Memory
SER CPU#2
“Attractive SEU resistance due to very low CPU#1 Neutron- charge collection volumes in FD-SOI” Memory ST Vendor A ST Vendor A ST ST Michael L. Alles Vanderbilt University, S3S conference, 2015 CPU#2 65nm 45nm 45nm 28nm 28nm 28nm Bulk Bulk Bulk Bulk Bulk FD-SOI Mobileye using STM FD-SOI 28nm technology for their 4th gen chipset
ST, P. Magarshack, Shanghai FDSOI forum, 2015
10/10/201711 SOITEC Confidential FD-SOI technology Source: Automotive Product Group (APG) presentation,, Marco Monti FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER
• Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm ß Gate bias ß Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design UTBB: Ultra-Thin Body and BOX
10/10/201712 SOITEC Confidential FD-SOI technology FDSOI Structure by IBM- VLSI 2009
Insitu doped SiGe S/D: ⇒Lower S/D resistance ⇒Reduces parasitic capacitance
B - SiGe
Lg= 25nm Tsi= 6nm Tinv=1.6nm Ioff= 3nmA/um Ion-N=570um/um Ion-P=550uA/um Vdd=0.9v
13 BY Nguyen, Soitec Apr. 22, 2011 IBM: 28LP Bulk vs. FDSOI 20LP Parameter 28LP Bulk IBM et al. (*) ETSOI IBM et al. (**) Lg 30nm 22nm VDD 1V 1V nFET pFET nFET pFET Ion @ 660µA/µm 380µA/µm 760µA/µm 590µA/µm Ioff=300pA/um Ion @ 740µA/µm 420µA/µm 920µA/µm 880µA/µm Ioff = 1nA/um DIBL 120mV/V 130mV/V 85 mV/V 90 mV/V AVt 2mV.µm 1.25mV.µm VDD 1.1V Ion @ 920µA/um 525nA/µm 1100µA/µm 1050µA/µm Ioff=1nA/um, (*): IBM Alliance 28LP technology as reported at IEDM’09, F Arnaud et al. (**): ETSOI technology for 22/20LP from IBM Research, as reported at FDSOI workshop dec 2010.
10/10/201714 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER improvement
• Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing
Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm ß Gate bias ß Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
10/10/201715 SOITEC Confidential FD-SOI technology SOI value: part of device integrated by substrate engineering
Optimized SOI wafers provide excellent silicon geometry control To make the best of FD technology
FD-SOI transistor Soitec FD-2D wafer Ultra-Thin Top Silicon Layer SDG Ultra-Thin Buried Oxide Base Silicon
Critical dimension: Enables: Critical dimension: Top Si thickness channel thickness
10/10/201716 SOITEC Confidential FD-SOI technology FDSOI Uniformity: Lowest VT variability m) µ (mV. vt A
±2.6A, 2mm EE- 721 pts F5X inspection Gate Length (nm)
Cheng et. Al. IBM IEDM 2009
Record and reproducible low A VT of 1.25mV. µm @ Lg=25nm (32/28nm GR)
B.Doris et al., FD ‐Workshop at SFO, 2012
10/10/201717 SOITEC Confidential FD-SOI technology Planar Bulk vs FDSOI Vt Variation
V t V ariation
0.03
0.025 Retrograde Bulk
0.02
0.015
sigma Vt (V) Vt sigma FDSOI 0.01
0.005
0 5 15 25 35 45 Lg(nm) FDSOI shows best results S O I Retro Bulk in Uniformvariation Bulk (throughout gate length)
Source: UCB/Soitec , SOI 2009 Conference 50-60% Vt variation improvement by using undoped channel retains with technology scaling
10/10/201718 SOITEC Confidential FD-SOI technology Single Port 4Mb SRAM: No Back Bias
VImproved memory minimum voltage
28nm LP Bulk vs 28nm FDSOI from STMicroelectronics (gate-first HKMG Technology)
10/10/201719 SOITEC Confidential FD-SOI technology 10/10/201720 SOITEC Confidential FD-SOI technology C2 - Confidential FDSOI for RF & Analog Beyond 28nm Bulk
FDSOI key analog differentiations Higher Analog Performance vs Bulk Lower variability than bulk FDSOI Lower Capacitance enabling higher frequency Lower Phase noise Remaining planar On the fly Vt tuning New circuit topology enabler : double gate transistor Analog : VT, Fmax, Gm, Ioff, …. Bulk CMOS Ideal for next generations transceivers and SoC
Vgs
Gain @ Lmin Gain @ Id Variability (Undoped Channel) Fmax > 300Ghz
10/10/201721 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER
• Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm ß Gate bias ß Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
10/10/201722 SOITEC Confidential FD-SOI technology Electrostatic Scaling Rule of FDSOI down to Lg~10nm
5nm
Electrostatic control improved by thinning Tbox and TSi Superior short-channel control maintained with scaling Scalability possible down to Lg~10nm, thanks to UTBB FDSOI
10/10/201723 SOITEC Confidential FD-SOI technology Multi-VT Solution for FD-SOI with Dual Metal Gate/Ground Plane Logic SRAM nMOS pMOS nMOS pMOS HVT 0,8 TiN LVT TaAlN TaAlN TiN LVT RVT HVT SHVT BOX BOX BOX BOX 0,6 N-GP P-GP Metal N-GP P-GP nMOS change 0,4 nMOS pMOS nMOS pMOS GP-N GP-P TiN RVT TaAlN TaAlN SHVT TiN 0,2 GP-N GP-P BOX BOX GP BOX BOX N-GP P-GP N-GP 0 P-GP change GP-P -0,2 GP-N GP-P GP-N
Threshold voltage (V) voltage Threshold -0,4 GP pMOS -0,6 change metal change -0,8 TiN TaAlN/TaN
O. Weber et al., IEDM’10
Multi Vt requirement for SoC can be achieved for FDSOI device using dual WF metal-gate and ground-plane approach without back-bias
10/10/201724 SOITEC Confidential FD-SOI technology Multi-VT Modulation for FDSOI with Back Bias
Leti- VLSI 2010 Q. Liu, ST, VLSI 2010
VT tuning with BOX = 10nm and VBB , GP N and PMOS: VT modulation of ≤200mV for 10nm BOX No degradation of Ion-Ioff trade-off with back-bias up to +/-2V
10/10/201725 SOITEC Confidential FD-SOI technology Body-Bias enabling wider dynamic operating range NXP example (BB level 0)
Source: NXP presentation at SOI Consortium, Santa Clara, April 2017
10/10/201726 SOITEC Confidential FD-SOI technology FD-SOI with Back Bias enables 0.4v Operation for IoT FDSOI 0.08um2 SRAM (80nm CPP)
VBB
Q. Liu, et. al. VLSI Symposium 2011 R. Tsuchiya, et. al. IEDM 2007
• SRAM remains functional down to V DD =0.4V • Clear SNM modulation from back bias • Both Stability and Vt variation improved with RBB • Lower Vdd for logic operation with software controlled Back-bias enables SoC Product with tremendous power saving (>70%) 10/10/201727 SOITEC Confidential FD-SOI technology 22nm FDX Platform Features: ULL, ULP & RF
Source : R. Carter, GlobalFoundries, IEDM 2016
10/10/201728 SOITEC Confidential FD-SOI technology 22nm FDX Platform Features: ULL, ULP & RF
10/10/201729 SOITEC Confidential FD-SOI technology 10/10/2017 SOITEC Confidential FD-SOI technology C2 - Confidential 30 FD-SOI Transistor Advantages
UTBB FDOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER
• Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing
Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm ß Gate bias ß Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
10/10/201731 SOITEC Confidential FD-SOI technology FDSOI Scalability: Boosters Roadmap
28nm FDSOI
22/14nm FDSOI
12/10nm FDSOI
2nd gen RSD + cSiGe
10/10/201732 SOITEC Confidential FD-SOI technology FDSOI Performance Booster: local Ge Condensation for PMOS
10/10/201733 SOITEC Confidential FD-SOI technology Strain SiGeOI by Ge Condensation of SOI
Source: S. Nakaharai, Appl. Phys. Lett. 83, 3516 (2003);
S. Nakaharai et al, MIRAI, APL, V83, no17, 2003
µ (V− V ) IIon = WC v eff G T DSAT ox sat µ + − eff2v sat LV /( G V T )
• Local Ge condensation with various Ge content/strain level has been used to boost hole mobility or P-type MOSFET performance
10/10/201734 SOITEC Confidential FD-SOI technology Performance of PMOS using cSiGe channel formed by Local Ge Condensation
Source: IBM, Cheng et. al, IEDM-2012
35%
• NMOS does not degrade with local Ge condensation process • Compressive SiGe channel PMOS improved by 35% over unstrained Si FDSOI
10/10/201735 SOITEC Confidential FD-SOI technology ARM says 22nm FD-SOI with proper BB optimization outperforms FinFET at pure performance standpoint
Selective back-gate biasing is developed by ARM Using proper BB on 22nm FD-SOI can achieve higher performance/power tradeoff as those of 14 FinFET technology for
Total Power Total 14FinFET 22FD-SOI ARM HP CPU (Cortex- A72)
Performance Source : ARM, SOI Consortium San Jose 2016
10/10/201736 SOITEC Confidential FD-SOI technology FDSOI Performance Booster: Tension Strain Si Channel for NMOS
10/10/201737 SOITEC Confidential FD-SOI technology Strained Si on Insulator (sSOI) for boosting NMOS Performance 75%
27%
Source: IBM, Khakifirooz et. al, VLSI- 2012 10/10/201738 SOITEC Confidential FD-SOI technology 10nm FD-SOI and DC Performance Comparison
Source: Q. Liu et. al, IEDM 2014
10/10/201739 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages
UTBB FDOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER
• Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing
Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm ß Gate bias ß Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
10/10/201740 SOITEC Confidential FD-SOI technology Simplicity of the FDSOI Integration
Shallow Trench isolation 1- Isolation: Si BOX ‒ Shallow Trench Isolation Si substrate ‒ Define the bulk/SOI area (hybrid option) Gate Process ‒ Ground plane implant 2- Gate Stack:
‒ Sac Ox and High-K deposition
‒ Metal gate & poly Si deposition
‒ Gate stack patterning, etch, HfO2 removal SEG of SD region 3- Source/Drain formation
‒ Selective epitaxy growth (insitu doped or undoped with extension & S/D implant
‒ Salicidation Spacer and NiSi for SD contact 4- MOL and BEOL
‒ ILD/Via/Metal Interconnect Backend
10/10/201741 SOITEC Confidential FD-SOI technology 28nm FDSOI Process Migration
Process steps
10/10/201742 SOITEC Confidential FD-SOI technology Global Foundries 22nm FD-SOI Process Flow
38 Masks and 8 metal Levels
10/10/201743 SOITEC Confidential FD-SOI technology 65/45/28nm FDSOI NMOS PMOS • UTBB substrate • Elevated Si EPI S/D N+ Si Epi N+ Si Epi P+ Si Epi P+ Si Epi
Ground Plane Ground Plane
22/14nm FDSOI NMOS PMOS • UTBB substrate • SiGe Channel for PMOS • Insitu doped SiGe and SiC EPI for S/D P-Si(C) P-Si(C) B-SiGe B-SiGe
Ground Plane
10nm FDSOI NMOS PMOS • sSOI substrate • SiGe Channel for PMOS • Insitu doped SiGe & Si(C) EPI for S/D P-Si(C) P-Si(C) B-SiGe B-SiGe
Ground Plane Ground Plane
10/10/2017 FD-SOI: FinFET performance at lower manufacturing cost
10/10/2017 45 SOITEC Confidential FD-SOI technology Agenda
1 FD-SOI technology overview
2 Markets, foundries offers & ecosystems
3 FD-SOI material & roadmap
4 Summary
10/10/201746 SOITEC Confidential FD-SOI technology FD-SOI brings many differentiation in Mobile, IoT, 5G & Automotive markets
Mobility IoT
Best Power/Perf/Cost Perfect fit for wireless & ULP solution for / ULL IoT clients in need of :
Low-mid tier Baseband + AP On-demand processing performance
4G transceiver integration Integrated RF 5G mmWave design Embedded memory
5G & Radars Automotive Ideal technology for Unique advantages in low power/ high reliability (SER) 5G mmWave low power single chip solution with integrated ADAS (<5W) for autonomous driving PA Radar - Mid to long range single chip
<6GHz applications w/ 35- Infotainment 50% die shrink (LTE, Wifi,…) MCU for Body Electronics
FD-SOI global wafers estimate: 2021 (est.): 1-3M wafers/y. Source : Soitec estimates
10/10/201747 SOITEC Confidential FD-SOI technology The FD-SOI Revolution has started in Consumer & Automobile
Consumer: a game changer technology for Automotive : best power efficiency allowing better battery life simpler integration and enhanced reliability
FD-SOI technology unlocks battery-powered FD-SOI - reference technology for ADAS device potential level 3 applications Next generation e-Cockpit solution with full management of car infotainment
FD-SOI based Sony GPS to i.MX based reference cut standard GPS power platform developed by NXP Advanced features - consumption by 5 to 10x for Amazon’s Alexa Level 3 autonomous driving object recognition Now, more than a day FD-SOI is a key enabler of through neural network autonomy with GPS ON the i.MX reference platform for always-on applications 2.5Tops @ only 3W
10/10/201748 SOITEC Confidential FD-SOI technology FD-SOI: Strong traction from foundries
Samsung GlobalFoundries
10/10/201749 SOITEC Confidential FD-SOI technology 28nm FD-SOI cheaper cost per gate & design cost
10/10/2017 50 SOITEC Confidential FD-SOI technology FD-SOI – A mainstream solution with many choices
Performance & density at any cost - for Servers, networking & High-end Mobile
FinFET 7nm
FinFET 10 nm
FinFET 16/14nm
HK, PolySi 28nm
R.Martino - Shanghai FD SOI Forum – Sept 2015 Bulk 90/65/45 nm
10/10/201751 SOITEC Confidential FD-SOI technology FD-SOI – A mainstream solution with many choices
Performance & density at Cost-effective & performance for Low-power applications any cost - for Servers, networking & High-end Mobile FD-SOI 12 nm FinFET 7nm FD-SOI FinFET 18 nm 10 nm eMRAM
FinFET FD-SOI 16/14nm 22 nm eMRAM
HK, FD-SOI PolySi 28 nm 28nm eMRAM
Bulk FD-SOI 90/65/45 65 nm nm
10/10/201752 SOITEC Confidential FD-SOI technology Latest Announcements FD-SOI: ecosystem getting stronger GLOBALFOUNDRIES
GLOBALFOUNDRIES and the Chengdu municipality to invest 100M$ to build a world-class FD-SOI ecosystem including multiple design centers and accelerate adoption of 22 FD-SOI (FDX) in China A rapidly growing FD-SOI ecosystem Increasing 22 FD-SOI capacity: +40% est. in Germany by 2020 Research Substrates Foundries&IDM Fabless & Consumer New 300 mm fab. in China with Technology & OEMs Products expected volume production in 2019 IP Focus on 12 FD-SOI development
& Licensees SAMSUNG Tools & EDA IP & Design Extension of current 28 nm FD-SOI Services platform by incorporating RF and embedded MRAM
18 nm FD-SOI process technology targeted for risk production in 2019
+50 fabless under CEA - LETI development Presented path to 10nm FD-SOI
IP/ EDA Vendors
Active position in promoting FD-SOI
10/10/201753 SOITEC Confidential FD-SOI technology Agenda
1 FD-SOI technology overview
2 Markets, foundries offers & ecosystems
3 FD-SOI material & roadmap
4 Summary
10/10/201754 SOITEC Confidential FD-SOI technology FD-SOI Substrate Maturity
Long collaborative history on FD-SOI
Smart Cut & Research Donor Advanced 28FD foundry 22FD foundry Industrialisation device experts Institute substrate R&D offer offer 2005 2005 2005 2008 2010 2014 2015
FD-SOI substrate reached production maturity since 2013
Proven manufacturing capability on more than 70000 wafers +/-5Å top silicon uniformity specification met with CpK>1: all wafers, all points Differential Reflective Metrology defined to predict / protect variability on device Defectivity in line with foundry requirements >95% device wafer yield demonstrated at foundry Top silicon thickness Full wafer thickness deviation (Å) (41 points per wafer, ~15k wafers)
10/10/201755 SOITEC Confidential FD-SOI technology Thickness control >70 000 Wafers @ ± 1 Atomic Layer !
Silicon thickness uniformity is guaranteed to within just a few atomic layers:
+5Å
Target
-5Å Soitec FD-SOI wafer ±5Å ±1,4cm
10/10/2017 56 SOITEC Confidential FD-SOI technology Standard Smart-Cut™ process flow and FD-SOI specifics enabling ultra thin SOI film and BOX
High quality top wafer for thin SOI film compatibility
Adapted to thin BOX
Adapted to thin SOI film
Adapted to thin BOX
Adapted to thin SOI film
10/10/2017 57 SOITEC Confidential FD-SOI technology Efficient collaboration with equipment makers Example of FD-SOI roughness management
Enhanced smoothing with Kokusai batch Unique chip scale thickness measurement anneal technology developed with HSEB
FD-SOI Local Thickness Variability Within Wafer Uniformity DRM 6 σ (A) < 3.0 < 3.5 < 4.0 < 4.5 < 5.0 < 5.5 < 6.0 < 6.5 < 7.0 F.De Crecy – CEA/LETI HSEB Baldur tool > 7.0 Simulation of silicon smoothing under high temp anneal
〉 Tool customized with new deposit management 〉 Collaboration on Differential Reflective Metrology for SOI manufacturing development
〉 New tool redesign ongoing for enhanced flow 〉 Full map thickness measurement – a critical parameter for managment to achieve ultimate FD-SOI FD-SOI roughness & uniformity
10/10/201758 SOITEC Confidential FD-SOI technology A multi-nodes FD-SOI Product Roadmap
Target node 65FD 28FD 22FD 12FD Beyond 12FD
Box thick. 15nm 25nm 20nm 15 – 20nm ≤ 20nm
Top Si unif ± 1.0 nm ± 0.5 nm ± 0.5 nm ± 0.4 nm tbd FD-SOI Top Si thick. 30 nm 12 nm 12 nm 12 nm Pending device substrate Si Si Si Si Si / SiGe Top Si Mob. unstrained unstrained unstrained unstrained Strained / relaxed
Industrial Prod. Prod. Prod. Dev. R&D status
10/10/2017 59 SOITEC Confidential FD-SOI technology SOITEC FD-SOI wafer capacity
UP TO 1.5MWAFERS/YEAR CAPACITY WITHIN EXISTING FACTORY Phase 1 Phase 2 Phase 3 3Mw/y
1.5 Mw/y
500 Kw/y 100 Kw/y
Today +6 months +18 months Next Phase* Soitec Capacity only. Not taking into account SOITEC licensees Detailed Capex and Operational plans are defined for Bernin 2 (up to 500kw) and Singapore (up to 1Mw) Will be triggered in coordination with foundries demand
Phase 2: Singapore fab will get full qualification at customer level in first half 2019
Phase 3 (additional >1,5Mw) is in planning stage – different options (locations, partners) are being considered estimated time to qualified fab: 24 months timing will be coordinated with foundries
10/10/201760 SOITEC Confidential FD-SOI technology Summary
FD-SOI enables far better scalability and transistor characteristics than planar bulk V higher performance V lower power V better reliability V wider operating range through its back-bias capability FD-SOI is a simpler and cost-efficient process/design than other fully depleted approaches FD-SOI allows very strong differentiation in low power & 5G markets FD-SOI roadmap down to 12nm is already definded by foundry The value of FD-SOI is now recognized by fabless and is about to be introduced in high volume consumer products FD-SOI is enabled by SOITEC engineered substrates SOITEC has the capacitity to support multi-million wafers/year supply chain FD-SOI ecosystem is getting ready
10/10/201761 SOITEC Confidential FD-SOI technology THANK YOU
SOITEC Confidential FD-SOI technology 10/10/2017 62 Disclaimer
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10/10/201763 SOITEC Confidential FD-SOI technology