FD-SOI Technology Bich-Yen Nguyen Soitec Agenda 1 FD-SOI technology overview 2 Markets, foundries offers & ecosystems 3 FD-SOI material & roadmap 4 Summary 10/10/20172 SOITEC Confidential FD-SOI technology Challenge of Traditional Planar Bulk Transistor Scaling Source: IBM, T.C. Chen, ISSCC 2006 • Increased standby power dissipation • Amplified V variability th new transistor architectures and ⇒Impact Yield materials are needed ⇒Limit Vdd scaling 10/10/20173 SOITEC Confidential FD-SOI technology Continue Moore Law with New Materials & Device Architectures 2003 2005 2007 2009 2011 2012 Hartmann, GSA12 90nm 45 nm 22nm 65nm 32nm Strained Silicon Introduction of New High-K / Metal Gate Materials Introduction of New Fully Depleted Device Devices Architecture 10/10/20174 SOITEC Confidential FD-SOI technology Leakage Power is still a Major Issue Despite the Use of Hi-K Dielectric High-K/Metal Gate Stack Source: IBS SiON/Poly Gate Stack Technology node Leakage power is still tremendously growing after insertion of the High- K/MG gate stack at 28nm node as demands for more performance and functionality 10/10/20175 SOITEC Confidential FD-SOI technology New Device Architecture: Planar FDSOI or Multi-Gate Transistor Minimum Design Max Disruption scalability G G D SD S Buried OX S G D Bulk Si Bulk Si Buried oxide Conventional Planar Planar Single-or double Multiple-Gate, FinFET or Bulk Transistor Gate FDSOI Nanowire Transistor FDSOI : Fully Depleted Silicon-on Insulator Thin channel (Fully Depleted) with multi gates for better gate or short channel (SCE) control Better gate control ⇒ better transistors scaling 10/10/20176 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages UTBB FDSOI Transistor Advantages Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER • Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm Gate bias Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/20177 SOITEC Confidential FD-SOI technology FDSOI Device Physics Body factor: n = …1.05… in FDSOI; …1.5… in Bulk FDSOI Vg G Bulk/PDSOI Vg G Coxf S D Cox F S D Csi s1 Oxide F F Silicon Cdepl s Coxb s2 W 1 2 Linear current: I = µ C ()V − V V − n V D ox L G TH D 2 D 1 W 2 Saturation current: I = µ C (()V − V ) Dsat 2n ox L G TH kT Sub-threshold slope: S = n ln(10 ) q µ gm = 2 Cox W L Gain (strong inversion): VA VA ID n ID 10/10/20178 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages UTBB FDSOI Transistor Advantages Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER • Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm Gate bias Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/20179 SOITEC Confidential FD-SOI technology FD-SOI Transistor Level Benefits BULK FD-SOI Thin and excellent Gate uniformity SOI defined Gate channel Source Drain Source Top Si Drain BOX 2nd gate through ultra thin BOX Bulk wafer FD-SOI base wafer Vth and SCE defined by complex and heavily Vertical transistor layout determined by FD-SOI channel and halo doping techniques engineered substrate and undoped channel Large Vt mismatch due to random dopant Significant improved Vt mismatch due to fluctuation => limit Vdd scaling minimize random dopant fluctuation => enable Vd scaling down to 0.4V or lower Strong sensitivity to short channel effect Excellent SCE Large junction capacitance (Cj), GIDL and Didode leakage Minimum Cj, GIDL & diode leakages Limited well bias capability Extensive back bias capability 10/10/201710 SOITEC Confidential FD-SOI technology FD-SOI superior SER enables high reliability required applications FD-SOI = 20x SER CPU#1 Memory improvement vs. bulk CPU#2 28nm FD-SOI 28nm in FT/Mb in CPU#1 Memory SER CPU#2 “Attractive SEU resistance due to very low CPU#1 Neutron- charge collection volumes in FD-SOI” Memory ST Vendor A ST Vendor A ST ST Michael L. Alles Vanderbilt University, S3S conference, 2015 CPU#2 65nm 45nm 45nm 28nm 28nm 28nm Bulk Bulk Bulk Bulk Bulk FD-SOI Mobileye using STM FD-SOI 28nm technology for their 4th gen chipset ST, P. Magarshack, Shanghai FDSOI forum, 2015 10/10/201711 SOITEC Confidential FD-SOI technology Source: Automotive Product Group (APG) presentation,, Marco Monti FD-SOI Transistor Advantages UTBB FDSOI Transistor Advantages Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER • Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm Gate bias Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/201712 SOITEC Confidential FD-SOI technology FDSOI Structure by IBM- VLSI 2009 Insitu doped SiGe S/D: ⇒Lower S/D resistance ⇒Reduces parasitic capacitance B - SiGe Lg= 25nm Tsi= 6nm Tinv=1.6nm Ioff= 3nmA/um Ion-N=570um/um Ion-P=550uA/um Vdd=0.9v 13 BY Nguyen, Soitec Apr. 22, 2011 IBM: 28LP Bulk vs. FDSOI 20LP Parameter 28LP Bulk IBM et al. (*) ETSOI IBM et al. (**) Lg 30nm 22nm VDD 1V 1V nFET pFET nFET pFET Ion @ 660µA/µm 380µA/µm 760µA/µm 590µA/µm Ioff=300pA/um Ion @ 740µA/µm 420µA/µm 920µA/µm 880µA/µm Ioff = 1nA/um DIBL 120mV/V 130mV/V 85 mV/V 90 mV/V AVt 2mV.µm 1.25mV.µm VDD 1.1V Ion @ 920µA/um 525nA/µm 1100µA/µm 1050µA/µm Ioff=1nA/um, (*): IBM Alliance 28LP technology as reported at IEDM’09, F Arnaud et al. (**): ETSOI technology for 22/20LP from IBM Research, as reported at FDSOI workshop dec 2010. 10/10/201714 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages UTBB FDSOI Transistor Advantages Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER improvement • Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility boost • Scalable down to 10nm Gate bias Back Bias Conventional planar • Lower manufacturing risk processing • Equivalent bulk design UTBB: Ultra-Thin Body and BOX 10/10/201715 SOITEC Confidential FD-SOI technology SOI value: part of device integrated by substrate engineering Optimized SOI wafers provide excellent silicon geometry control To make the best of FD technology FD-SOI transistor Soitec FD-2D wafer Ultra-Thin Top Silicon Layer SDG Ultra-Thin Buried Oxide Base Silicon Critical dimension: Enables: Critical dimension: Top Si thickness channel thickness 10/10/201716 SOITEC Confidential FD-SOI technology FDSOI Uniformity: Lowest VT variability m) µ (mV. vt A ±2.6A, 2mm EE- 721 pts F5X inspection Gate Length (nm) Cheng et. Al. IBM IEDM 2009 Record and reproducible low A VT of 1.25mV. µm @ Lg=25nm (32/28nm GR) B.Doris et al., FD ‐Workshop at SFO, 2012 10/10/201717 SOITEC Confidential FD-SOI technology Planar Bulk vs FDSOI Vt Variation V t V ariation 0.03 0.025 Retrograde Bulk 0.02 0.015 sigma Vt (V) Vt sigma FDSOI 0.01 0.005 0 5 15 25 35 45 Lg(nm) FDSOI shows best results S O I Retro Bulk in Uniformvariation Bulk (throughout gate length) Source: UCB/Soitec , SOI 2009 Conference 50-60% Vt variation improvement by using undoped channel retains with technology scaling 10/10/201718 SOITEC Confidential FD-SOI technology Single Port 4Mb SRAM: No Back Bias VImproved memory minimum voltage 28nm LP Bulk vs 28nm FDSOI from STMicroelectronics (gate-first HKMG Technology) 10/10/201719 SOITEC Confidential FD-SOI technology 10/10/201720 SOITEC Confidential FD-SOI technology C2 - Confidential FDSOI for RF & Analog Beyond 28nm Bulk FDSOI key analog differentiations Higher Analog Performance vs Bulk Lower variability than bulk FDSOI Lower Capacitance enabling higher frequency Lower Phase noise Remaining planar On the fly Vt tuning New circuit topology enabler : double gate transistor Analog : VT, Fmax, Gm, Ioff, …. Bulk CMOS Ideal for next generations transceivers and SoC Vgs Gain @ Lmin Gain @ Id Variability (Undoped Channel) Fmax > 300Ghz 10/10/201721 SOITEC Confidential FD-SOI technology FD-SOI Transistor Advantages UTBB FDSOI Transistor Advantages Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage • Latch-up immunity Ultra thin Body • Excellent SCE (SS, DIBL) • No History Effect • Lower SER • Improved V T variability No channel doping • Improved mismatch (SRAM & analog) • Better analog gain • Reduced process cost Courtesy of STM Body Biasing Ultra thin BOX option • Enables Extended body biasing Knobs to control Perf/Power: Channel mobility